Datasheet

73S1215F Data Sheet DS_1215F_003
USR[7:0] Control
USRxINTSrc set to
4(ext INT0 high)
or
6(ext INT0 low)
1
0
INT5
INT4
RESETB
TC
CLR
9 BIT CNTR
RESETB
CE
PDMUX
(FF94h:bit7)
MPU
INT0
PWRDN_analogQ
CLR
D
PWRDN
(FFF1h:bit7)
USR0
USR6
USR1
USR2
USR3
USR4
USR5
USR7
TC
CE
CLR
5 BIT CNTR
Notes:
1. The counters are clocked by the MPUCLK
2. TC - Terminal count (high at overflow)
3. CE - Count enable
RESETB
Figure 6: Detail of Power Down Interrupt Logic
28 Rev. 1.4
PWRDN BIT
PWRDN SIG
EXT. EVENT
INT0 to MPU
MPU STOP
ANALOG Enable
PLL CLOCKS
t1
t2
t3
t4
t5
t6
t0
t7
t0: MPU sets PWRDN bit
t1: 32 MPU clock cycles after t0, the PWRDN SIG is asserted, turning all analog functions OFF.
t2: MPU executes STOP instruction, must be done prior to t1.
t3: Analog functions go to OFF condition. No Vref, PLL/VCO, Ibias, etc.
text
text: An external event (RTC, Keypad, Card event, USB) occurs.
t4: PWRDN bit and PWRDN signal are cleared by external event.
t5: High-speed oscillator/PLL/VCO operating.
t6: After 512 MPU clock cycles, INT0 to MPU is asserted.
t7: INT0 causes MPU to exit STOP condition.
Figure 7: Power Down Sequencing