Datasheet

DS_1215F_003 73S1215F Data Sheet
Rev. 1.4 47
Timer/Counter Control Register (TCON): 0x88 Å 0x00
Table 43: The TCON Register
MSB LSB
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Bit Symbol Function
TCON.7 TF1
The Timer 1 overflow flag is set by hardware when Timer 1 overflows.
This flag can be cleared by software and is automatically cleared when
an interrupt is processed.
TCON.6 TR1 Timer 1 Run control bit. If cleared, Timer 1 stops.
TCON.5 TF0
Timer 0 overflow flag set by hardware when Timer 0 overflows. This
flag can be cleared by software and is automatically cleared when an
interrupt is processed.
TCON.4 TR0 Timer 0 Run control bit. If cleared, Timer 0 stops.
TCON.3 IE1 External Interrupt 1 edge flag.
TCON.2 IT1 External interrupt 1 type control bit.
TCON.1 IE0 External Interrupt 0 edge flag.
TCON.0 IT0 External Interrupt 0 type control bit.
1.7.6 WD Timer (Software Watchdog Timer)
The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles.
After a reset, the watchdog timer is disabled and all registers are set to zero. The watchdog consists of a
16-bit counter (WDT), a reload register (WDTREL), prescalers (by 2 and by 16), and control logic. Once
the watchdog starts, it cannot be stopped unless the internal reset signal becomes active.
Note: It is recommended to use the hardware watchdog timer instead of the software watchdog
timer (refer to the RTC description).
WD Timer Start Procedure: The WDT is started by setting the SWDT flag. When the WDT register
enters the state 0x7CFF, an asynchronous WDTS signal will become active. The signal WDTS sets bit 6
in the IP0 register and requests a reset state. WDTS is cleared either by the reset signal or by changing
the state of the WDT timer.
Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request
signal from becoming active. This requirement imposes an obligation on the programmer to issue two
instructions. The first instruction sets WDT and the second instruction sets SWDT. The maximum delay
allowed between setting WDT and SWDT is 12 clock cycles. If this period has expired and SWDT has
not been set, WDT is automatically reset, otherwise the watchdog timer is reloaded with the content of
the WDTREL register and WDT is automatically reset.