Datasheet

73S1215F Data Sheet DS_1215F_003

56 Rev. 1.4

External Interrupt Control Register (INT6Ctl): 0xFF95 Å 0x00

Table 61: The INT6Ctl Register

MSB LSB

– – VFTIEN VFTINT I2CIEN I2CINT ANIEN ANINT

Bit Symbol Function

INT6Ctl.7 –

INT6Ctl.6 –

INT6Ctl.5 VFTIEN VDD fault interrupt enable.

INT6Ctl.4 VFTINT VDD fault interrupt flag.

INT6Ctl.3 I2CIEN I

C interrupt enabled.

INT6Ctl.2 I2CINT I

C interrupt flag.

INT6Ctl.1 ANIEN

If ANIEN = 1 Analog Compare event interrupt is enabled. When

masked (ANIEN = 0), ANINT (bit 0) may be set, but no interrupt is

generated.

INT6Ctl.0 ANINT

(Read Only) Set when the selected ANA_IN signal changes with

respect to the selected threshold if Compare_Enable is asserted.

Cleared on read of register.