Datasheet

73S1215F Data Sheet DS_1215F_003
92 Rev. 1.4
Card Status/Control Register (CRDCtl): 0xFE05 Å 0x00
This register is used to configure the card detect pin (DETCARD) and monitor card detect status. This
register be written to properly configure Debounce, Detect_Polarity (= 0 or = 1), and the pull-up/down
enable before setting CDETEN. The card detect logic is functional even without smart card logic clock.
When the PWRDN bit is set = 1, no debounce is provided but card presence is operable.
MSB LSB
DEBOUN CDETEN – – DETPOL PUENB PDEN CARDIN
Bit Symbol Function
CRDCtl.7 DEBOUN
Debounce – When set = 1, this will enable hardware de-bounce
of the card detect pin. The de-bounce function shall wait for
64ms of stable card detect assertion before setting the CARDIN
bit. This counter/timer uses the keypad clock as a source of
1kHz signal. De-assertion of the CARDIN bit is immediate upon
de-assertion of the card detect pin(s).
CRDCtl.6 CDETEN
Card Detect Enable – When set = 1, activates card detection
input. Default upon power-on reset is 0.
CRDCtl.5 –
CRDCtl.4 –
CRDCtl.3 DETPOL
Detect Polarity – When set = 1, the DETCARD pin shall interpret
a logic 1 as card present.
CRDCtl.2 PUENB Enable pull-up current on DETCARD pin (active low).
CRDCtl.1 PDEN Enable pull-down current on DETCARD pin.
CRDCtl.0 CARDIN
Card Inserted – (Read only). 1 = card inserted, 0 = card not
inserted. A change in the value of this bit is a “card event.” A
read of this bit indicates whether smart card is inserted or not
inserted in conjunction with the DETPOL setting.