Datasheet

DS_8010C_024 73S8010C Data Sheet
Rev. 1.5 13
9 Deactivation Sequence
Deactivation is initiated either by the system controller resetting the Start/Stop bit, or automatically in the
event of hardware faults. Hardware faults are over-current, over-temperature, V
DD
fault, V
CC
fault, and
card extraction during the session.
The following steps and Figure 7 show the deactivation sequence and the timing of the card control
signals when the system controller clears the Start/Stop bit:
1. RST goes low at the end of t
1
.
2. CLK goes low at the end of t
2
.
3. I/O goes low at the end of t
3
. Out of reception mode.
4. Shut down V
CC
at the end of time t
4
.
Figure 7: Deactivation Sequence
10 Interrupt
The interrupt is an active low interrupt. It is set low if either a V
CC
fault or a V
DD
fault is detected. It is also
set low if one of the following status bit conditions is detected:
 Early ATR
 Mute ATR
 Card insert or card extract
 Protection status from Over-current or Over-heating
If the interrupt is set low by the detection of these status bits, then the interrupt is set high when these
status bits are read. (READ STATUS DONE)
Figure 8: FAULT Functions, INT operation
t
1
≥ 0.5 μs t
3
≥ 0.5 μs
t
2
≥ 7.5 μs t
4
≥ 0.5 μs
INT
ANY FAULT
STATUS BITS
READ STATUS DONE