Datasheet

73S8010R Data Sheet DS_8010R_022
14 Rev. 1.6
3.2 System Controller Interface (I
2
C Bus)
A fast-mode 400 kHz I
2
C bus slave interface is used for controlling the 73S8010R device and reading the
status of the device via the data pin SDA and clock pin SCL. The bus has 3 address select pins, SAD0,
SAD1, and SAD2. This allows up to 8 devices to be connected in parallel. Table 9 lists the device
address selections for the SAD2:0 settings.
Table 9: Device Address Selection
SAD2 SAD1 SAD0
(7 bit) I
2
C
Address
0 0 0 0x40
0 0 1 0x42
0 1 0 0x44
0 1 1 0x46
1 0 0 0x48
1 0 1 0x4A
1
1
0
0x4C
1
1
1
0x4E
Bit 0 of the I
2
C address is the R/W bit. Refer to Figure 5 and Figure 6 for usage.
Table 10 describes the Control Register Bits.
Table 10: Control Register Description
Power-on-reset value = 0x00
Name Bit Description
Start/Stop 0 When set, initiates an activation and a cold reset procedure; when reset,
initiates a deactivation sequence.
Warm reset 1 When set, initiates a warm reset procedure; automatically reset by hardware
when the card starts answering or when the card is declared mute.
5 V and 3 V 2 When set, V
CC
= 3 V; when reset, V
CC
= 5 V. When de-activating (setting bit
0 = 0) and operating with 3 V (bit 2 =1), do not simultaneously set bit 2 =0.
Clock Stop 3 When set, the card clock is stopped. Bit 4 determines the card clock stop
level.
Clock Stop Level 4 When set, card clock stops high; when reset card clock stops low.
Clksel1 5 Bits 5 and 6 determine the clock rate to the card. See Table 11 for more
details.
Clksel2 6
I/O enable 7 I/O enable bit. When set, I/O is transferred on I/OUC; when reset I/O to
I/OUC is high impedance.
Table 11: Card Clock Rate Selection
Bit Clksel2 Bit Clksel1 Card Clock
0 0 Clkin/8
0 1 Clkin/4
1 0 Clkin/2
1 1 Clkin (Xtalin)