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73S8024RN

Low-Cost Smart Card Interface

DATA SHEET

Rev. 2 1

19-5404; Rev 2; 6/12

DESCRIPTION

The 73S8024RN is a single smart card (ICC) interface IC

that can be controlled by a dedicated control bus. The

73S8024RN has been designed to provide full electrical

compliance with ISO 7816-3, EMV 4.0 (EMV2000) and

NDS specifications.

Interfacing with the system controller is done through a

control bus, composed of digital inputs to control the

interface, and one interrupt output to inform the system

controller of the card presence and faults.

The card clock can be generated by an on-chip oscillator

using an external crystal or by connection to a clock

signal.

The 73S8024RN incorporates an ISO 7816-3

activation/deactivation sequencer that controls the card

signals. Level-shifters drive the card signals with the

selected card voltage (3V or 5V), coming from an internal

Low Drop-Out (LDO) voltage regulator. This LDO

regulator is powered by a dedicated power supply input

. Digital circuitry is separately powered by a digital

power supply V

With its embedded LDO regulator, the 73S8024RN is a

cost effective solution for any application where a 5V

(typically -5% +10%) power supply is available.

Hardware support for auxiliary I/O lines, C4 / C8 contacts,

is provided*.

Emergency card deactivation is initiated upon card

extraction or upon any fault generated by the protection

circuitry. The fault can be a card over-current, a V

(digital power supply)**, a V

(regulator power supply), a

(card power supply) or an over-heating fault.

The card over-current circuitry is a true current detection

function, as opposed to V

voltage drop detection, as

usually implemented in ICC interface ICs.

The V

voltage fault has a threshold voltage that can be

adjusted with an external resistor or resistor network. It

allows automated card deactivation at a customized V

voltage threshold value. It can be used, for instance, to

match the system controller operating voltage range.

APPLICATIONS

• Set-Top-Box Conditional Access and Pay-per-

View

• Point of Sales and Transaction Terminals

• Control Access and Identification

* Pins/functions not available on 20-pin QFN package.

** User V

DD_FLT

threshold configuration not available on

20-pin QFN package.

ADVANTAGES

• Traditional step-up converter is replaced by a LDO

regulator:

 Greatly reduced power dissipation

 Fewer external components are required

 Better noise performance

 High current capability (90mA supplied to the card)

• SO28 package is pin-to-pin compatible with

industry-standard TDA8004 and TDA8024

• Card clock STOP (high and low) mode

• Small format (4x4x0.85mm) 20QFN package option

• True card over-current detection

FEATURES

• Card Interface:

 Complies with ISO 7816-3, EMV 4.0, and NDS

 An LDO voltage regulator provides 3V / 5V to the

card from an external power supply input

 Provides at least 90mA to the card

 ISO 7816-3 Activation / Deactivation sequencer with

emergency automated deactivation on card removal

or fault detected by the protection circuitry

 Protection includes 3 voltage supervisors that detect

voltage drops on V

(card), V

(digital)**, and V

(regulator) power supplies

 The V

voltage supervisor threshold value can be

externally adjusted**

 Over-current detection 150mA max

 Card clock stop high or low*

 2 card detection inputs, 1 for each possible user

polarity

 Auxiliary I/O lines, for C4 / C8 contact signals*

 Card CLK clock frequency up to 20MHz

• System Controller Interface:

 3 D

igital inputs control the card activation /

deactivation, card reset and card voltage

 4 Digital inputs control the card clock (division rate

and card clock stop modes)

 1 Digital output, interrupt to the system controller,

allows the system controller to monitor the card

presence and faults.

 Crystal oscillator or host clock, up to 27MHz

• Regulator Power Supply:

 4.75V to 5.5V (EMV 4.0)

 4.85V to 5.5V (NDS)

• Digital Interfacing: 2.7V to 5.5V

• ±6kV ESD Protection on the card interface

• Package: SO28, 20QFN or 32QFN

Summary of content (27 pages)

PAGE 1
9-5404; Rev 2; 6/12 73S8024RN Low-Cost Smart Card Interface DATA SHEET DESCRIPTION ADVANTAGES • The 73S8024RN is a single smart card (ICC) interface IC that can be controlled by a dedicated control bus. The 73S8024RN has been designed to provide full electrical compliance with ISO 7816-3, EMV 4.0 (EMV2000) and NDS specifications.
PAGE 2
73S8024RN Data Sheet DS_8024RN_020 FUNCTIONAL DIAGRAM NC VDDF_ADJ VDD 21 [20] {12} VPC 5 [2,9,16,25,32] 18 [17] 6 6 [3] {2} VPC FAULT DIGITAL POWER SUPPLY VDD VOLTAGE SUPERVISOR VOLTAGE REFERENCE {13} [21] 22 GND VDD FAULT VCC FAULT ICC FAULT {10} [18] 19 Int_Clk CMDVCC {11} [19] 20 RSTIN {20} [31] 3 5V/3V {14} [22] 23 OFF DIGITAL CIRCUITRY & FAULT LOGIC {18} [29] 1 CLKDIV1 {19} [30] 2 CLKDIV2 {15} [23] 24 XTALIN {16} [24] 25 XTALOUT [4] 7 CLKSTOP [5] 8 CLKLEV {17} [26] 26 I/OUC [27] AUX1
PAGE 3
DS_8024RN_020 73S8024RN Data Sheet Table of Contents 1 Pin Description ...............................................................................................................................5 2 System Controller Interface ...........................................................................................................7 3 Power Supply and Voltage Supervision ........................................................................................8 4 Card Power Supply ...............
PAGE 4
73S8024RN Data Sheet DS_8024RN_020 Figures Figure 1: 73S8024RN Block Diagram ...................................................................................................... 2 Figure 2: Activation Sequence – RSTIN Low When CMDVCC Goes Low .............................................. 10 Figure 3: Activation Sequence – RSTIN High When CMDVCCB Goes Low ........................................... 11 Figure 4: Deactivation Sequence .......................................................................
PAGE 5
DS_8024RN_020 1 73S8024RN Data Sheet Pin Description CARD INTERFACE Name Pin 28SO 11 Pin 20QFN 5 AUX1 13 – AUX2 12 – RST CLK 16 15 8 7 PRES 10 4 PRES 9 3 VCC 17 9 GND 14 6 I/O Pin Description 32QFN 8 Card I/O: Data signal to/from card. Includes a pull-up resistor to VCC. 11 AUX1: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC. 10 AUX2: Auxiliary data signal to/from card. Includes a pull-up resistor to VCC.
PAGE 6
73S8024RN Data Sheet DS_8024RN_020 MICROCONTROLLER INTERFACE Name Pin 28SO 19 Pin 20QFN 10 5V/#V 3 20 CLKSTOP 7 – CLKLVL 8 – CLKDIV1 CLKDIV2 1 2 18 19 CMDVCC Pin Description 32QFN 18 Command VCC (negative assertion): Logic low on this pin causes the LDO regulator to ramp the VCC supply to the card and initiates a card activation sequence, if a card is present. 31 5 volt / 3 volt card selection: Logic one selects 5 volts for VCC and card interface, logic low selects 3 volt operation.
PAGE 7
DS_8024RN_020 73S8024RN Data Sheet 2 System Controller Interface Three separated digital inputs allow direct control of the card interface from the host as follows: • Pin CMDVCC: When low, starts an activation sequence. • Pin RSTIN: controls the card Reset signal (when enabled by the sequencer). • Pin 5V/#V: Defines the card voltage.
PAGE 8
73S8024RN Data Sheet DS_8024RN_020 3 Power Supply and Voltage Supervision The 73S8024RN smart card interface IC incorporates a LDO voltage regulator. The voltage output is controlled by the digital input 5V/#V. This regulator is able to provide either 3V or 5V card voltage from the power supply applied on the VPC pin. Digital circuitry is powered by the power supply applied on the VDD pin. VDD also defines the voltage range to interface with the system controller.
PAGE 9
DS_8024RN_020 73S8024RN Data Sheet 4 Card Power Supply The card power supply is internally provided by the LDO regulator, and controlled by the digital ISO 7816-3 sequencer. Card voltage selection is carried out by the digital input 5V/#V. Choice of the VCC Capacitor: Depending on the applications, the requirements in terms of both VCC minimum voltage and transient currents that the interface must be able to provide to the card are different.
PAGE 10
73S8024RN Data Sheet DS_8024RN_020 7 Activation Sequence The 73S8024RN smart card interface IC has an internal 10ms delay at power on reset or on the application of VDD > VDDF. No activation is allowed at this time. The CMDVCC (edge triggered) must then be set low to activate the card. In order to initiate activation, the card must be present; there can be no over-temperature fault or no VDD fault.
PAGE 11
DS_8024RN_020 73S8024RN Data Sheet The following steps show the activation sequence and the timing of the card control signals when the system controller pulls the CMDVCC low while the RSTIN is high: • • • • • CMDVCC is set low. Next, the internal VCC control circuit checks the presence of VCC at the end of t1. In normal operation, the voltage VCC to the card becomes valid during this time. If not, OFF goes low to report a fault to the system controller, and the power VCC to the card is shut down.
PAGE 12
73S8024RN Data Sheet DS_8024RN_020 8 Deactivation Sequence Deactivation is initiated either by the system controller by setting the CMDVCC high, or automatically in the event of hardware faults. Hardware faults are over-current, overheating, VDD fault, VPC fault, VCC fault, and card extraction during the session. To be noted that VPC and VCC faults are linked together so that a fault is generated when VPC goes lower than VCC.
PAGE 13
DS_8024RN_020 73S8024RN Data Sheet 9 OFF and Fault Detection There are two different cases that the system controller can monitor the OFF signal: to query regarding the card presence outside card sessions, or for fault detection during card sessions. Outside a card session: In this condition, CMDVCC is always high, OFF is low if the card is not present, and high if the card is present. Because it is outside a card session, any fault detection will not act upon the OFF signal.
PAGE 14
73S8024RN Data Sheet DS_8024RN_020 Neutral State No I/O reception Yes I/O & not I/OUC No Yes No I/OUC & not I/O Yes I/OUC in I/OICC in No No I/OUC I/O yes yes Figure 6: I/O and I/OUC State Diagram I/O I/OUC tI/O_HL Delay from I/O to I/OUC: Delay from I/OUC to I/O: tI/O_LH tI/O_HL = 100ns tI/OUC_HL = 100ns tI/OUC_HL tI/OUC_LH tI/O_LH = 25ns tI/OUC_LH = 25ns Figure 7: I/O – I/OUC Delays Timing Diagram 14 Rev.
PAGE 15
DS_8024RN_020 73S8024RN Data Sheet 11 Typical Application Schematic AUX2UC_to/from_uC AUX1UC_to.
PAGE 16
73S8024RN Data Sheet DS_8024RN_020 12 Electrical Specification 12.1 Absolute Maximum Ratings Operation outside these rating limits may cause permanent damage to the device. The smart card interface pins are protected against short circuits to VCC, ground, and each other. Parameter Rating Supply Voltage VDD -0.5 to 6.0 VDC Supply Voltage VPC -0.5 to 6.0 VDC Input Voltage for Digital Inputs -0.3 to (VDD +0.5) VDC Storage Temperature -60 to 150°C Pin Voltage (except card interface) -0.
PAGE 17
DS_8024RN_020 73S8024RN Data Sheet 12.4 Smart Card Interface Requirements Symbol Parameter Condition Min Typ Max Unit -0.1 0.1 V -0.1 0.4 V 4.60 5.25 V 4.75 5.25 V 4.55 2.80 5.25 3.2 V V 4.6 5.25 V 2.76 3.2 V 4.6 5.25 V 4.65 5.25 V 2.76 3.2 V 350 65 mV mA 90 mA Card Power Supply (VCC) Regulator General conditions, -40°C < T < 85°C, 4.75v < VPC < 5.5v, 2.7v < VDD < 5.5v NDS conditions, 4.85v < VPC < 5.
PAGE 18
73S8024RN Data Sheet Symbol Parameter DS_8024RN_020 Condition Min Typ Max Unit Interface Requirements – Data Signals: I/O, AUX1, AUX2, and host interfaces: I/OUC, AUX1UC, AUX2UC. ISHORTL, ISHORTH, and VINACT requirements do not pertain to I/OUC, AUX1UC, and AUX2UC.
PAGE 19
DS_8024RN_020 Symbol 73S8024RN Data Sheet Parameter Condition Min IOH =-200µA IOL=200µA IOL = 0 IOL = 1mA 0.9 VCC 0 Vcc = 3V Vcc = 5V CL = 35pF for CLK, 10% to 90% CL = 200pF for RST, 10% to 90% CL =35Pf, FCLK ≤ 20MHz 0.3 0.5 Typ Max Unit VCC 0.3 V V 0.1 0.3 30 70 V V mA mA V/ns V/ns 8 ns 100 ns 55 % Max Unit 0.8 VDD + 0.3 0.45 V V V V 24 kΩ -5 5 μA -0.3 0.7 VDD 0.3 VDD VDD+0.
PAGE 20
73S8024RN Data Sheet DS_8024RN_020 12.6 DC Characteristics Symbol Parameter IDD Supply Current IPC Supply Current IPCOFF VPC supply current when VCC = 0 Condition Min Typ Max Unit 2.7 7.0 mA VCC on, ICC=0 I/O, AUX1, AUX2=high, Clock not toggling 450 650 µA CMDVCC High 345 550 µA Typ Max Unit 2.4 V 12.
PAGE 21
DS_8024RN_020 73S8024RN Data Sheet 13 Mechanical Drawing (20QFN) 0.85 NOM / 0.90 MAX 0.02 NOM / 0.05 MAX 0.20 REF 4.0 2.0 20 1 2 4.0 2.0 SEATING PLANE SIDE VIEW TOP VIEW 0.18 / 0.30 2.50 / 2.70 1.25 / 1.35 0.20 MIN 0.18 / 0.30 2.50 / 2.70 2 K 1.25 / 1.35 1 0.35 / 0.45 PIN #1 ID R 0.20 20 19 0.50 0.20 MIN BOTTOM VIEW Figure 9: 20QFN Mechanical Drawing Rev.
PAGE 22
73S8024RN Data Sheet DS_8024RN_020 CLKDIV1 I/OUC XTALOUT 17 16 CAUTION: Use handling procedures necessary for a static sensitive component 18 19 CLKDIV2 20 5V/#V 14 Package Pin Designation (20QFN) GND 1 15 XTALIN VPC 2 14 OFF PRES 3 13 GND PRES 4 12 VDD I/O 5 11 RSTIN 6 7 8 9 10 GND CLK RST VCC CMDVCC TERIDIAN 8024RN Figure 10: 20QFN Pin Out 22 Rev.
PAGE 23
DS_8024RN_020 73S8024RN Data Sheet 15 Mechanical Drawing (32QFN) 5 2.5 0.85 NOM./ 0.9MAX. 0.00 / 0.005 0.20 REF. 1 2.5 2 3 5 TOP VIEW SEATING PLANE 0.35 / 0.45 SIDE VIEW 3.0 / 3.2 0.18 / 0.3 CHAMFERED 0.30 1.5 / 1.6 1 2 3 3.0 / 3.2 0.25 1.5 / 1.6 0.5 0.2 MIN. 0.35 / 0.45 0.5 0.25 BOTTOM VIEW Figure 11: 32QFN Mechanical Drawing Rev.
PAGE 24
73S8024RN Data Sheet DS_8024RN_020 16 Package Pin Designation (32QFN) NC 5V/#V CLKDIV2 CLKDIV1 AUX2UC AUX1UC I/OUC NC 32 31 30 29 28 27 26 25 CAUTION: Use handling procedures necessary for a static sensitive component GND 1 24 XTALOUT NC 2 23 XTALIN VPC 3 22 OFF CLKSTOP 4 21 GND CLKLVL 5 20 VDD PRES 6 19 RSTIN PRES 7 18 CMDVCC I/O 8 17 VDDF_ADJ 10 11 12 13 14 15 16 AUX2 AUX1 GND CLK RST VCC NC NC 9 TERIDIAN S8024RN Figure 12: 32QFN Pin Out
PAGE 25
DS_8024RN_020 73S8024RN Data Sheet 17 Mechanical Drawing (SO) .050 TYP. (1.270) .305 (7.747) .285 (7.239) PIN NO. 1 BEVEL .715 (18.161) .695 (17.653) .420 (10.668) .390 (9.906) .0115 (0.29) .003 (0.076) .110 (2.790) .092 (2.336) .016 nom (0.40) .335 (8.509) .320 (8.
PAGE 26
73S8024RN Data Sheet DS_8024RN_020 19 Ordering Information Part Description Order No.
PAGE 27
DS_8024RN_020 73S8024RN Data Sheet Revision History Revision Date Description 1.1 5/18/2004 1.2 11/5/2004 1.3 4/27/2005 1.4 7/15/2005 1.5 8/23/2005 1.6 12/5/2007 Removes leaded package options, replaces 32QFN punched with SAWN mechanical dimensions, update 28SO package dimensions. 1.7 1/17/2008 Changed dimension of bottom exposed pad on 32QFN mechanical package figure. 1.8 1/19/2009 In Figure 1, modified the device block diagram to make pin 2 a no connect.