Datasheet

78M6610+PSU Data Sheet
5.5 Timing Specifications
5.5.1 RESET
Parameter
Condition
Min
Typ
Max
Unit
Reset pulse fall time
–
1
1
–
µs
Reset pulse width – 5
1
–
µs
1
Guaranteed by design, not subject to test.
5.5.2 SPI Slave Port
Parameter Condition Min Typ Max Unit
t
SPIcyc
SCK cycle time 1
– –
µs
t
SPILead
Enable lead time 15 – – ns
t
SPILag
Enable lag time 0 – – ns
t
SPIW
SCK pulse width:
High
Low
250
250
– – ns
ns
t
SPISCK
SSB to first SCK fall Ignore if SCK is low
when SSB falls.
– 2
1
–
ns
t
SPIDIS
Disable time – 0
1
– ns
t
SPIEV
SCK to Data Out (SDO) – 25 ns
t
SPISU
Data input setup time (SDI) 10 – – ns
t
SPIH
Data input hold time (SDI) 5 – – ns
1
Guaranteed by design, not subject to test.
MSB OUT LSB OUT
MSB IN LSB IN
t
SPIcyc
t
SPILead
t
SPILag
t
SPISCK
t
SPIH
t
SPIW
t
SPIEV
t
SPIW
t
SPIDIS
SSB
SCK
SDI
SDO
t
SPISU
Figure 5-1: SPI Slave Port Timing
58 Rev 3