Datasheet

78M6610+PSU Data Sheet
1.2 Power-On Reset, WD Timer, and Reset Circuitry
Power-On Reset (POR)
An on-chip Power-On Reset (POR) block monitors the supply voltage (V
3P3D
) and initializes the internal
digital circuitry at power-on. Once V
3P3D
is above the minimum operating threshold, the POR circuit
triggers and initiates a reset sequence. It will also issue a reset to the digital circuitry if the supply voltage
falls below the minimum operating level.
Watchdog Timer (WDT)
A Watchdog Timer (WDT) block detects any software processing errors. The embedded software
periodically refreshes the free-running watchdog timer to prevent it from timing out. If the WDT times out,
it is an indication that software is no longer being executed in the intended sequence; thus, a system
reset is initiated.
External Reset Pin (RESET Pin)
The 24-pin QFN package provides a dedicated reset (RESET) pin. In addition to the internal sources, a
reset can be forced by applying a low level to the RESET pin.
If the RESET pin is pulled low, all digital activities in the device stop, except the clock management
circuitry and oscillators, which continue to run. The external reset input is filtered to prevent spurious reset
events in noisy environments. The reset does not occur until RESET has been held low for at least 1 µs.
Once initiated, the reset mode persists until the RESET is set high and the reset timer times out (4096
clock cycles). At the completion of the reset sequence, the internal reset is released and the processor
(EMP) begins executing from address 0.
If not used, the RESET pin can be connected either directly or through a pull-up resistor to V
3P3D
supply.
A simple connection diagram is shown in Figure 1-3
.
GNDD
V
3P3D
RESET
1nF
10KΩ
V
3P
3
GND
Manual
Reset Switch
GNDD
V
3P3D
RESET
V
3
P3
GND
78M6610+PSU/B 78M6610+PSU/B
a) RESET External Connection Example
b) Unused RESET Connection Example
Figure 1-3: RESET Pin Connections
Rev 3 7