Datasheet

78M6612 Data Sheet DS_6612_001
12 Rev 2
1.5.3 Real-Time Clock (RTC)
The RTC is driven directly by the crystal oscillator. The RTC consists of a counter chain and output
registers. The counter chain consists of seconds, minutes, hours, day of week, day of month, month, and
year. The RTC is not supported in all firmware libraries. Contact Maxim support for more information.
1.5.4 Temperature Sensor
The device includes an on-chip temperature sensor for determining the temperature of the bandgap
reference. The MPU may request an alternate multiplexer frame containing the temperature sensor
output by asserting MUX_ALT. The primary use of the temperature data is to determine the magnitude of
compensation required to offset the thermal drift in the system (see Section 3.4 Temperature
Compensation).
1.5.5 Flash Memory
The 78M6612 includes 32 KB of on-chip Flash memory. The Flash memory primarily contains MPU and
CE program code. It also contains images of the CE DRAM, MPU RAM, and I/O RAM. On power-up,
before enabling the CE, the MPU copies these images to their respective locations.
The Flash memory is segmented into individually erasable 1024-byte pages. Flash space allocated for the CE
program is limited to 1024 words (2 KB). The CE program must begin on a 1-KB boundary of the Flash address
space.
Flash Write Procedures
The MPU has the ability to write to the Flash memory when the CE is disabled. As an alternative to using Flash, a
small EEPROM can store data without compromises. EEPROM interfaces are included in the device.
Updating Individual Bytes in Flash Memory
The original state of a Flash byte is 0xFF (all ones). Once a value other than 0xFF is written to a Flash memory cell,
overwriting with a different value usually requires that the cell be erased first. Since cells cannot be erased
individually, the page has to be copied to RAM, followed by a page erase. After this, the page can be updated in
RAM and then written back to the Flash memory.
Flash Erase Procedures
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence. These special
pattern/sequence requirements prevent inadvertent erasure of the Flash memory.
The mass erase sequence is:
1. Write 1 to the FLSH_MEEN bit (SFR address 0xB2[1].
2. Write pattern 0xAA to FLSH_ERASE (SFR address 0x94).
The mass erase cycle can only be initiated when the ICE port is enabled.
The page erase sequence is:
1. Write the page address to FLSH_PGADR (SFR address 0xB7[7:1].
2. Write pattern 0x55 to FLSH_ERASE (SFR address 0x94).