Datasheet

DS_6612_001 78M6612 Data Sheet

Rev 2 17

1.5.10 Hardware Watchdog Timer

In addition to the basic watchdog timer included in the 80515 MPU, an

independent, robust, fixed-duration, watchdog timer (WDT) is included in

the device. It uses the crystal oscillator as its time base and must be

refreshed by the MPU firmware at least every 1.5 seconds. When not

refreshed on time the WDT overflows, and the part is reset as if the

RESET pin were pulled high, except that the I/O RAM bits will be

maintained. 4096 oscillator cycles (or 125 ms) after the WDT overflow,

the MPU will be launched from program address 0x0000. Asserting

ICR_E will deactivate the WDT.

The WDT can also be disabled by tying the V1 pin to V3P3. Of course,

this also deactivates V1 power fault detection. Since there is no method

in firmware to disable the crystal oscillator or the WDT, it is guaranteed

that whatever state the part might find itself in, upon WDT overflow, the

part will be reset to a known state.

Figure 4: Functions Defined by V1

1.5.11 Test Ports (TXUXOUT pin)

One out of 16 digital or 8 analog signals can be selected to be output on the TMUXOUT pin. The

function of the multiplexer is described in the applicable firmware documentation.

V3P3

V3P3 -

400mV

V3P3 - 10mV

VBIAS

Battery

modes

Normal

operation,

WDT

enabled

WDT dis-

abled