Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsClock & Timing ICsSOIC 16 W

1 of 16 070505

FEATURES

§ Step sizes of 0.25 ns, 0.5 ns, 1 ns, 2 ns, 5 ns

§ On-chip reference delay

§ Configurable as delay line, pulse width

modulator, or free-running oscillator

§ Can delay clocks by a full period or more

§ Guaranteed monotonicity

§ Parallel or serial programming

§ Single 5V supply

§ 16-pin DIP or SOIC package

PIN ASSIGNMENT

PIN DESCRIPTION

IN - Input

P0/Q - Parallel Input P0 (parallel mode)

- Serial Data Output (serial mode)

P1/CLK - Parallel Input P1 (parallel mode)

- Serial Input Clock (serial mode)

P2/D - Parallel Input P2 (parallel mode)

- Serial Data Input (serial mode)

P3 - P7 - Remaining Parallel Inputs

GND - Ground

OUT/ OUT - Output

REF/PWM - Reference or PWM Output

P /S - Parallel / Serial Programming

Select

MS - Output Mode Select

LE - Input Latch Enable

- Supply Voltage

DESCRIPTION

The DS1023 is an 8-bit programmable delay line similar in function to the DS1020/DS1021.

Additional features have been added to extend the range of applications:

The internal delay line architecture has been revised to allow clock signals to be delayed by up to a full

period or more. Combined with an on-chip reference delay (to offset the inherent or “step zero” delay of

the device) clock phase can now be varied over the full 0-360 degree range.

DS1023

8-Bit Programmable Timing Element

www.maxim-ic.com

Q/P0

CLK/P1

D/P2

GND

OUT/OUT

REF/PWM

P/S

DS1023 300-mil DIP

DS1023S 300-mil SOIC

Summary of content (16 pages)

PAGE 1
DS1023 8-Bit Programmable Timing Element www.maxim-ic.com FEATURES § § § § § § § § PIN ASSIGNMENT Step sizes of 0.25 ns, 0.
PAGE 2
DS1023 On-chip gating is provided to allow the device to provide a pulse width modulated output, triggered by the input with duration set by the programmed value. Alternatively the output signal may be inverted on chip, allowing the device to perform as a free-running oscillator if the output is (externally) connected to the input. PROGRAMMING The device programming is identical to the DS1020/DS1021. Note, however, that the serial clock and data pins are shared with three of the parallel input pins.
PAGE 3
DS1023 Applications can read the setting of the DS1023 Delay Line by connecting the serial output pin (Q) to the serial input (D) through a resistor with a value of 1 to 10 kohms (Figure 2). Since the read process is destructive, the resistor restores the value read and provides isolation when writing to the device. The resistor must connect the serial output (Q) of the last device to the serial input (D) of the first device of a daisy chain (Figure 1).
PAGE 4
DS1023 For highest accuracy it is strongly recommended that the reference delay is used. Variations in input voltage levels and transition times can significantly alter the measured delay from input to output. This effect is totally removed if the reference delay output is used. Furthermore, adverse effects on step zero delay caused by process temperature coefficients are also cancelled out.
PAGE 5
DS1023 MS = 1 Figure 4 Output Function Pulse Width Modulated Output Delayed and Inverted Output Name PWM OUT Pin Number 9 15 PWM is an output triggered by the rising edge of the input waveform. After a time interval approximately equal to the Step Zero delay of the device the PWM output will go high. The output will return to a low level after a time interval determined by the programmed values (Table 1).
PAGE 6
DS1023 FUNCTIONAL BLOCK DIAGRAM Figure 5 DELAY LINE DETAIL (CONCEPTUAL) - DS1023-200, DS1023-500 Figure 6 6 of 16
PAGE 7
DS1023 DELAY LINE DETAIL (CONCEPTUAL) - DS1023-25, DS1023-50, DS1023-100 Figure 7 PART NUMBER TABLE Table 1 DELAYS RANGES AND TOLERANCE (all times measured in ns) PART NUMBER DS1023-25 DS1023-50 DS1023-100 DS1023-200 DS1023-500 STEP SIZE 0.25 0.50 1.0 2.0 5.0 MAX. DELAY TIME (1)/ MAX. OUTPUT PULSE WIDTH (2) 63.75 127.5 255 510 1275 MAXIMUM DEVIATION (3) ±1 ±2 ±4 ±8 ±20 MAXIMUM I/P FREQ 25 MHz 25 MHz 25 MHz 25 MHz 10 MHz MINIMUM I/P PULSE WIDTH 20 20 20 20 50 1. In “Normal” mode (MS=0).
PAGE 8
DS1023 DALLAS SEMICONDUCTOR TEST CIRCUIT Figure 8 TEST SETUP DESCRIPTION Figure 8 illustrates the hardware configuration used for measuring the timing parameters of the DS1023. The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (20 ps resolution) connected to the output. The DS1023 serial and parallel ports are controlled by interfaces to a central computer.
PAGE 9
DS1023 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Operating Temperature Range Storage Temperature Soldering Temperature Short Circuit Output Current -1.0V to +7.0V 0°C to 70°C -55°C to +125°C 260°C for 10 seconds 50 mA for 1 second * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
PAGE 10
DS1023 TIMING DIAGRAM: SILICON DELAY LINE Figure 9 AC ELECTRICAL CHARACTERISTICS DS1023-25 Delay Specifications (TA = 0°C to 70°C; VCC = 5V ± 5%) PARAMETER Step Zero Delay -absolute -wrt REF Reference Delay Delay Step Size Maximum Delay -absolute -wrt REF Integral Non-linearity (deviation from straight line) OUT Delta Delay IN High to PWM High Minimum PWM Output Pulse Width Minimum Input Pulse Width Minimum Input Period Input Rise and Fall Times SYMBOL TYP MAX UNITS NOTES 0 16.5 -1.5 18 0.
PAGE 11
DS1023 AC ELECTRICAL CHARACTERISTICS – DS1023-50 Delay Specifications (TA= 0°C to 70°C; VCC = 5V ± 5%) PARAMETER Step Zero Delay -absolute -wrt REF Reference Delay Delay Step Size Maximum Delay -absolute -wrt REF Integral Non-linearity (deviation from straight line) OUT Delta Delay IN High to PWM High Minimum PWM Output Pulse Width Minimum Input Pulse Width Minimum Input Period Input Rise and Fall Times SYMBOL TYP MAX UNITS NOTES 0 16.5 -1.5 18 0.5 22 0 22 1.
PAGE 12
DS1023 AC ELECTRICAL CHARACTERISTICS DS1023-200 Delay Specifications PARAMETER Step Zero Delay -absolute -wrt REF Reference Delay Delay Step Size Maximum Delay -absolute -wrt REF Integral Non- linearity (deviation from straight line) OUT Delta Delay IN High to PWM High Minimum PWM Output Pulse Width Minimum Input Pulse Width Minimum Input Period Input Rise and Fall Times SYMBOL MIN TYP MAX UNITS NOTES 22 0 22 2.5 ns ns ns ns 1, 13 2, 14 3, 13 16 tD0 tDREF0 tREF tSTEP 1.5 16.5 -1.
PAGE 13
DS1023 NOTES: 1. Delay from input to output with a programmed delay value of zero. 2. This is the relative delay between REF and OUT. The device is trimmed such that when programmed to zero delay the OUT output will always appear before the REF output. This parameter is numerically equal to tD0-tREF. (See Figure 15). 3. The reference delay is closely matched to the step zero delay to allow relative timings down to zero or less. 4.
PAGE 14
DS1023 TERMINOLOGY Period: The time elapsed between the leading edge of the first pulse and the leading edge of the following pulse. tWI (Pulse Width): The elapsed time on the pulse between the 1.5V point on the leading edge and the 1.5V point on the trailing edge, or the 1.5V point on the trailing edge and the 1.5V point on the leading edge. tRISE (Input Rise Time): The elapsed time between the 20% and the 80% point on the leading edge of the input pulse.
PAGE 15
DS1023 TIMING DIAGRAM: SERIAL MODE ( P /S = 1) Figure 12 DELAY vs PROGRAMMED VALUE Figure 13 tDMAX (measured) tDO 15 of 16
PAGE 16
DS1023 DETAILED RESPONSE CHARACTERISTICS Figure 14 DELAY PARAMETERS Figure 15 NOTES: 1. The device is trimmed such that tDREF = 255 * (nominal step size). 2. Since tDO is trimmed to be less than tREF, the actual step size will be slightly above the nominal value. 3. Consequently the range of absolute delay values (tDMAX-tDO) will also exceed the nominal range by an amount equal to tDREF0.