Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsLinear ICsDS1085LZ-25+

1 of 21 051606

FEATURES

§ User-Programmable Frequency Synthesizer

§ Programmable From 4.1kHz to 66MHz

§ Dual Synchronous Outputs

§ 4.13MHz to 66MHz Reference Oscillator

Output

§ 4.1kHz to 66MHz Main Oscillator Output

§ Single 3.0 to 3.6V Supply

§ Three Resolution Options

§ 2-Wire Serial Interface

§ 0.75% Absolute Accuracy

§ Nonvolatile (NV) Frequency Settings

§ No External Timing Components

§ Power-Down Mode

ORDERING INFORMATION

PIN ASSIGNMENT

SO (150mil)

PIN DESCRIPTION

OUT1 - Main Oscillator Output

OUT0 - Reference Oscillator Output

- Power-Supply Voltage

GND - Ground

CTRL1 - Control Pin for OUT1

CTRL0 - Control Pin for OUT0

SDA - 2-Wire Serial Data Input/Output

SCL - 2-Wire Serial Clock

DEVICE PACKAGE

STEP

SIZE

OSCILLATOR

OUTPUT RANGE

DS1085LZ-5 150mil SO 5kHz 4.1kHz to 66MHz

DS1085LZ-12 150mil SO 12.5kHz 4.1kHz to 66MHz

DS1085LZ-25 150mil SO 25kHz 4.1kHz to 66MHz

DESCRIPTION

The DS1085L is a dual-output frequency synthesizer requiring no external timing components for

operation. It can be used as a standalone oscillator or as a dynamically programmed, processor-controlled

peripheral device. An internal master oscillator can be programmed from 33MHz to 66MHz with three

resolution options of 5kHz, 12.5kHz, and 25kHz. A programmable 3-bit prescaler (divide-by-1, 2, 4, or 8)

permits the generation of a reference oscillator output (OUT0) from the master, ranging from 4.13MHz to

66MHz. A second independent prescaler and a 1-to-1025 divider allow the generation of a main oscillator

output (OUT1) from 4.1kHz to 66MHz. The two outputs, although synchronous with the master, can be

independently programmed. The combination of programmable master oscillator, prescalers, and dividers

allows the generation of thousands of user-specified frequencies. All master oscillator, prescaler, and

divider settings are stored in NV (EEPROM) memory, providing a default value on power-up that allows

it to be used as a standalone oscillator. A 2-wire serial interface allows in-circuit, on-the-fly programming

of the master oscillator, prescalers (P0 and P1), and divider (N). This allows dynamic frequency

modification, if required, or, for fixed-frequency applications, the DS1085L can be used with factory- or

user-programmed values.

DS1085L

3.3V EconOscillator Frequenc

Synthesize

www.maxim-ic.com

SCL

CTRL0

CTRL1

OUT1

OUT0

GND

EconOscillator is a trademark of Dallas Semiconductor.

Summary of content (21 pages)

PAGE 1
DS1085L 3.3V EconOscillator Frequency Synthesizer www.maxim-ic.com FEATURES § § § § § § § § § § § § User-Programmable Frequency Synthesizer Programmable From 4.1kHz to 66MHz Dual Synchronous Outputs 4.13MHz to 66MHz Reference Oscillator Output 4.1kHz to 66MHz Main Oscillator Output Single 3.0 to 3.6V Supply Three Resolution Options 2-Wire Serial Interface 0.
PAGE 2
DS1085L External control inputs, CTRL1 and CTRL0, enable or disable the two oscillator outputs. Both outputs feature a synchronous enable that ensures no output glitches when the output is enabled and a constant time interval (for a given frequency setting) from an enable signal to the first output transition. These inputs can also be configured to disable the master oscillator, putting the device into a low-power mode for power-sensitive applications. Figure 1.
PAGE 3
DS1085L Table 1. DEVICE COMPARISONS BY PART NUMBER PART NUMBER STEP SIZE (kHz) DAC SPAN (MHz) OFFSET SIZE (MHz) DS1085LZ-5 5 5.12 2.56 DS1085LZ-12 12.5 12.80 3.20 DS1085LZ-25 25 25.60 3.20 For further description of use of the OFFSET register see the REGISTER FUNCTIONS section. The master clock can be routed directly to the outputs (OUT0 and OUT1) or through separate prescalers (P0 and P1). In the case of OUT1, an additional programmable divider (N) can be used to generate frequencies down to 4.1kHz.
PAGE 4
DS1085L Table 2. DEVICE MODE USING OUT0 EN0 (BIT) SEL0 (BIT) PDN0 (BIT) CTRL0 OUT0 CTRL0 DEVICE (PIN) (PIN) FUNCTION MODE 1 High-Z Power-Down* Power-Down*** 0 0 0 0 High-Z Active Mux Select 1 MCLK/M 0 1 0 Active 0 MCLK Output Enable 1 High-Z 1 0 0 Active 0 MCLK 1 High-Z Output Enable 1 1 0 Active** 0 MCLK/M Power-Down 1 High-Z Power-Down X 0 1 0 MCLK Active 1 High-Z Power-Down Power-Down X 1 1 0 MCLK/M Active * This mode is for applications where OUT0 is not used, but CTRL0 is used as a device shutdown.
PAGE 5
DS1085L REGISTER FUNCTIONS The user-programmable registers can be used to determine the mode of operation (MUX), operating frequency (DAC, OFFSET, DIV), and bus settings (ADDR). The functions of the registers are described in this section, but the details of how these registers are programmed can be found in a later section. The register settings are nonvolatile, with the values being stored automatically or as required in EEPROM when the registers are programmed through the SDA and SCL pins.
PAGE 6
DS1085L Table 6. FREQUENCY vs. OFFSET OFFSET OS - 10 OS - 9 OS - 8 OS - 7 OS - 6 OS - 5 OS - 4 OS - 3 OS - 2 OS - 1 OS* OS + 1 OS + 2 OS + 3 OS + 4 OS + 5 OS + 6 DS1085LZ-5 FREQUENCY RANGE — — — — 30.7 to 35.8 33.3 to 38.4 35.8 to 41.0 38.4 to 43.5 41.0 to 46.1 43.5 to 48.6 46.1 to 51.2 48.6 to 53.8 51.2 to 56.3 53.8 to 58.9 56.3 to 61.4 58.9 to 64.0 61.4 to 66.6 DS1085LZ-12 FREQUENCY RANGE — — — — 25.6 to 38.4 28.8 to 41.6 32.0 to 44.8 35.2 to 48.0 38.4 to 51.2 41.6 to 54.4 44.8 to 57.6 48.0 to 60.8 51.
PAGE 7
DS1085L The functions of the individual bits are described in the following paragraphs. DIV1 (Default Setting = 0) This bit allows the output of the prescaler P1 to be routed directly to the OUT1 pin (DIV1 = 1). In this condition, the N divider is bypassed so the programmed value of N is ignored. If DIV1 = 0, the N divider functions normally. EN0 (Default Setting = 1) If EN0 = 1 and PDN0 = 0, the CTRL0 functions as an output enable for OUT0, the frequency of the output being determined by the SEL0 bit.
PAGE 8
DS1085L Table 7a. PRESCALER P0 DIVISOR M SETTINGS 0M1 0M0 PRESCALER P0 DIVISOR “M” 0 0 1* 0 1 2 1 0 4 1 1 8 *Factory Default Setting Table 7b. PRESCALER P1 DIVISOR M SETTINGS 1M1 1M0 PRESCALER P1 DIVISOR “M” 0 0 1* 0 1 2 1 0 4 1 1 8 *Factory Default Setting NOTE: When EN0 = SEL0 = PDN0 = 0, CTRL0 also functions as a power-down. This is a special case for situations when OUT0 is not used. Under these conditions all the circuitry associated with OUT0 is powered down. OUT0 is powered down (see Table 2).
PAGE 9
DS1085L N The DIV word sets the programmable divider. These 10 bits (N0–N9) determine the value of the programmable divider (N). The range of divisor values is from two to 1025, and is equal to the programmed value of N plus 2 (see Table 8). Table 8. PROGRAMMABLE DIVISOR N VALUES BIT VALUE 00000000 00XXXXXX 00000000 01XXXXXX — — — — 11111111 11XXXXXX * Factory Default Setting DIVISOR (N) 2* 3 — — — — 1025 ADDR BYTE (Address 0Dh) MSB — X NAME Factory Default X = Don’t care.
PAGE 10
DS1085L COMMAND SET Data and control information is read from and written to the DS1085L in the format shown in Figure 3. To write to the DS1085L, the master issues the slave address of the DS1085L and the R/ W bit is set to 0. After receiving an acknowledge, the bus master provides a command protocol. After receiving this protocol, the DS1085L issues an acknowledge, and then the master can send data to the DS1085L.
PAGE 11
DS1085L Access RANGE [37h] If R/ W is 1, the next data bytes read are the values stored in the RANGE register. This register has a 14bit value. The upper eight bits are sent first, followed by a second byte that contains the five LSBs of the register value in the most significant positions of the data byte. The upper five MSB’s of the first byte contain the OS value for the frequency adjust Table 6. The register is read-only.
PAGE 12
DS1085L 2-WIRE SERIAL DATA BUS The DS1085L communicates through a 2-wire serial interface. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a “master.” The devices that are controlled by the master are “slaves.” A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the bus.
PAGE 13
DS1085L A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. Figure 2. DATA TRANSFER ON 2-WIRE SERIAL BUS Figures 2, 3, and 4 detail how data transfer is accomplished on the 2-wire bus.
PAGE 14
DS1085L SLAVE ADDRESS A control byte is the first byte received following the START condition from the master device. The control byte consists of a 4-bit control code; for the DS1085L, this is set as 1011 binary for read and write operations. The next three bits of the control byte are the device select bits (A2, A1, A0). The address bits to which the DS1085L responds are factory set to 000, but can be altered by writing new values to the ADDR register.
PAGE 15
DS1085L Figure 4.
PAGE 16
DS1085L ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature -0.5V to +6.0V 0°C to +70°C -55°C to +125°C See IPC/JEDEC J-STD-020A * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
PAGE 17
DS1085L MASTER OSCILLATOR CHARACTERISTICS (VCC = 3.3V ±10%, TA = 0°C to +70°C.) PARAMETER Master Oscillator Range SYMBOL fOSC Default Master Oscillator Frequency f0 Master Oscillator Frequency Tolerance Df0 f0 Voltage Frequency Variation Temperature Frequency Variation Integral Nonlinearity of Frequency DAC DfV f0 DfT f0 INL CONDITION -5 version -12 version -25 version VCC = 3.3V, TA = +25°C SYMBOL TYP MAX 66 48.58 52.3 50.9 +0.75 DAC step size Overvoltage range, TA = +25°C Default freq.
PAGE 18
DS1085L AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE (VCC = 3.3V ±10%, TA = 0°C to +70°C.
PAGE 19
DS1085L 7) DAC and OFFSET register settings must be configured to maintain the clock frequency within this range. Correct operation of the device is not guaranteed if these limits are exceeded. 8) Frequency settles faster for small charges in value. During a change, the frequency changes smoothly from the original value to the new value. 9) This indicates the time taken between power-up and the outputs becoming active. An on-chip delay is intentionally introduced to allow the oscillator to stabilize.
PAGE 20
DS1085L TYPICAL OPERATING CHARACTERISTICS (VCC = 3.3V ±10%, TA = 0°C to +70°C.) SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. VOLTAGE 20 14.0 18 12.0 16 CURRENT (mA) CURRENT (mA) 14 12 10 8 10.0 8.0 6.0 DS1085L-05 6 4.0 DS1085L-12 4 2.0 DS1085L-25 DS1085L-12 2 0.0 2.75 0 0 10 20 30 40 50 60 70 3.00 3.25 3.50 VOLTAGE (V) T EMPERAT URE (°C) SUPPLY CURRENT vs. DIVISOR SUPPLY CURRENT vs. DIVISOR 12 14 12 11 10 DS1085L-05 6 4 2.75V 3.
PAGE 21
DS1085L TYPICAL OPERATING CHARACTERISTICS (continued) (VCC = 3.3V ±10%, TA = 0°C to +70°C.) SUPPLY CURRENT vs. DIVISOR SUPPLY CURRENT vs. DAC SETTING AND OFFSET 10 9 14 8 12 7 CURRENT (mA) CURRENT (mA) 10 8 6 OS 4 5 4 DS1085L-25 3 OS+1 DS1085L-12 DS1085L-05 2 OS-1 2 6 1 0 0 200 400 600 800 0 1000 0 DAC SETTING 200 400 600 800 1000 DIVISOR (N) FREQUENCY % CHANGE vs. SUPPLY VOLTAGE FREQUENCY % CHANGE vs. TEMPERATURE DS1085L-12 1.