Datasheet
DS1231/S
DS1231/S
Power Monitor Chip
022698 1/9
FEATURES
• Warns processor of an impending power failure
• Provides time for an orderly shutdown
• Prevents processor from destroying nonvolatile
memory during power transients
• Automatically restarts processor after power is
restored
• Suitable for linear or switching power supplies
• Adjusts to hold time of the power supply
• Supplies necessary signals for processor interface
• Accurate 5% or 10% V
CC
monitoring
• Replaces power-up reset circuitry
• No external capacitors required
• Optional 16-pin SOIC surface mount package
PIN ASSIGNMENT
MODE
NC
GND
RST
NC
VCC
NC
NMI
NC
RST
NC
NC
TOL
NC
IN
NC
DS1231S 16–Pin SOIC
(300 MIL)
See Mech. Drawings
Section
VCC
NMI
RST
RST
IN
MODE
TOL
GND
DS1231 8–Pin DIP
(300 MIL)
See Mech. Drawings
Section
1
2
3
4
5
6
7
8
1
11
12
13
14
2
3
4
5
6
7
8
9
10
15
16
PIN DESCRIPTION
IN – Input
MODE – Selects input pin characteristics
TOL – Selects 5% or 10% V
CC
detect
GND – Ground
RST – Reset (Active High)
RST
– Reset (Active Low, open drain)
NMI
– Non–Maskable Interrupt
V
CC
– +5V Supply
NC – No Connections
DESCRIPTION
The DS1231 Power Monitor Chip uses a precise tem-
perature-compensated reference circuit which provides
an orderly shutdown and an automatic restart of a pro-
cessor-based system. A signal warning of an impending
power failure is generated well before regulated DC
voltages go out of specification by monitoring high volt-
age inputs to the power supply regulators. If line isola-
tion is required a UL-approved opto-isolator can be di-
rectly interfaced to the DS1231. The time for processor
shutdown is directly proportional to the available
hold-up time of the power supply. Just before the
hold-up time is exhausted, the Power Monitor uncondi-
tionally halts the processor to prevent spurious cycles
by enabling Reset as V
CC
falls below a selectable 5 or
10 percent threshold. When power returns, the proces-
sor is held inactive until well after power conditions have
stabilized, safeguarding any nonvolatile memory in the
system from inadvertent data changes.