9-5055; Rev 12/09 DS1305 Serial Alarm Real-Time Clock www.maxim-ic.
DS1305 ORDERING INFORMATION PART DS1305 DS1305N DS1305E DS1305E+ DS1305E/T&R DS1305E+T&R DS1305EN DS1305EN+ DS1305EN/T&R DS1305EN+T&R TEMP RANGE PIN-PACKAGE TOP MARK* 0°C to +70°C -40°C to +85°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C 16 DIP (300 mils) 16 DIP (300 mils) 20 TSSOP (173 mils) 20 TSSOP (173 mils) 20 TSSOP (173 mils) 20 TSSOP (173 mils) 20 TSSOP (173 mils) 20 TSSOP (173 mils) 20 TSSOP (173 mils) 20 TSSOP (173 mils) DS
DS1305 PIN DESCRIPTION PIN DIP TSSOP NAME 1 1 VCC2 2 2 VBAT 3 3 X1 4 5 X2 5 4, 6, 8, 13, 19 N.C. 6 7 INT0 7 9 INT1 8 10 GND 9 11 SERMODE 10 12 CE 11 14 SCLK FUNCTION Backup Power Supply. This is the secondary power supply pin. In systems using the trickle charger, the rechargeable energy source is connected to this pin. Battery Input for Standard +3V Lithium Cell or Other Energy Source. If not used, VBAT must be connect to ground.
DS1305 PIN DESCRIPTION (continued) PIN DIP TSSOP NAME 12 15 SDI 13 16 SDO 14 17 VCCIF 15 18 PF 16 20 VCC1 FUNCTION Serial Data Input. When SPI communication is selected, the SDI pin is the serial data input for the SPI bus. When 3-wire communication is selected, this pin must be tied to the SDO pin (the SDI and SDO pins function as a single I/O pin when tied together). Serial Data Output. When SPI communication is selected, the SDO pin is the serial data output for the SPI bus.
DS1305 RECOMMENDED LAYOUT FOR CRYSTAL Local ground plane (Layer 2) X1 crystal X2 GND CLOCK ACCURACY The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast.
DS1305 READING FROM THE CLOCK REGISTERS Buffers are used to copy the time and date register at the beginning of a read. When reading in burst mode, the user copy is static while the internal registers continue to increment. Figure 2.
DS1305 hour, and minute alarm registers is set to a logic 1. When bit 7 of the day, hour, minute, and seconds alarm registers is set to a logic 1, alarm occurs every second. During each clock update, the RTC compares the Alarm 0 and Alarm 1 registers with the corresponding clock registers. When a match occurs, the corresponding alarm flag bit in the status register is set to a 1. If the corresponding alarm interrupt enable bit is enabled, an interrupt output is activated. Table 2.
DS1305 AIE1 (Alarm Interrupt Enable 1) – When set to a logic 1, this bit permits the interrupt 1 request flag (IRQF1) bit in the status register to assert INT1 (when INTCN = 1) or to assert INT0 (when INTCN = 0). When the AIE1 bit is set to logic 0, the IRQF1 bit does not initiate an interrupt signal.
DS1305 Table 3.
DS1305 Figure 4. POWER-SUPPLY CONFIGURATIONS CONFIGURATION 1: BACKUP SUPPLY IS NONRECHARGEABLE LITHIUM BATTERY NOTE: DEVICE IS WRITE-PROTECTED IF VCC < VCCTP. CONFIGURATION 2: BACKUP SUPPLY IS A RECHARGEABLE BATTERY OR SUPER CAPACITOR NOTE: DEVICE DOES NOT PROVIDE AUTOMATIC WRITE PROTECTION.
DS1305 SERIAL INTERFACE The DS1305 offers the flexibility to choose between two serial interface modes. The DS1305 can communicate with the SPI interface or with a standard 3-wire interface. The interface method used is determined by the SERMODE pin. When this pin is connected to VCC, SPI communication is selected. When this pin is connected to ground, standard 3-wire communication is selected.
DS1305 ADDRESS AND DATA BYTES Address and data bytes are shifted MSB first into the serial data input (SDI) and out of the serial data output (SDO). Any transfer requires the address of the byte to specify a write or read to either a RTC or RAM location, followed by one or more bytes of data. Data is transferred out of the SDO for a read operation and into the SDI for a write operation (Figures 6 and 7). Figure 6. SPI SINGLE-BYTE WRITE * SCLK CAN BE EITHER POLARITY. SERMODE = VCC Figure 7.
DS1305 Figure 8. SPI MULTIPLE-BYTE BURST TRANSFER READING AND WRITING IN BURST MODE Burst mode is similar to a single-byte read or write, except that CE is kept high and additional SCLK cycles are sent until the end of the burst. The clock registers and the user RAM can be read or written in burst mode. When accessing the clock registers in burst mode, the address pointer wraps around after reaching 1Fh (9Fh for writes).
DS1305 3-WIRE INTERFACE The 3-wire interface mode operates similarly to the SPI mode. However, in 3-wire mode there is one I/O instead of separate data in and data out signals. The 3-wire interface consists of the I/O (SDI and SDO pins tied together), CE, and SCLK pins. In 3-wire mode, each byte is shifted in LSB first unlike SPI mode where each byte is shifted in MSB first. As is the case with the SPI mode, an address byte is written to the device followed by a single data byte or multiple data bytes.
DS1305 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………..-0.5V to +7.0V Storage Temperature Range……………………………………………………………….-55°C to +125°C Soldering Temperature………………………………………….See IPC/JEDEC J-STD-020 Specification This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied.
DS1305 DC ELECTRICAL CHARACTERISTICS (Over the operating range, unless otherwise specified.) PARAMETER Input Leakage Output Leakage IOL= 1.5mA Logic 0 Output IOL = 4.0mA I Logic 1 OH = -0.4mA Output IOH = -1.
DS1305 3-WIRE AC ELECTRICAL CHARACTERISTICS (Over the operating range, unless otherwise specified.) (Figure 10 and Figure 11) PARAMETER SYMBOL Data to CLK Setup tDC CLK to Data Hold tCDH CLK to Data Delay tCDD CLK Low Time tCL CLK High Time tCH CLK Frequency tCLK CLK Rise and Fall tR, tF CE to CLK Setup tCC CLK to CE Hold tCCH CE Inactive Time tCWH CE to Output High-Z tCDZ SCLK to Output High-Z tCCZ MIN VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.
DS1305 Figure 10. TIMING DIAGRAM: 3-WIRE READ DATA TRANSFER SERMODE = GND * I/O IS SDI AND SDO TIED TOGETHER. Figure 11. TIMING DIAGRAM: 3-WIRE WRITE DATA TRANSFER SERMODE = GND * I/O IS SDI AND SDO TIED TOGETHER.
DS1305 SPI AC ELECTRICAL CHARACTERISTICS (Over the operating range, unless otherwise specified.) (Figure 12 and Figure 13) PARAMETER SYMBOL MIN TYP MAX UNITS Data to CLK Setup tDC CLK to Data Hold tCDH CLK to Data Delay tCDD CLK Low Time tCL CLK High Time tCH CLK Frequency tCLK CLK Rise and Fall tR, tF CE to CLK Setup tCC CLK to CE Hold tCCH CE Inactive Time tCWH CE to Output High-Z tCDZ VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.0V VCC = 5V VCC = 2.
DS1305 Figure 12. TIMING DIAGRAM: SPI READ DATA TRANSFER SERMODE = VCC * SCLK CAN BE EITHER POLARITY, TIMING SHOWN FOR CPOL = 1. Figure 13. TIMING DIAGRAM: SPI WRITE DATA TRANSFER SERMODE = VCC * SCLK CAN BE EITHER POLARITY, TIMING SHOWN FOR CPOL = 1.
DS1305 NOTES: 1) ICC1T and ICC2T are specified with CE set to a logic 0 and EOSC bit = 0 (oscillator enabled). 2) ICC1A and ICC2A are specified with CE = VCC, SCLK=2MHz at VCC = 5V; SCLK = 500kHz at VCC = 2.0V, VIL = 0V, VIH = VCC, and EOSC bit = 0 (oscillator enabled). 3) Measured at VIH = 2.0V or VIL = 0.8V and 10ms maximum rise and fall time. 4) Measured with 50pF load. 5) Measured at VOH = 2.4V or VOL = 0.4V. 6) ICC1S and ICC2S are specified with CE set to a logic 0.
DS1305 REVISION HISTORY REVISION DATE DESCRIPTION Added Table 1. Crystal Specifications to the Clock Accuracy section. 12/09 PAGES CHANGED 5 Added “SERMODE = VCC” to Figures 6, 7, 12, and 13. 12, 20 Added “SERMODE = GND” to Figures 9, 10, and 11. 14, 18 Removed the “Crystal Capacitance” parameter from the Capacitance table. 16 22 of 22 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
