9-5056; Rev 12/09 DS1306 Serial Alarm Real-Time Clock www.maxim-ic.com FEATURES PIN CONFIGURATIONS Real-Time Clock (RTC) Counts Seconds, Minutes, Hours, Date of the Month, Month, Day of the Week, and Year with Leap-Year Compensation Valid Up to 2100 96-Byte, Battery-Backed NV RAM for Data Storage Two Time-of-Day Alarms, Programmable on Combination of Seconds, Minutes, Hours, and Day of the Week 1Hz and 32.
DS1306 ORDERING INFORMATION PART DS1306 DS1306+ DS1306N DS1306N+ DS1306E DS1306E+ DS1306EN DS1306EN+ DS1306EN/T&R DS1306EN+T&R DS1306E/T&R DS1306E+T&R TEMP RANGE PIN-PACKAGE TOP MARK* 0°C to +70°C 0°C to +70°C -40°C to +85°C 0°C to +70°C 0°C to +70°C 0°C to +70°C -40°C to +85°C -40°C to +85°C -40°C to +85°C -40°C to +85°C 0°C to +70°C 0°C to +70°C 16 DIP (300 mils) 16 DIP (300 mils) 16 DIP (300 mils) 16 DIP (300 mils) 20 TSSOP (173 mils) 20 TSSOP (173 mils) 20 TSSOP (173 mils) 20 TSSOP (173 mils) 20 T
DS1306 PIN DESCRIPTION (continued) PIN TSSOP DIP 9 7 10 8 11 9 12 10 14 11 15 12 16 13 17 14 18 15 20 16 4, 6, 13, 19 — NAME FUNCTION 1Hz Output. The 1Hz pin provides a 1Hz square wave output. This output is active when the 1 Hz bit in the control register is a logic 1. Both INT0 and 1Hz 1Hz pins are open-drain outputs. The interrupt, 1Hz signal, and the internal clock continue to run regardless of the level of VCC (as long as a power source is present).
DS1306 DESCRIPTION The DS1306 serial alarm real-time clock (RTC) provides a full binary coded decimal (BCD) clock calendar that is accessed by a simple serial interface. The clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24hour or 12-hour format with AM/PM indicator.
DS1306 RECOMMENDED LAYOUT FOR CRYSTAL Local ground plane (Layer 2) X1 crystal X2 GND CLOCK ACCURACY The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit can result in the clock running fast.
DS1306 Figure 2.
DS1306 registers is set to a logic 1. Similarly, an alarm is generated every minute when bit 7 of the day, hour, and minute alarm registers is set to a logic 1. When bit 7 of the day, hour, minute, and seconds alarm registers is set to a logic 1, an alarm occurs every second. During each clock update, the RTC compares the Alarm 0 and Alarm 1 registers with the corresponding clock registers. When a match occurs, the corresponding alarm flag bit in the status register is set to a 1.
DS1306 STATUS REGISTER (READ 10H) BIT7 0 BIT6 0 BIT5 0 BIT4 0 BIT3 0 BIT2 0 BIT1 IRQF1 BIT0 IRQF0 IRQF0 (Interrupt 0 Request Flag) – A logic 1 in the interrupt request flag bit indicates that the current time has matched the Alarm 0 registers. If the AIE0 bit is also a logic 1, the INT0 pin goes low. IRQF0 is cleared when the address pointer goes to any of the Alarm 0 registers during a read or write. IRQF0 is activated when the device is powered by VCC1, VCC2, or VBAT.
DS1306 Table 3.
DS1306 Figure 4. POWER-SUPPLY CONFIGURATIONS CONFIGURATION 1: BACKUP SUPPLY IS NONRECHARGEABLE LITHIUM BATTERY NOTE: DEVICE IS WRITE-PROTECTED IF VCC < VCCTP. CONFIGURATION 2: BACKUP SUPPLY IS A RECHARGEABLE BATTERY OR SUPER CAPACITOR NOTE: DEVICE DOES NOT PROVIDE AUTOMATIC WRITE PROTECTION.
DS1306 SERIAL INTERFACE The DS1306 offers the flexibility to choose between two serial interface modes. The DS1306 can communicate with the SPI interface or with a standard 3-wire interface. The interface method used is determined by the SERMODE pin. When this pin is connected to VCC, SPI communication is selected. When this pin is connected to ground, standard 3-wire communication is selected.
DS1306 ADDRESS AND DATA BYTES Address and data bytes are shifted MSB first into the serial data input (SDI) and out of the serial data output (SDO). Any transfer requires the address of the byte to specify a write or read to either a RTC or RAM location, followed by one or more bytes of data. Data is transferred out of the SDO for a read operation and into the SDI for a write operation (Figures 6 and 7). Figure 6. SPI SINGLE-BYTE WRITE * SCLK CAN BE EITHER POLARITY. SERMODE = VCC Figure 7.
DS1306 Figure 8. SPI MULTIPLE-BYTE BURST TRANSFER READING AND WRITING IN BURST MODE Burst mode is similar to a single-byte read or write, except that CE is kept high and additional SCLK cycles are sent until the end of the burst. The clock registers and the user RAM may be read or written in burst mode. When accessing the clock registers in burst mode, the address pointer will wrap around after reaching 1Fh (9Fh for writes).
DS1306 Figure 9. 3-WIRE SINGLE BYTE TRANSFER SINGLE-BYTE READ CE SCLK I/O* A0 A1 A2 A3 A4 A5 A6 0 D0 D1 D2 D3 D4 D5 D6 D7 SINGLE-BYTE WRITE CE SCLK I/O* A0 A1 A2 A3 A4 A5 A6 1 D0 D1 D2 D3 D4 D5 D6 D7 NOTE: IN BURST MODE, CE IS KEPT HIGH AND ADDITIONAL SCLK CYCLES ARE SENT UNTIL THE END OF THE BURST. *I/O IS SDI AND SDO TIED TOGETHER.
DS1306 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………..-0.5V to +7.0V Storage Temperature Range……………………………………………………………….-55C to +125C Soldering Temperature.……………………………….Refer to the IPC/JEDEC Standard J-STD-020 Specification This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation sections of this specification is not implied.
DS1306 DC ELECTRICAL CHARACTERISTICS (TA = Over the operating range, unless otherwise specified.) PARAMETER Input Leakage Output Leakage IOL = 1.5mA Logic 0 Output IOL = 4.0mA IOH = -0.4mA Logic 1 Output IOH = -1.
DS1306 3-WIRE AC ELECTRICAL CHARACTERISTICS (TA = Over the operating range, unless otherwise specified.) (Figure 10 and Figure 11) PARAMETER Data to CLK Setup CLK to Data Hold CLK to Data Delay CLK Low Time CLK High Time CLK Frequency CLK Rise and Fall CE to CLK Setup CLK to CE Hold CE Inactive Time CE to Output High-Z SCLK to Output High-Z SYMBOL VCC = 2.0V tDC VCC = 5V VCC = 2.0V tCDH VCC = 5V VCC = 2.0V tCDD VCC = 5V VCC = 2.0V tCL VCC = 5V VCC = 2.0V tCH VCC = 5V VCC = 2.0V tCLK VCC = 5V VCC = 2.
DS1306 Figure 10. TIMING DIAGRAM: 3-WIRE READ DATA TRANSFER SERMODE = GND * I/O IS SDI AND SDO TIED TOGETHER. Figure 11. TIMING DIAGRAM: 3-WIRE WRITE DATA TRANSFER SERMODE = GND * I/O IS SDI AND SDO TIED TOGETHER.
DS1306 SPI AC ELECTRICAL CHARACTERISTICS (TA = Over the operating range, unless otherwise specified.) PARAMETER Data to CLK Setup CLK to Data Hold CLK to Data Delay CLK Low Time CLK High Time CLK Frequency CLK Rise and Fall CE to CLK Setup CLK to CE Hold CE Inactive Time CE to Output High-Z SYMBOL VCC = 2.0V tDC VCC = 5V VCC = 2.0V tCDH VCC = 5V VCC = 2.0V tCDD VCC = 5V VCC = 2.0V tCL VCC = 5V VCC = 2.0V tCH VCC = 5V VCC = 2.0V tCLK VCC = 5V VCC = 2.0V tR, tF VCC = 5V VCC = 2.0V tCC VCC = 5V VCC = 2.
DS1306 Figure 12. TIMING DIAGRAM: SPI READ DATA TRANSFER SERMODE = VCC * SCLK CAN BE EITHER POLARITY, TIMING SHOWN FOR CPOL = 1. Figure 13. TIMING DIAGRAM: SPI WRITE DATA TRANSFER SERMODE = VCC * SCLK CAN BE EITHER POLARITY, TIMING SHOWN FOR CPOL = 1.
DS1306 NOTES: 1) ICC1T and ICC2T are specified with CE set to a logic 0. 2) ICC1A and ICC2A are specified with CE = VCC, SCLK = 2MHz at VCC = 5V; SCLK = 500kHz at VCC = 2.0V, VIL = 0V, VIH = VCC. 3) Measured at VIH = 2.0V or VIL = 0.8V and 10ms maximum rise and fall time. 4) Measured with 50pF load. 5) Measured at VOH = 2.4V or VOL = 0.4V. 6) VCC = VCC1, when VCC1 > VCC2 + 0.2V (typical); VCC = VCC2, when VCC2 > VCC1. 7) VCC2 = 0V. 8) VCC1 = 0V. 9) VCC1 < VBAT.
DS1306 REVISION HISTORY REVISION DATE DESCRIPTION Added Table 1. Crystal Specifications to the Clock Accuracy section. 12/09 PAGES CHANGED 5 Added “SERMODE = VCC” to Figures 6, 7, 12, and 13. 12, 20 Added “SERMODE = GND” to Figures 9, 10, and 11. 14, 18 Removed the “Crystal Capacitance” parameter from the Capacitance table. 16 22 of 22 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
