Datasheet

1 of 13
FEATURES
 Converts CMOS SRAM into nonvolatile
memory
 Unconditionally write-protects SRAM when
V
CC
is out of tolerance
 Automatically switches to battery backup
supply when V
CC
power failure occurs
 Flexible memory organization
- Mode 0: 4 banks with 1 SRAM each
- Mode 1: 2 banks with 2 SRAMs each
- Mode 2: 1 bank with 4 SRAMs each
 Monitors voltage of a lithium cell and
provides advanced warning of impending
battery failure
 Signals low-battery condition on active low
Battery Warning output signal
 Resets processor when power failure occurs
and holds processor in reset during system
power-up
 Optional 5% or 10% power-fail detection
 16-pin PDIP, 16-pin SO and 20-pin TSSOP
packages
 Industrial temperature range of -40°C to
+85°C
PIN DESCRIPTION
V
CCI
- +5V Power Supply Input
V
CCO
- SRAM Power Supply Output
V
BAT
- Backup Battery Input
A, B - Address Inputs
CEI1
-
CEI4
- Chip Enable Inputs
CEO1
-
CEO4
- Chip Enable Outputs
TOL - V
CC
Tolerance Select
BW
- Battery Warning Output (Open
Drain)
RST
- Reset Output (Open Drain)
MODE - Mode Input
GND - Ground
NC - No Connection
PIN ASSIGNMENT
DS1321
Flexible Nonvolatile Controller with
Lithium Battery Monitor
1
2
3
4
20
19
18
17
5
6
7
8
9
10
11
12
13
14
15
16
NC
DS1321E 20-Pin TSSOP
V
CCI
RST
BW
CEO1
CEO2
NC
CEO3
CEO4
NC
MODE
V
CCO
V
BAT
TOL
CEI1
CEI2
NC
A/CEI3
B/CEI4
GND
1
2
3
4
16
15
14
13
5
6
7
8
9
10
11
12
V
CCI
RST
BW
CEO1
CEO2
CEO3
CEO4
MODE
V
CCO
V
BAT
TOL
CEI1
CEI2
A/CEI3
B/CEI4
GND
DS1321 16-Pin PDIP
(300 mils)
1
2
3
4
16
15
14
13
5
6
7
8
9
10
11
12
V
CCI
RST
BW
CEO1
CEO2
CEO3
CEO4
MODE
V
CCO
V
BAT
TOL
CEI1
CEI2
A/CEI3
B/CEI4
GND
DS1321S 16-Pin SO
(150 mils)
19-6312; Rev 6/12