Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsIntegrated Circuits (ICs)Timer IC t- real time clock Binary counter uMAX 8

1 of 15

REV: 070607

General Description

The DS1371 is a 32-bit binary counter that is

designed to continuously count time in seconds.

An additional counter that can generate a

periodic alarm or serve as a watchdog timer is

also provided. If enabled as a watchdog timer,

the watchdog strobe input pin provides a

hardware reset of the counter. If disabled, this

counter can be used as 3 Bytes of general-

purpose RAM. A configurable output can be

used as an interrupt or provide a square wave at

one of four selectable frequencies. The device is

programmed serially through a I

C bidirectional

bus.

Applications

Servers

Point-of-Sale Equipment

Portable Instruments

Elapsed Time Measurements

Typical Operating Circuit

Features

 32-Bit Binary Counter

 24-Bit Binary Counter Provides Periodic

Alarm, Watchdog Timer, or RAM

 Strobe Input to Reset Watchdog Timer

 Single Output Configurable as Interrupt or

Square Wave

 I

C Serial Interface

 Low-Voltage Operation

 Operating Temperature Range:

-40°C to +85°C

 Available in 8-Pin μSOP

Ordering Information

PART TEMP RANGE

PIN-

PACKAGE

TOP

MARK

DS1371U -40°C to +85°C 8 μSOP 1371

DS1371U+ -40°C to +85°C 8 μSOP 1371

+Denotes a lead-free/RoHS-compliant package. A + appears on the top

mark for lead-free packages.

Pin Configuration

DS1371

C, 32-Bit Binary Counte

Watchdo

Clock

www.maxim-ic.com

TOP VIEW

μSOP

WDS

GND

SQW/

SCL

SDA

DS1371

Summary of content (15 pages)

PAGE 1
DS1371 I C, 32-Bit Binary Counter Watchdog Clock 2 www.maxim-ic.com General Description Features The DS1371 is a 32-bit binary counter that is designed to continuously count time in seconds. An additional counter that can generate a periodic alarm or serve as a watchdog timer is also provided. If enabled as a watchdog timer, the watchdog strobe input pin provides a hardware reset of the counter. If disabled, this counter can be used as 3 Bytes of generalpurpose RAM.
PAGE 2
DS1371 ABSOLUTE MAXIMUM RATINGS Voltage Range on VCC Pin Relative to Ground………………………………………………………..-0.3V to +6.0V Voltage Range on SDA, SCL, and WDS Relative to Ground…………………………………..-0.3V to (VCC +0.5V) Operating Temperature Range (noncondensing)……………………………………………………...-40°C to +85°C Storage Temperature Range………………………………………………………………………….-55°C to +125°C Soldering Temperature…………………………………………………………………...
PAGE 3
DS1371 AC ELECTRICAL CHARACTERISTICS (VCC = 1.7V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.
PAGE 4
DS1371 Typical Operating Characteristics (VCC = 3.3V, TA = +25°C, unless otherwise noted.) IOSCO vs. VCC SQUARE-WAVE OFF IOSC1 vs. VCC SQUARE-WAVE ON DS1371 toc02 900 850 SUPPLY CURRENT (nA) 550 SUPPLY CURRENT (nA) 950 DS1371 toc01 600 500 450 400 800 750 700 650 600 550 500 350 450 300 400 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 2.5 3.5 4.0 4.5 ICCA vs. VCC SQUARE-WAVE ON DS1371 toc03 SUPPLY CURRENT (µA) 650 600 550 500 -20 0 20 40 60 5.0 5.
PAGE 5
DS1371 Figure 1. Timing Diagram X1 ÷4 X2 ÷2 ÷4096 32,768Hz 8192Hz 4096Hz 1Hz GND Alarm/ Watchdog Stat/Ctrl SDA SCL 1Hz WACE Power WDS SQW/INT SQW M U X CLR Oscillator DS1371 VCC M U X 4096Hz ÷4096 1Hz WD/ALM M U X 32-Bit Counter 24-Bit Counter AIE INT CLR INTCN I2C Interface Figure 2.
PAGE 6
DS1371 PIN DESCRIPTION PIN NAME FUNCTION 1, 2 X1, X2 3 WDS 4 GND These signals are connections for a standard 32.768kHz quartz crystal. The internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (CL) of 6pF. No external resistors or capacitors are required. For more information about crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations with Dallas Real-Time Clocks.
PAGE 7
DS1371 Table 1. Crystal Specifications* PARAMETER SYMBOL Nominal Frequency Series Resistance Load Capacitance fO ESR CL MIN TYP MAX UNITS 50 kHz kΩ pF 32.768 6 *The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications. LOCAL GROUND PLANE (LAYER 2) X1 CRYSTAL X2 GND Figure 3.
PAGE 8
DS1371 Address Map Table 2 shows the address map for the registers of the DS1371. During a multibyte access, when the address pointer reaches the end of the register space (08h), it wraps around to location 00h. On an I2C START, STOP, or address pointer incrementing to location 00h, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run.
PAGE 9
DS1371 Time-of-Day Counter The time-of-day counter is a 32-bit up counter. The contents can be read or written by accessing the address range 00h–03h. When the counter is read, the current time of day is latched into a register, which is output on the serial data line while the counter continues to increment. Writing to the counter resets the countdown chain for the time-of-day counter (Figure 2). The watchdog countdown chain is unaffected.
PAGE 10
DS1371 Special Purpose Registers The DS1371 has two additional registers (07h–08h) that control the WD/ALM counter, square-wave output, and interrupts. Control Register (07h) Bit # Name Default 7 EOSC 0 6 WACE 0 5 WD/ALM 0 4 0 0 3 INTCN 0 2 RS2 1 1 RS1 1 0 AIE 0 Bit 7: Enable Oscillator (EOSC). When set to logic 0, the oscillator is started. When set to logic 1, the oscillator is stopped.
PAGE 11
DS1371 Status Register (08h) Bit # Name Default 7 OSF 1 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 0 0 AF — Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period and can be used to judge the validity of the timekeeping data. This bit is set to logic 1 any time that the oscillator stops. The following are examples of conditions that can cause the OSF bit to be set: • The first time power is applied.
PAGE 12
DS1371 Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition.
PAGE 13
DS1371 Figures 5 and 6 detail how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two types of data transfer are possible: Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte. Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master.
PAGE 14
S 1101000 DS1371 0 A XXXXXXXX B - Block Select S - Start A - Acknowledge (ACK) P - Stop A XXXXXXXX A XXXXXXXX A ... XXXXXXXX A P Master to slave DATA TRANSFERRED (X+1 BYTES + ACKNOWLEDGE) Slave to master S 1101000 Figure 5.
PAGE 15
DS1371 Revision History REV DATE DESCRIPTION 110502 Initial data sheet release. (Page 14) In Figures 6 and 7, corrected the slave address and removed the second “START.” Changed all 2-wire references to I2C. (Page 1) Added lead-free packages to the Ordering Information table. (Page 2) Removed “A” from J-STD-020 (Soldering Temperature) reference. Removed Figure 3 (oscillator circuit) and incorporated into new Figure 2 (page 5).