Rev 0; 7/07 I2C, 32-Bit, Binary Counter Clock with 64-Bit ID Features The DS1372 is a 32-bit binary up counter and 24-bit down counter with a unique 64-bit ID. The counters, ID, configuration, and status registers are accessed using an I 2 C serial interface. The DS1372 includes a SQW/INT open-drain output that can output either a square wave at one of four predefined frequencies, or it can output an active-low signal when the 24-bit down counter reaches 0.
DS1372 I2C, 32-Bit, Binary Counter Clock with 64-Bit ID ABSOLUTE MAXIMUM RATINGS Operating Temperature Range (noncondensing)……. .......................................-40°C to +85°C Storage Temperature Range…………………….-55°C to +125°C Soldering Temperature………….......See IPC/JEDEC J-STD-020 specification. Voltage Range on Any Pin Relative to Ground…. .-0.3V to +6.0V Continuous Power Dissipation (TA = +70°C) (derate 4.5mW/°C above +70°C) ……………………. ....
I2C, 32-Bit, Binary Counter Clock with 64-Bit ID (VCC = 2.4V to 5.5V, TA = -40°C to +85°C, unless otherwise noted.) (Note 1) PARAMETER Data Setup Time (Note 10) Rise Time of SDA and SCL Signals (Note 11) Fall Time of SDA and SCL Signals (Note 11) SYMBOL tSU:DAT CONDITIONS MIN Fast mode Standard mode TYP MAX 100 250 ns Fast mode 20 + 0.1CB 300 Standard mode 20 + 0.1CB 1000 Fast mode 20 + 0.1CB 300 Standard mode 20 + 0.1CB 300 Fast mode Standard mode 0.6 4.
I2C, 32-Bit, Binary Counter Clock with 64-Bit ID DS1372 Pin Description PIN 1, 2 NAME FUNCTION X1, X2 Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for operation with a crystal having a 12.5pF specified load capacitance (CL). Pin X1 is the input to the oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the internal oscillator, pin X2, is floated if an external oscillator is connected to pin X1.
I2C, 32-Bit, Binary Counter Clock with 64-Bit ID The DS1372 is a 32-bit binary counter designed to continuously count time in seconds. An additional counter is provided that can generate a periodic alarm. An interrupt output can be driven when the alarm condition is met. The device includes a unique, factory-lasered 64-bit ROM ID. The device is programmed serially by an I2C bidirectional bus.
DS1372 I2C, 32-Bit, Binary Counter Clock with 64-Bit ID Alarm Operation reloaded with the seed value and the countdown restarts. When the counter is read, the current counter value is latched into a register, which is output on the serial data line while the counter continues to decrement. The counter is disabled if the seed value is zero or if ACE = 0. Whenever the ACE is set from 0 to 1, the counter is reloaded with the current seed value and the counter begins to count down.
I2C, 32-Bit, Binary Counter Clock with 64-Bit ID The DS1372 has two additional registers that control the alarm counter and interrupts: Control Register (07h) and Status Register (08h). Control Register (07h) Bit # 7 6 5 4 3 2 1 0 Name EOSC ACE 0 0 INTCN RS2 RS1 AIE Reset 0 0 0 0 1 1 1 0 Control Register (07h) Bit 7: Enable Oscillator (EOSC). When set to logic 0, the oscillator is started. When set to logic 1, the oscillator is stopped.
DS1372 I2C, 32-Bit, Binary Counter Clock with 64-Bit ID Status Register (08h) Bit # 7 6 5 4 3 2 1 0 Name OSF 0 0 0 0 0 0 AF Reset 1 0 0 0 0 0 0 0 Status Register (08h) ID Register Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator either is stopped or was stopped for some period of time and may be used to judge the validity of the timekeeping data. This bit is set to logic 1 anytime the oscillator stops.
I2C, 32-Bit, Binary Counter Clock with 64-Bit ID DS1372 SDA tBUF tSP tHD:STA tLOW tR tF SCL tHD:STA STOP tSU:STA tHIGH tSU:DAT START tSU:STO REPEATED START tHD:DAT Figure 4. Data Transfer on I2C Serial Bus SDA MSB SLAVE ADDRESS R/W DIRECTION BIT ACKNOWLEDGEMENT SIGNAL FROM RECEIVER ACKNOWLEDGEMENT SIGNAL FROM RECEIVER SCL 1 2 6 7 8 9 1 2 3–7 8 ACK 9 ACK START CONDITION REPEATED IF MORE BYTES ARE TRANSFERED STOP CONDITION OR REPEATED START CONDITION Figure 5.
DS1372 I2C, 32-Bit, Binary Counter Clock with 64-Bit ID Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain high. Start data transfer: A change in the state of the data line from high to low, while the clock line is high, defines a START condition. Stop data transfer: A change in the state of the data line from low to high, while the clock line is high, defines a STOP condition.
I2C, 32-Bit, Binary Counter Clock with 64-Bit ID S 110100 AD0 0 A XXXXXXXX direction bit (R/W), which is one for a read. The bit position signified by A is compared to the value on the AD0 pin. After receiving and decoding the slave address byte, the device outputs an acknowledge on the SDA line. The DS1372 then begins to transmit data starting with the register address pointed to by the register pointer.
DS1372 I2C, 32-Bit, Binary Counter Clock with 64-Bit ID Chip Information SUBSTRATE CONNECTED TO GROUND PROCESS: CMOS Thermal Information Thermal Resistance (Junction to Ambient) θJA: 221°C/W Thermal Resistance (Junction to Case) θJC: 39°C/W Package Information For the latest package outline information, go to www.maxim-ic.com/packages. PACKAGE DOCUMENT NO. 8-pin μSOP 21-0036 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product.
