Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsIntegrated Circuits (ICs)Timer IC t- real time clock Clock/calendar EDIP 24

1 of 17

19-6715; Rev 6/13

FEATURES

 Integrated NV SRAM, Real-Time Clock,

Crystal, Power-Fail Control Circuit and

Lithium Energy Source

 Clock Registers are Accessed Identically to

the Static RAM; These Registers are

Resident in the Eight Top RAM Locations

 Century Byte Register

 Totally Nonvolatile with Over 10 Years of

Operation in the Absence of Power

 BCD Coded Century, Year, Month, Date,

Day, Hours, Minutes, and Seconds with

Automatic Leap Year Compensation Valid

Up to the year 2100

 Battery Voltage Level Indicator Flag

 Power-Fail Write Protection Allows for ±10%

Power Supply Tolerance

 Lithium Energy Source is Electrically

Disconnected to Retain Freshness until

Power is Applied for the First Time

 Standard JEDEC Bytewide 2k x 8 Static

RAM Pinout

 Quartz Accuracy ±1 Minute a Month at

+25°C, Factory Calibrated

 Underwriters Laboratories (UL) Recognized

PIN CONFIGURATION

ORDERING INFORMATION

PART

VOLTAGE (V)

TEMP RANGE

PIN-PACKAGE

TOP MARK**

DS1742-85+

5.0

0°C to +70°C

24 EDIP (0.740a)

DS1742-85+

DS1742-100+

5.0

0°C to +70°C

24 EDIP (0.740a)

DS1742-100+

DS1742-100IND+

5.0

-40°C to +85°C

24 EDIP (0.740a)

DS1742-100IND+

DS1742W-120+

3.3

0°C to +70°C

24 EDIP (0.740a)

DS1742W-120+

DS1742W-150+

3.3

0°C to +70°C

24 EDIP (0.740a)

DS1742W-150+

+Denotes a lead(Pb)-free/RoHS-compliant device.

**The top mark will include a “+” on lead(Pb)-free devices.

A10

DQ7

DQ6

DQ5

DQ4

DQ3

DQ0

DQ1

DQ2

GND

DS1742

ENCAPSULATED DIP

TOP VIEW

DS1742

Y2KC Nonvolatile Timekeeping RAM

Summary of content (17 pages)

PAGE 1
DS1742 Y2KC Nonvolatile Timekeeping RAM FEATURES            Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit and Lithium Energy Source Clock Registers are Accessed Identically to the Static RAM; These Registers are Resident in the Eight Top RAM Locations Century Byte Register Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power BCD Coded Century, Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap Year Compensation Valid Up to t
PAGE 2
DS1742 PIN DESCRIPTION PIN 1 2 3 4 5 6 7 8 19 22 23 9 10 11 13 14 15 16 17 12 18 20 21 24 NAME A7 A6 A5 A4 A3 A2 A1 A0 A10 A9 A8 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 GND CE OE WE VCC 3B FUNCTION Address Input Data Input/Output Ground Active-Low Chip-Enable Input Active-Low Output-Enable Input Active-Low Write-Enable Input Power-Supply Input DESCRIPTION The DS1742 is a full-function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) and 2k x 8 nonvolatile static RAM.
PAGE 3
DS1742 CLOCK OPERATIONS—READING THE CLOCK While the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the DS1742 clock registers should be halted before clock data is read to prevent reading of data in transition. However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted when a 1 is written into the read bit, bit 6 of the century register, see Table 2.
PAGE 4
DS1742 SETTING THE CLOCK As shown in Table 2, bit 7 of the Control register is the W (write) bit. Setting the W bit to 1 halts updates to the DS1742 registers. The user can subsequently load correct date and time values into all eight registers, followed by a write cycle of 00h to the Control register to clear the W bit and transfer those new settings into the clock, allowing timekeeping operations to resume from the new set point.
PAGE 5
DS1742 Table 2.
PAGE 6
DS1742 RETRIEVING DATA FROM RAM OR CLOCK The DS1742 is in the read mode whenever OE (output enable) is low, WE (write enable) is high, and CE (chip enable) is low. The device architecture allows ripple-through access to any of the address locations in the NV SRAM. Valid data will be available at the DQ pins within tAA after the last address input is stable, providing that the CE and OE access times and states are satisfied.
PAGE 7
DS1742 BATTERY LONGEVITY The DS1742 has a lithium power source that is designed to provide energy for clock activity, and clock and RAM data retention when the VCC supply is not present. The capability of this internal power supply is sufficient to power the DS1742 continuously for the life of the equipment in which it is installed. For specification purposes, the life expectancy is 10 years at 25°C with the internal clock oscillator running in the absence of VCC power.
PAGE 8
DS1742 ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………..-0.3V to +6.0V Storage Temperature Range………………………………………………………...-40°C to +85°C Soldering Temperature (EDIP, leads)..……………………..+260°C for 10 seconds (See Note 7) This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
PAGE 9
DS1742 DC ELECTRICAL CHARACTERISTICS (VCC = 3.3V ±10%, Over the operating range.) PARAMETER SYMBOL 1B 12B Active Supply Current TTL Standby Current ( CE = VIH) CMOS Standby Current ( CE ≥VCC - 0.2V) Input Leakage Current (any input) Output Leakage Current (Any Output) Output Logic 1 Voltage (IOUT = -1.0mA) Output Logic 0 Voltage (IOUT =2.1mA) Write Protection Voltage Battery Switchover Voltage MIN 13B TYP 14B MAX 15B UNITS 16B ICC 10 30 mA 2, 3 ICC1 0.7 2 mA 2, 3 ICC2 0.
PAGE 10
DS1742 AC CHARACTERISTICS—READ CYCLE (3.3V) (VCC = 3.3V ±10%, Over the operating range.
PAGE 11
DS1742 AC CHARACTERISTICS—WRITE CYCLE (5V) (VCC = 5.0V ±10%, Over the operating range.) PARAMETER SYMBOL 38B Write Cycle Time Address Access Time tWC tAS Pulse Width CE Pulse Width Data Setup Time Data Hold time Address Hold Time tWEW tCEW tDS tDH tAH tWEZ tWR WE WE Data Off Time Write Recovery Time 85ns ACCESS MIN 85 0 65 70 35 0 5 MAX 30 5 100ns ACCESS MIN MAX 100 0 70 75 40 0 5 35 5 UNITS ns ns ns ns ns ns ns ns ns AC CHARACTERISTICS—WRITE CYCLE (3.3V) (VCC = 3.
PAGE 12
DS1742 WRITE CYCLE TIMING DIAGRAM—WRITE-ENABLE CONTROLLED WRITE CYCLE TIMING DIAGRAM—CHIP-ENABLE CONTROLLED 12 of 17
PAGE 13
DS1742 POWER-UP/POWER-DOWN CHARACTERISTICS (5V) (VCC = 5.0V ±10%, Over the operating range.
PAGE 14
DS1742 POWER-UP/POWER-DOWN CHARACTERISTICS (3.3V) (VCC = 3.3V ±10%, Over the operating range.) PARAMETER 25B CE or WE at VIH, Before Power- SYMBOL 26B MIN 27B TYP 28B MAX 29B UNITS 30B tPD 0 µs VCC Fall Time: VPF(MAX) to VPF(MIN) tF 300 µs VCC Rise Time: VPF(MIN) to VPF(MAX) tR 0 µs Down Power-Up Recovery Time tREC Expected Data Retention Time (Oscillator On) tDR 35 10 NOTES 31B ms years 5, 6 POWER-UP/POWER-DOWN WAVEFORM TIMING (3.
PAGE 15
DS1742 AC TEST CONDITIONS Output Load: 100pF + 1TTL Gate Input Pulse Levels: 0.0 to 3.0V Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns NOTES: 1) Voltage referenced to ground. 2) Typical values are at +25°C and nominal supplies. 3) Outputs are open. 4) Battery switchover occurs at the lower of either the battery voltage or VPF. 5) Data retention time is at +25°C.
PAGE 16
DS1742 PACKAGE INFORMATION For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
PAGE 17
DS1742 REVISION HISTORY REVISION DATE 041305 071905 060706 022207 102808 6/13 DESCRIPTION 40B Added “UL Recognized” bullet to Features and new Ordering Information table Added new Pin Description table Updated note for Table 2 updated Operating Temperature Range for Absolute Maximum Ratings Corrected 24-pin to 28-pin package and top mark items in Ordering Information table Removed reference to J-STD-020 and indicated the lead soldering temperature of +260°C for 10 seconds max Added DS1742-85, DS1742-85