Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsIntegrated Circuits (ICs)Timer IC t- real time clock Clock/calendar PowerCap 34 (modules)

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19-6719; Rev 9/13

FEATURES

 Integrated NV SRAM, Real-Time Clock,

Crystal, Power-Fail Control Circuit, and

Lithium Energy Source

 Clock Registers are Accessed Identically to

the Static RAM. These Registers Reside in

the Eight Top RAM Locations.

 Century Byte Register

 Totally Nonvolatile with Over 10 Years of

Operation in the Absence of Power

 BCD-Coded Century, Year, Month, Date,

Day, Hours, Minutes, and Seconds with

Automatic Leap Year Compensation Valid

through 2099

 Low-Battery-Voltage Level Indicator Flag

 Power-Fail Write Protection Allows for ±10%

Power-Supply Tolerance

 Lithium Energy Source is Electrically

Disconnected to Retain Freshness Until

Power is Applied for the First Time

 DIP Module Only

Standard JEDEC Bytewide 8k x 8 Static

RAM Pinout

 PowerCap Module Board Only

Surface-Mountable Package for Direct

Connection to PowerCap Containing

Battery and Crystal

Replaceable Battery (PowerCap)

Power-On Reset Output

Pin-for-Pin Compatible with Other Densities

of DS174XP Timekeeping RAM

 Underwriters Laboratories (UL) Recognized

to Prevent Charging of the Internal Lithium

Battery

PIN CONFIGURATIONS

CE2

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

N.C.

A12

DQ0

DQ1

DQ2

GND

28-Pin Encapsulated Package

(28 PIN 740)

DS1743

N.C.

RST

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

GND

N.C.

A12

A11

A10

N.C.

GND

BAT

34-Pin PowerCap Module Board

(Uses DS9034PCX+ or DS9034I-PCX+ PowerCap)

DS1743P

TOP VIEW

DS1743/DS1743P

Y2K-

Compliant, Nonvolatile Timekeeping

RAMs

Summary of content (17 pages)

PAGE 1
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs FEATURES            Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit, and Lithium Energy Source Clock Registers are Accessed Identically to the Static RAM. These Registers Reside in the Eight Top RAM Locations.
PAGE 2
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs PIN DESCRIPTION PIN PDIP PowerCap 1, 2, 3, 1 31–34 2 30 3 25 4 24 5 23 6 22 7 21 8 20 9 19 10 18 11 16 12 15 13 14 14 17 15 13 16 12 17 11 18 10 19 9 NAME FUNCTION N.C.
PAGE 3
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs ORDERING INFORMATION PART TEMP RANGE PIN-PACKAGE DS1743-85+ DS1743-100+ DS1743-100 IND+ DS1743P-85+ DS1743P-100+ DS1743P-100IND+ DS1743W-120+ DS1743W-120 IND+ DS1743W-150+ DS1743W-150 IND+ DS1743WP-120+ DS1743WP-120 IND+ DS9034PCX+ DS9034I-PCX+ 0°C to +70°C 0°C to +70°C -40°C to +85°C 0°C to +70°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 28 EDIP
PAGE 4
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs TIME AND DATE OPERATION The time and date information is obtained by reading the appropriate register bytes. Table 2 shows the RTC registers. The time and date are set or initialized by writing the appropriate register bytes. The contents of the time and date registers are in the BCD format. The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined, but must be sequential (i.e.
PAGE 5
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs Figure 1. Block Diagram Dallas Semiconductor DS1743 Table 1.
PAGE 6
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs The pre-existing contents of the Control register bits 0:5 (Century value) will not be modified by a write cycle to Control if the R bit is being cleared to 0 in that write operation. STOPPING AND STARTING THE CLOCK OSCILLATOR The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off to minimize current drain from the battery. The OSC bit is the MSB (bit 7) of the seconds registers, see Table 2.
PAGE 7
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs Table 2.
PAGE 8
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs WRITING DATA TO RAM OR CLOCK The DS1743 is in the write mode whenever WE, and CE are in their active state. The start of a write is referenced to the latter occurring transition of WE, on CE. The addresses must be held valid throughout the cycle. CE or WE must return inactive for a minimum of tWR prior to the initiation of another read or write cycle. Data in must be valid tDS prior to the end of write and remain valid for tDH afterward.
PAGE 9
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………………-0.3V to +6.0V Storage Temperature Range……………………………………………………………………….-40°C to +85°C Soldering Temperature (EDIP) (leads, 10 seconds)…………………….……………………………..…+260°C Soldering Temperature…………………………………………..….
PAGE 10
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs DC ELECTRICAL CHARACTERISTICS (3.3V) (VCC = 3.3V ±10%, TA = Over the Operating Range.) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Active Supply Current ICC 10 30 mA 2, 3 TTL Standby Current (CE = VIH) CMOS Standby Current (CE ≥ VCC - 0.2V; CE2 = GND + 0.2V) Input Leakage Current (Any Input) Output Leakage Current (Any Output) Output Logic 1 Voltage (IOUT = -1.0mA) Output Logic 0 Voltage (IOUT =2.1mA) Write-Protection Voltage ICC1 0.
PAGE 11
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs AC CHARACTERISTICS—READ CYCLE (3.3V) (VCC = 3.3V ±10%, TA = Over the Operating Range.
PAGE 12
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs AC CHARACTERISTICS—WRITE CYCLE (5V) (VCC = 5.0V ±10%, TA = Over the Operating Range.
PAGE 13
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs WRITE CYCLE TIMING—WRITE-ENABLE CONTROLLED (See Note 5) WRITE CYCLE TIMING— CE /CE2-CONTROLLED (See Note 5) 13 of 17
PAGE 14
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs POWER-UP/DOWN CHARACTERISTICS—5V (VCC = 5.0V ±10%, TA = Over the Operating Range.
PAGE 15
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs POWER-UP/DOWN CHARACTERISTICS—3.3V (VCC = 3.3V ±10%, TA = Over the Operating Range.) PARAMETER CE or WE at VIH, Before Power-Down VCC Fall Time: VPF(MAX) to VPF(MIN) VCC Rise Time: VPF(MIN) to VPF(MAX) VPF to RST High Expected Data-Retention Time (Oscillator On) SYMBOL MIN TYP MAX tPD 0 µs tF tR 300 0 µs µs ms 35 tREC tDR 10 UNITS NOTES years 6, 7 MAX UNITS NOTES POWER-UP/DOWN WAVEFORM TIMING (3.
PAGE 16
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs AC TEST CONDITIONS Output Load: 50 pF + 1TTL Gate Input Pulse Levels: 0 to 3.0V Timing Measurement Reference Levels: Input: 1.5V Output: 1.5V Input Pulse Rise and Fall Times: 5ns NOTES: 1) Voltages are referenced to ground. 2) Typical values are at +25°C and nominal supplies. 3) Outputs are open. 4) Battery switchover occurs at the lower of either the battery terminal voltage or VPF.
PAGE 17
DS1743/DS1743P Y2K-Compliant, Nonvolatile Timekeeping RAMs REVISION HISTORY REVISION DATE 9/13 DESCRIPTION Updated the Ordering Information table; updated the Setting the Clock section added the parameter tCE2A for 3.3V read operation in the AC Characteristics—Read Cycle (3.3V) table PAGES CHANGED 3, 4, 11 17 of 17 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied.