Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - Digital potentiometer linear Non-permanent SO 16

1 of 11 110706

FEATURES

 3V or 5V Operation

 Ultra-Low Power Consumption

 Two Digitally Controlled, 256-Position

Potentiometers

 14-Pin TSSOP (173 mil) and 16-Pin SO (150

mil) Packaging Available for Surface-Mount

Applications

 Addressable Using 3 Address Inputs

 2-Wire Serial Interface

 Operating Temperature Range:

- Industrial: -40°C to +85°C

 Standard Resistance Values:

- DS1803-010 10kΩ

- DS1803-050 50kΩ

- DS1803-100 100kΩ

PIN ASSIGNMENT

PIN DESCRIPTION

L0, L1 - Low End of Resistor

H0, H1 - High End of Resistor

W0,W1 - Wiper terminal of Resistor

- 3V/5V Power Supply Input

A0, A1, A2 - Chip Select Inputs

SDA - Serial Data I/O

SCL - Serial Clock Input

GND - Ground

NC - No Connection

DESCRIPTION

The DS1803 addressable dual digital potentiometer features two independently controlled 256-position

potentiometers. Device control is achieved through a 2-wire serial interface. Three address pins allow up

to 8 DS1803’s to share the same 2-wire interface. The exact wiper position of each potentiometer can be

written or read. The DS1803 is available in a 16-pin DIP, 16-pin SO, and 14-pin TSSOP package. The

device is available in three standard resistance values: 10kΩ, 50kΩ, and 100kΩ and is specified over the

industrial temperature range.

DS1803

Addressable Dual Digital Potentiomete

www.maxim-ic.com

H1 1 14 VCC

L1 2 13 NC

W1 3 12 H0

A2 4 11 L0

A1 5 10 W0

A0 6 9 SDA

GND 7 8 SCL

DS1803 14-PIN TSSOP (173 MIL)

H1 1 16 VCC

NC 2 15 NC

L1 3 14 H0

W1 4 13 L0

A2 5 12 W0

A1 6 11 NC

A0 7 10 SDA

GND 8 9 SCL

DS1803Z 16-PIN SO (150 MIL)

DS1803 16-PIN DIP (300 MIL)

See Mech. Drawings Section on Website

Summary of content (11 pages)

PAGE 1
DS1803 Addressable Dual Digital Potentiometer www.maxim-ic.
PAGE 2
DS1803 DEVICE OPERATION The DS1803 is an addressable, digitally controlled device which has two 256-position potentiometers. A functional block diagram of the part is shown in Figure 1. Communication and control of the device is accomplished via a 2-wire serial interface. Address inputs A0, A1, and A2 allow up to 8 DS1803s to share the same 2-wire interface. Each potentiometer is composed of a 256 position resistor array.
PAGE 3
DS1803 Stop data transfer: A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Figure 2 details how data transfer is accomplished on the 2-wire bus.
PAGE 4
DS1803 SLAVE ADDRESS The control byte is the first byte received following the START condition from the master device. The control byte consists of a four bit control code; for the DS1803, this is 0101 binary. The next three bits of the control byte are the device select bits (A2, A1, A0). They are used by the master device to select which of the devices on the bus are to be accessed. The last bit of the control byte (R/ W *) defines the operation to be performed.
PAGE 5
DS1803 operations that can be used with the DS1803. The binary value of each write command is shown in Figure 5 and also in the Table 1.
PAGE 6
DS1803 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -1.0V to +7.0V -40° to +85°C; industrial -55°C to +125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
PAGE 7
DS1803 ANALOG RESISTOR CHARACTERISTICS PARAMETER SYMBOL End-to-End Resistor Tolerance (-40°C to +85°C;VCC=2.7V to 5.5V) MIN TYP -20 MAX UNITS NOTES +20 % 17 Absolute Linearity ±0.75 LSB 13 Relative Linearity ±0.
PAGE 8
DS1803 5. After this period, the first clock pulse is generated. 6. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 7. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCL signal. 8. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250 ns must then be met.
PAGE 9
DS1803 DS1803 BLOCK DIAGRAM Figure 1 2–WIRE DATA TRANSFER OVERVIEW Figure 2 9 of 11
PAGE 10
DS1803 CONTROL BYTE Figure 3 2–WIRE READ PROTOCOL Figure 4 2–WIRE WRITE PROTOCOL Figure 5 Write Pot-0 10 of 11
PAGE 11
DS1803 TIMING DIAGRAM Figure 6 DS1803 ORDERING INFORMATION ORDERING NUMBER DS18030-010 DS18030-050 DS18030-100 DS1803E-010 DS1803E-050 DS1803E-100 DS1803Z-010 DS1803Z-050 DS1803Z-100 DS1803E-010+ DS1803E-50+ DS1803E-100+ DS1803E-010+T&R DS1803E-50+T&R DS1803Z-010+ DS1803Z-050+ DS1803Z-100+ DS1803Z-010+T&R DS1803Z-050+T&R DS1803Z-100+T&R DS1803-100+T&R DS1803E-10/T&R DS1803E-50/T&R DS1803E-100/T&R DS1803Z-010/T&R DS1803Z-050/T&R DS1803Z-100/T&R PACKAGE 16L DIP 16L DIP 16L DIP 14L TSSOP (173 MIL) 14L TSSOP