Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - Digital potentiometer linear Permanent TSSOP 20

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FEATURES

§ Three linear taper potentiometers

- Two 10kW, 100-position

- One 100kW, 256-position

§ 248 bytes of user EEPROM memory

§ Monitors microprocessor power supply,

voltage sense, and external override

§ Access to data and potentiometer control

through a 2-wire interface

§ External write-protect (WP) pin to protect

data and potentiometer settings

PIN CONFIGURATION

§ Operates from a 5V supply

§ Nonvolatile (NV) wiper storage

§ Packaging: 20-pin TSSOP

§ Programming temperature: 0ºC to +70ºC

§ Industrial operating temperature:

-40ºC to +85ºC

ORDERING INFORMATION

DS1846E-010

DS1846E-010/T&R (Tape-and-Reel Version)

PIN DESCRIPTION

– Power-Supply Input

GND – Ground

SDA – 2-Wire Serial Data

Input/Output

SCL – 2-Wire Serial Clock Input

WP – Write-Protect Input

A0 – Address Input

H0, H1, H2 – High End of Potentiometer

L0, L1, L2 – Low End of Potentiometer

W0, W1, W2 – Wiper Terminal of

Potentiometer

PBRST – Pushbutton Reset Input

NMI – Nonmaskable Interrupt

Output

IN – NMI Voltage Input

RST – Active-Low Reset Output

RST – Active-High Reset Output

OVERVIEW

The DS1846 NV tri-potentiometer, memory, and MicroMonitor™ consists of two 10kW, 100-position

linear taper potentiometers, one 100kW, 256-position linear taper potentiometer; 256 bytes of EEPROM

memory; and a MicroMonitor. The device provides an ideal method for setting bias voltages and currents

in control applications using a minimum of circuitry.

DS1846

NV Tri-Potentiometer,

Memory, and MicroMonito

www.maxim-ic.com

SDA

SCL

NMI

GND

PBRST

RST

20-Pin TSSOP

MicroMonitor is a trademark of Dallas Semiconductor.

Summary of content (18 pages)

PAGE 1
www.maxim-ic.
PAGE 2
DS1846 The EEPROM memory allows a user to store configuration or calibration data for a specific system or device and provides control of the potentiometer wiper settings. Any type of user information can reside in the first 248 bytes (00h to F7h) of this memory. The next three bytes of memory (F8h to FAh) are for potentiometer settings and the last five addresses of EEPROM memory (FBh to FFh) are reserved. These reserved and potentiometer registers should not be used for data storage.
PAGE 3
DS1846 PIN DESCRIPTIONS VCC—Power-Supply Terminal. The DS1846 will support supply voltages ranging from +4.5V to +5.5V. GND—Ground Terminal SDA—2-Wire Serial Data Interface. The serial data pin is for serial data transfer to and from the DS1846. The pin is open drain and can be wire-ORed with other open-drain or open-collector interfaces. SCL—2-Wire Serial Clock Interface. The serial clock input is used to clock data into the DS1846 on rising edges and clock data out on falling edges. WP—Write Protect.
PAGE 4
DS1846 MEMORY ORGANIZATION The EEPROM of the DS1846 contains 256 bytes. Bytes 00h to F7h are general-purpose user memory. The next three bytes, F8h, F9h, and FAh, contain the wiper settings for each of the potentiometers (see Table 1). The last five bytes, FBh to FFh, are reserved and should not be used. The memory, internal to the device, is organized as 32 pages of eight bytes each.
PAGE 5
DS1846 2-WIRE OPERATION Clock and Data Transitions: The SDA pin is normally pulled high with an external resistor or device. Data on the SDA pin may only change during SCL low time periods. Data changes during SCL high periods indicates a start or stop condition depending on the conditions discussed below. See the timing diagrams for further details (Figures 2 and 3). Start Condition: A high-to-low transition of SDA with SCL high is a start condition, which must precede any other command.
PAGE 6
DS1846 DS1846 is not latched into EEPROM. Note that in order for eight bytes to be stored sequentially (and to prevent looping around), the address byte must be set to the beginning of the desired page (three LSBs of the address are 0). For detailed information concerning page operations, see the MEMORY ORGANIZATION section. The DS1846 is capable of an 8-byte page write. A page write is initiated the same way as a byte write, but the master does not send a stop condition after the first data byte.
PAGE 7
DS1846 2-WIRE SERIAL PORT OPERATION The 2-wire serial port interface supports a bidirectional data transmission protocol with device addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a “master.” The devices that are controlled by the master are “slaves.
PAGE 8
DS1846 Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the byte has been received. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account.
PAGE 9
DS1846 WRITE PROTECT The WP pin protects EEPROM data and potentiometer position from alteration in an application. This pin must be open or connected high to protect data from alteration. WP has an internal pullup (RWP). READING AND WRITING THE POTENTIOMETER VALUES Reading from and writing to the potentiometers consists of a standard read or write to EEPROM memory at the addresses F8h, F9h, and FAh. The 8-bit value at address F8h controls the wiper setting for potentiometer 1, which has 256 positions.
PAGE 10
DS1846 DEVICE OPERATION Power Monitor The DS1846 detects out-of-tolerance power-supply conditions and warns a processor-based system of an impending power failure. When VCC falls below the minimum VCC tolerance, a comparator asserts the RST and RST signals. On power-up, RST and RST are kept active for a minimum of tRST to allow the power supply and processor to stabilize. Pushbutton Reset The DS1846 provides an input pin for direct connection to a pushbutton reset (see Figure 4).
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DS1846 TYPICAL APPLICATION Figure 4 VCC Optional, see note. Vsense VVcc CC To 2-Wire Master SDA Vcc SCL IN A0 To Microprocessor Interrupt Potentiometer Terminals /PBRST WP /RST /NMI RST Reset Outputs L0 DS1846 H0 W1 W0 L1 H1 L2 W2 GND H2 Potentiometer Terminals Note: NMI can be used to produce a reset, which is shown by the dotted line in Figure 4. The following equations are used to calculate the resistor values when using VSENSE.
PAGE 12
DS1846 TIMING DIAGRAM: PUSHBUTTON RESET Figure 5 TIMING DIAGRAM: NONMASKABLE INTERRUPT Figure 6 tNMI 12 of 18
PAGE 13
DS1846 TIMING DIAGRAM: POWER-DOWN Figure 7 tVF TIMING DIAGRAM: POWER-UP Figure 8 tVR 13 of 18
PAGE 14
DS1846 ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Range Programming Temperature Range Storage Temperature Range Soldering Temperature -0.5V to +6.0V -40°C to +85°C; Industrial 0°C to +70°C -55°C to +125°C See IPC/JEDEC J-STD-020A specification * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
PAGE 15
DS1846 DC ELECTRICAL CHARACTERISTICS PARAMETER Input Leakage Current Standby Current SYMBOL CONDITION IIL ISTBY VOL1 (-40°C to +85°C; VCC = 4.5V to 5.5V) MIN TYP MAX UNITS +200 nA mA 0 200 0.4 0 0.6 -200 100 3mA sink current 6mA sink current Low-Level Output Voltage (SDA) VOL2 I/O Capacitance Output at 2.4V CI/O IOH -1.0 pF mA IOH -0.5 mA IOL RWP 40 65 4 100 mA kW RPBR 25 40 60 kW VCCTP VTP 4.15 1.15 4.3 1.2 4.40 1.25 V V NMI Output at 2.4V Output at 0.
PAGE 16
DS1846 AC ELECTRICAL CHARACTERISTICS PARAMETER SCL Clock Frequency SYMBOL fSCL Bus Free Time Between Stop and Start Condition Hold Time (Repeated) Start Condition Low Period of SCL Clock High Period of SCL Clock Data Hold Time tBUF tHD:DAT Data Setup Time tSU:DAT Rise Time of Both SDA and SCL Signals Fall Time of Both SDA and SCL Signals Setup Time for Stop Condition Pulse Width of Spikes (which must be suppressed by input filter) Capacitive Load for each Bus Line EEPROM Write Time = VIL Reset Acti
PAGE 17
DS1846 ANALOG RESISTOR CHARACTERISTICS (-40°C to +85°C; VCC = 4.5V to 5.5V) PARAMETER Wiper Resistance End-to-End Resistance Absolute Linearity Relative Linearity -3dB Cutoff Frequency Temperature Coefficient SYMBOL RW fcutoff CONDITION MIN 10kW pot 100kW pot 10kW pot 100kW pot 7 70 -1 -3 -0.25 TYP 300 9 90 350 34 750 10kW pot 100kW pot 17 of 18 MAX 600 11 110 +1 +3 +0.
PAGE 18
DS1846 NOTES: 1) All voltages are referenced to ground. 2) I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VCC is switched off. 3) ISTBY specified with VCC = 5.0V and control port logic pins are driven to the appropriate logic levels. Appropriate logic levels specify that logic inputs are within a 0.5V of ground or VCC for the corresponding inactive state. All inputs should be connected high.