Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsData collecting ICsData acquisition IC - Digital potentiometer linear Non-permanent SOIC 16

FEATURES

§ Two digitally controlled, 256-position

potentiometers

§ Serial port provides means for setting and

reading both potentiometers

§ Resistors can be connected in series to

provide increased total resistance

§ 20-pin TSSOP and 16-pin SO packages are

available

§ Resistive elements are temperature

compensated to ±0.3 LSB relative linearity

§ Standard resistance values:

- DS1868B-10 ∼10kΩ

- DS1868B-50 ∼50kΩ

- DS1868B-100 ∼100kΩ

§ +5V or ±3V operation

§ Operating temperature range:

Industrial: -40°C to +85°C

PIN DESCRIPTION

L0, L1 - Low End of Resistor

H0, H1 - High End of Resistor

W0, W1 - Wiper Terminal of Resistor

OUT

- Stacked Configuration Output

RST

- Serial Port Reset Input

DQ - Serial Port Data Input

CLK - Serial Port Clock Input

OUT

- Cascade Port Output

- +5 Volt Supply

GND - Ground Connections

NC - No Internal Connection

- Substrate Bias Voltage

DNC - Do Not Connect

*All GND pins must be connected to ground.

PIN ASSIGNMENT

PART NO.

PIN-

PACKAGE

END-TO-END

RESISTANCE

(kΩ)

DS1868BE-010+

20 TSSOP

DS1868BE-050+

20 TSSOP

DS1868BE-100+

20 TSSOP

100

DS1868BS-010+

16 SO

DS1868BS-050+

16 SO

DS1868BS-100+

16 SO

100

DS1868B

Dual Digital Potentiometer

www. maximintegrated.com

20-Pin TSSOP (173-mil)

DNC

RST

CLK

DNC

GND

DNC

OUT

DNC

DS1868BS 16-Pin SO (300-mil)

RST

CLK

GND

OUT

19-6593; Rev 1; 1/14 Maxim Integrated 1

Summary of content (13 pages)

PAGE 1
www. maximintegrated.com FEATURES § § § § § § § § Two digitally controlled, 256-position potentiometers Serial port provides means for setting and reading both potentiometers Resistors can be connected in series to provide increased total resistance 20-pin TSSOP and 16-pin SO packages are available Resistive elements are temperature compensated to ±0.
PAGE 2
DESCRIPTION DS1868B The DS1868B Dual Digital Potentiometer Chip consists of two digitally controlled solid-state potentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the wiper on the resistor array is set by an 8-bit value that controls which tap point is connected to the wiper output.
PAGE 3
DS1868B BLOCK DIAGRAM Figure 1 DS1868B I/O SHIFT REGISTER Figure 2 Transmission of data always begins with the stack select bit followed by the potentiometer-1 wiper position value and lastly the potentiometer-0 wiper position value. When wiper position data is to be written to the DS1868B, 17 bits (or some integer multiple) of data should always be transmitted.
PAGE 4
STACKED CONFIGURATION Figure 3 DS1868B CASCADE OPERATION A feature of the DS1868B is the ability to control multiple devices from a single processor. Multiple DS1868Bs can be linked or daisy-chained as shown in Figure 4. As a data bit is entered into the I/O shift register of the DS1868B a bit will appear at the COUT output after a minimum delay of 50ns. The stack select bit of the DS1868B will always be the first out of the part at the beginning of a transaction.
PAGE 5
ABSOLUTE AND RELATIVE LINEARITY DS1868B Absolute linearity, also known as Integral Nonlinearity, is defined as the difference between the actual measured output voltage and the expected output voltage. Figure 5 presents the test circuit used to measure absolute linearity. Absolute linearity is given in terms of a minimum increment or expected output when the wiper is moved one position. In the case of the test circuit, a minimum increment (MI) or one LSB would equal 5/256V.
PAGE 6
DS1868B ABSOLUTE AND RELATIVE LINEARITY Figure 6 DS1868B Linearity vs. Tap Position 0.5 DS1868B 10kΩ 0.4 0.3 0.2 DNL LSB 0.1 0 -0.1 -0.2 -0.3 INL -0.4 -0.5 0 32 64 96 128 160 192 224 256 Tap Position TYPICAL APPLICATION CONFIGURATIONS Figures 7 and 8 show two typical application configurations for the DS1868B.
PAGE 7
VARIABLE GAIN AMPLIFIER Figure 7 DS1868B FIXED GAIN ATTENUATOR Figure 8 Maxim Integrated .............................................................................................................................................................................................
PAGE 8
DS1868B ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground (VB = GND) ......................................................... -0.5V to +7.0V Voltage on Any Pin when VB = -3.3V ......................................................................... -3.3V to (VCC + 0.5) Operating Temperature ....................................................................................................... -40°C to +85°C Storage Temperature ...............................................................
PAGE 9
DS1868B CAPACITANCE PARAMETER Input Capacitance Output Capacitance SYMBOL TYP MAX UNITS CIN 5 pF COUT 7 pF AC ELECTRICAL CHARACTERISTICS PARAMETER CLK Frequency MIN (TA = +25°C) SYMBOL fCLK NOTES (-40°C to +85°C; VCC = 5.0V ±10%) MIN DC TYP MAX 3.
PAGE 10
TIMING DIAGRAMS Figure 9 DS1868B (a) 3-Wire Serial Interface General Overview (b) Start of Communication Transaction (c) End of Communication Transaction Maxim Integrated ...........................................................................................................................................................................................
PAGE 11
DS1868B TYPICAL SUPPLY CURRENT VS. SERIAL CLOCK RATE Figure 10 Maxim Integrated ...........................................................................................................................................................................................
PAGE 12
DS1868B DS1868B 20-PIN TSSOP DIM MIN MAX A MM - 1.10 A1 MM 0.05 - A2 MM 0.75 1.05 C MM 0.09 0.18 L MM 0.50 0.70 e1 MM 0.65 BSC B MM 0.18 0.30 D MM 6.40 6.90 E MM 4.40 NOM G MM 0.25 REF H MM 6.25 6.55 phi 0° 8° PACKAGE INFORMATION For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only.
PAGE 13
DS1868B REVISION HISTORY REVISION DATE 2/13 1/14 DESCRIPTION Initial Release Removed future product notation in Ordering Information PAGES CHANGED — 1 13 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.