Datasheet

56 Maxim Integrated
SFP Controller for Dual Rx Interface
DS1877
Table 02h, Register BEh: HLOS1
Table 02h, Register BDh: RESERVED
Table 02h, Register BFh: LLOS1
FACTORY DEFAULT 00h
READ ACCESS N/A
WRITE ACCESS N/A
A2h AND B2h MEMORY N/A
MEMORY TYPE N/A
This register is reserved.
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS (PW2 and QT2EN = 0) or (PW1 and RWTBL2 and QT2EN = 0)
A2h AND B2h MEMORY Common A2h and B2h memory locations
MEMORY TYPE Nonvolatile (SEE)
BFh 2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
BIT 7 BIT 0
Fast comparison DAC threshold adjust for low LOS1. See HLOS1 (Table 02h, Register BEh) for the functional
description.
FACTORY DEFAULT 00h
READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2)
WRITE ACCESS (PW2 and QT2EN = 0) or (PW1 and RWTBL2 and QT2EN = 0)
A2h AND B2h MEMORY Common A2h and B2h memory locations
MEMORY TYPE Nonvolatile (SEE)
BEh 2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
BIT 7 BIT 0
Fast comparison DAC threshold adjust for high LOS1. The combination of HLOS1 and LLOS1 creates a hys-
teresis comparator. As RSSI1 falls below the LLOS1 threshold, the LOS1 LO alarm bit is set to 1. The LOS1 LO
alarm remains set until the RSSI1 input is found above the HLOS1 threshold setting, which clears the LOS1 LO
alarm bit and sets the LOS1 HI alarm bit.