Datasheet
DS1878
SFP+ Controller with Digital LDD Interface
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LUT LOADED TO [7:0]
LUT LOADED TO [7:0]
DAC[1/2]TI
8
7
6
5
4
3
2
1
0
DAC[1/2]TI
DAC[1/2]TC = 0
TEMPERATURE (°C)
-40 +102
TEMPERATURE (°C)
-40 +102
DAC[1/2]TC = 1
LUT LOADED TO [8:1]
(DAC BIT 0 = 0)
LUT LOADED TO [8:1]
(DAC BIT 0 = 0)
DELTA-SIGMA DACA OR DACB
8
7
6
5
4
3
2
1
0
DELTA-SIGMA DACA OR DACB
Figure 13. DAC1/DAC2 LUT Assignments
In LUT mode, DAC1 and DAC2 are each controlled by
a separate 8-bit, 4°C-resolution, temperature-
addressed LUT. The delta-sigma outputs use a 10-bit
structure. The 8-bit LUTs are either loaded directly into
the MSBs (8:1) or the LSBs (7:0). This is determined by
DAC1TI (Table 02h, Register C3h), DAC2TI (Table 02h,
Register C4h), DAC1TC (Table 02h, Register C6h, bit
6), and DAC2TC (Table 02h, Register C6h, bit 5). See
Figure 13 for more details. The DAC1 LUT (Table 07h)
and DAC2 LUT (Table 08h) registers are nonvolatile
and password-2 protected.
The reference input, REFIN, is the supply voltage for
the output buffer of DAC1 and DAC2. The voltage con-
nected to REFIN must be able to support the edge rate
requirements of the delta-sigma outputs. In a typical
application, a 0.1µF capacitor should be connected
between REFIN and ground.
Digital I/O Pins
Five digital input and four digital output pins are provid-
ed for monitoring and control.
LOS, LOSOUT
By default (LOSC = 1, Table 02h, Register 89h), the
LOS pin is used to convert a standard comparator out-
put for loss of signal (LOS) to an open-collector output.
This means the mux shown in the
Block Diagram
by
default selects the LOS pin as the source for the
LOSOUT output transistor. The output of the mux can
be read in the STATUS byte (Lower Memory,
Register 6Eh) as the RXL bit. The RXL signal can be
inverted (INV LOS = 1) before driving the open-drain
output transistor using the XOR gate provided. Setting
LOSC = 0 configures the mux to be controlled by LOS
LO, which is driven by the output of the LOS quick trip
(Table 02h, Registers BEh and BFh). The mux setting
(stored in EEPROM) does not take effect until V
CC
>
POA, allowing the EEPROM to recall.