Datasheet
DS1878
IN1, RSEL, RSELOUT
The digital input IN1 and RSEL pins primarily serve to
meet the rate-select requirements of SFP and SFP+.
They also serve as general-purpose inputs. RSELOUT is
driven by a combination of the RSEL and logic dictated
by control registers in the EEPROM (Figure 16). The lev-
els of IN1 and RSEL can be read using the STATUS reg-
ister (Lower Memory, Register 6Eh). The open-drain
RSELOUT output is software-controlled and/or inverted
through the STATUS register and CNFGA register
(Table 02h, Register 89h). External pullup resistors must
be provided on RSELOUT to realize a high logic level.
The RSEL pin determines the value sent by the 3-wire
master to the limiting amplifier’s SETLOS register. When
RSEL is high, SETLOSH is used. When RSEL is low,
SETLOSL is used. The DS1878 can transmit a bit on the
3-wire bus to Register 0x00 (bit 1) of the MAX3945,
MAX3798, MAX3799, or RXCTRL1 (Table 02h, Register
E8h) within 80ms of a transition (rising or falling) on the
RSELOUT. This bit indicates the status of RSELOUT.
This feature is user programmable. A bit (RSELPIN,
Table 02h, Register 89h) is provided to determine
whether the I
2
C register RXCTRL1 or the status of the
RSELOUT pin is transmitted. When RSELPIN is set to 1,
the status of RSELOUT is sent out. RSELOUT is deter-
mined by RSEL pin, RSELC control bit, and INVRSOUT
control bit as shown in Figure 14.
The INVRSOUT bit inverts the RSELOUT bit, and this
inversion is reflected when this bit is sent out on the 3-
wire bus. Figure 14 illustrates the timing for the 3-wire
communication when RSELPIN is set to 1.
TXD, TXDOUT
TXDOUT is generated from a combination of TXFOUT,
TXD, and the internal signal FETG. A software control
identical to TXD is available (TXDC, Lower Memory,
Register 6Eh). A TXD pulse is internally extended
(t
INITR1
) to inhibit the latching of low alarms and warn-
ings related to the APC loop to allow for the loop to sta-
bilize. The nonlatching alarms and warnings are TXP
SFP+ Controller with Digital LDD Interface
22 ______________________________________________________________________________________
V
POA
V
CC
RSEL
RSELOUT
3W 0x00 BIT1
< 1μs
< 1μs
< 80ms
POV = 0
CONDITION: INVRSOUT = 0, RSELPIN = 1.
< 80ms
Figure 14. 3-Wire Communication on RSELOUT Transition