Datasheet

DS1878
SFP+ Controller with Digital LDD Interface
38 ______________________________________________________________________________________
Table 08h Register Map
TABLE 07h (DAC1 LUT)
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(HEX)
ROW
NAME
BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80–9F
<8>
LUT7 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1 DAC1
A0
<8>
LUT7 DAC1 DAC1 DAC1 DAC1 RESERVED RESERVED RESERVED RESERVED
ACCESS
CODE
<0> <1> <2> <3> <4> <5> <6> <7> <8> <9> <10> <11>
Read
Access
All All All PW2 All N/A PW1 PW2 N/A PW2 All
Write
Access
See each
bit/byte
separately
PW2 N/A
All and
device
hardware
PW2 +
mode
bit
All All PW1 PW2 PW2 N/A PW1
TABLE 08h (DAC2 LUT)
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(HEX)
ROW
NAME
BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
80–9F
<8>
LUT8 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2 DAC2
A0
<8>
LUT8 DAC2 DAC2 DAC2 DAC2 RESERVED RESERVED RESERVED RESERVED
Table 07h Register Map
Auxiliary A0h Memory Register Map
The access codes represent the factory default values of PW_ENA and PW_ENB (Table 02h, Registers C0h–C1h).
AUXILIARY MEMORY (A0h)
WORD 0 WORD 1 WORD 2 WORD 3
ROW
(HEX)
ROW
NAME
BYTE 0/8 BYTE 1/9 BYTE 2/A BYTE 3/B BYTE 4/C BYTE 5/D BYTE 6/E BYTE 7/F
00–FF
<5>
AUX EE EE EE EE EE EE EE EE EE