Datasheet

DS1878
SFP+ Controller with Digital LDD Interface
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Lower Memory, Register 71h: ALARM
2
POWER-ON VALUE 00h
READ ACCESS All
WRITE ACCESS N/A
MEMORY TYPE Volatile
71h MON3 HI MON3 LO MON4 HI MON4 LO RESERVED TXFS FETG TXFINT
BIT 7 BIT 0
BIT 7
MON3 HI: High-alarm status for MON3 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 6
MON3 LO: Low-alarm status for MON3 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 5
MON4 HI: High-alarm status for MON4 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or below threshold setting.
1 = Last measurement was above threshold setting.
BIT 4
MON4 LO: Low-alarm status for MON4 measurement. A TXD event does not clear this alarm.
0 = (Default) Last measurement was equal to or above threshold setting.
1 = Last measurement was below threshold setting.
BIT 3 RESERVED
BIT 2
TXFS: Reflects the status of the TXF pin. The status also includes any inversion caused by the INVTXF
bit (read only).
0 = TXF pin is low (after any inversion caused by the INVTXF bit).
1 = TXF pin is high (after any inversion caused by the INVTXF bit).
BIT 1
FETG: Status of Internal Signal FETG. The FETG signal is part of the internal shutdown logic.
0 = FETG is low.
1 = FETG is high.
BIT 0
TXFINT: TXFOUT Interrupt. This bit is the wire-ORed logic of all alarms and warnings wire-ANDed with
their corresponding enable bits in addition to nonmaskable alarms TXP HI, TXP LO, BIAS MAX, and HBAL.
The enable bits are found in Table 01h/05h, Registers F8h–FFh.