Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsInterface ICsInterface IC - customised TQFN 24

DS1886

SFP and PON ONU Controller

with Digital LDD Interface

General Description

The DS1886 controls and monitors all functions for SFF,

SFP, and SFP+ modules including all SFF-8472 func-

tionality for GPON/EPON and 10G PON ONU applica-

tions. The combination of the DS1886 with the MAX3710

supports all transmitter and receiver functionality. The

DS1886 includes modulation current control and APC set-

point control with tracking error adjustment. It continually

monitors RSSI for LOS generation. A 13-bit analog-to-

digital converter (ADC) monitors V

, temperature, laser

bias, laser modulation, and receive power to meet all

monitoring requirements. Receive power measurement

is differential with support for common mode to V

. A

9-bit digital-to-analog converter (DAC) is included with

temperature compensation for APD bias control.

Applications

SFF, SFP, and PON ONU Modules

Features

S Meets All SFF-8472 Control and Monitoring

Requirements

S Companion Controller for the MAX3710 Laser

Driver/Limiting Amplifier and MAX3945 Limiting

Amplifier

S MAX3710/DS1886 Combination Supports

Broad Spectrum of Continuous Mode and PON

Applications Up to 2.5GHz

S Temperature Lookup Table (LUT) to Compensate

for APC Tracking Error and Dual Closed-Loop

Variables

S Three Laser Control Modes



Dual Closed Loop: Laser Bias and Laser

Modulation Are Automatically Controlled with

Multiple LUTs to Compensate Dual Closed-Loop

Calibration Points



APC Loop: Laser Bias Automatically Controlled,

Laser Modulation Controlled by Temperature LUT



Open Loop: Laser Bias and Laser Modulation

Are Controlled by Temperature LUTs

S 13-Bit ADC



Laser Bias, Laser Power, and Receive Power

Support Internal and External Calibration



Differential Receive Power Input



Scalable Dynamic Range



Internal Direct-to-Digital Temperature Sensor



Alarm and Warning Flags for All Monitored

Channels

S 10-Bit DAC with Temperature Compensation for

APD Bias

S Digital I/O Pins: Transmit Disable Input/Output,

Rate Select Input, LOS Input/Output, Transmit

Fault Input/Output, and IN1 Status Monitor and

Fault input

S Comprehensive Fault Measurement System with

Maskable Alarm/Warnings

S Flexible Password Scheme Provides Three Levels

of Security

S 256-Byte A0h and 128-Byte Upper A2h EEPROM

S I

C-Compatible Interface

S 3-Wire Master to Communicate with the MAX3710/

MAX3711 Laser Driver/Limiting Amplifier and

MAX3945 Limiting Amplifier

19-6259; Rev 1; 8/12

Ordering Information appears at end of data sheet.

For pricing, delivery, and ordering information, please contact Maxim Direct at

1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Summary of content (92 pages)

PAGE 1
DS1886 SFP and PON ONU Controller with Digital LDD Interface General Description The DS1886 controls and monitors all functions for SFF, SFP, and SFP+ modules including all SFF-8472 functionality for GPON/EPON and 10G PON ONU applications. The combination of the DS1886 with the MAX3710 supports all transmitter and receiver functionality. The DS1886 includes modulation current control and APC setpoint control with tracking error adjustment. It continually monitors RSSI for LOS generation.
PAGE 2
DS1886 SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
DS1886 SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) LOS, LOSOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 RSEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 TXD, TXDOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
DS1886 SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) A2h Lower Memory, Register 04h–05h: TEMP WARN HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 A2h Lower Memory, Register 02h–03h: TEMP ALARM LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 A2h Lower Memory, Register 06h–07h: TEMP WARN LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 5
DS1886 SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) A2h Lower Memory, Register 7Bh–7Eh: PASSWORD ENTRY (PWE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 A2h Lower Memory, Register 7Fh: TBL SEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 A2h Table 01h Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 6
DS1886 SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) A2h Table 02h, Register A4h–A5h: TXB OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 A2h Table 02h, Register A6h–A7h: TXP OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 A2h Table 02h, Register A8h–A9h: RSSI FINE OFFSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 7
DS1886 SFP and PON ONU Controller with Digital LDD Interface TABLE OF CONTENTS (continued) A2h Table 02h, Register EFh: 3WSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 A2h Table 02h, Register F0h: 3WCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 A2h Table 02h, Register F1h: ADDRESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 8
DS1886 SFP and PON ONU Controller with Digital LDD Interface LIST OF FIGURES Figure 1a. ADC Channel Only for TXP when BURST_MODE = 1 in Table 02h, Register 89h . . . . . . . . . . . . . . . . . . . 19 Figure 1b. ADC Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 2. ADC Round-Robin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 9
DS1886 SFP and PON ONU Controller with Digital LDD Interface LIST OF TABLES Table 1. Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 2. ADC Default Monitor Full-Scale Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 3. RSSI Hysteresis Threshold Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 10
DS1886 SFP and PON ONU Controller with Digital LDD Interface ABSOLUTE MAXIMUM RATINGS (All voltages relative to ground.) Voltage Range on IN1, DAC, LOS, RSSIP, RSSIN, REFIN, RSEL, TXF, TXMON, TXD.......... -0.5V to (VCC + 0.5V) (subject to not exceeding +6V) Voltage Range on VCC, SDA, SCL, TXFOUT and LOSOUT........................................................-0.5V to +6V Continuous Power Dissipation (TA = +70NC) TQFN (derate 28.6mW/NC above +70NC)................2285.7mW Operating Temperature Range.....
PAGE 11
DS1886 SFP and PON ONU Controller with Digital LDD Interface DAC ELECTRICAL CHARACTERISTICS (VCC = +2.97V to +3.63V, TA = -40NC to +95NC, unless otherwise noted.) (Note 1) PARAMETER Delta-Sigma Input Clock Frequency Reference Voltage Input (REFIN) SYMBOL CONDITIONS VREFIN Minimum 0.1µF to GND RDS tINIT_DAC MAX MHz VCC V 0 VREFIN V 10 Bits 100 I See the Startup Timing Characteristics table ms VREFIN = 2.
PAGE 12
DS1886 SFP and PON ONU Controller with Digital LDD Interface AC ELECTRICAL CHARACTERISTICS (VCC = +2.97V to +3.63V, TA = -40NC to +95NC, unless otherwise noted.
PAGE 13
DS1886 SFP and PON ONU Controller with Digital LDD Interface I2C AC ELECTRICAL CHARACTERISTICS (VCC = +2.97V to +3.63V, TA = -40NC to +95NC, unless otherwise noted. Timing is referenced to VIL(MAX) and VIH(MIN).) (Note 1) (See Figure 19.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz SCL Clock Frequency fSCL Clock Pulse-Width Low tLOW 1.3 Fs Clock Pulse-Width High tHIGH 0.6 Fs Bus Free Time Between STOP and START Condition tBUF 1.3 Fs tHD:STA 0.
PAGE 14
DS1886 SFP and PON ONU Controller with Digital LDD Interface Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. SUPPLY VOLTAGE +95°C 0.65 0.60 +25°C 0.55 0.50 -40°C 0.45 0.9 VCC = 3.9V 0.8 SUPPLY CURRENT (mA) 0.40 0.7 0.6 0.5 0.3 0.2 0.35 0.1 SDA = SCL = VCC 0.30 2.85 3.10 3.35 3.60 SDA = SCL = VCC 0 3.85 10 -40 VCC (V) TXMON AND RSSI DNL 1 0 -1 USING FACTORY-PROGRAMMED FULL-SCALE VALUE OF 2.5V -3 0 0.5 1.0 1.5 2.0 VCC = 3.3V 0.
PAGE 15
DS1886 SFP and PON ONU Controller with Digital LDD Interface TXF LOSOUT SDAOUT SCLOUT CSEL1OUT Pin Configuration 24 23 22 21 20 TOP VIEW + Pin Description PIN NAME FUNCTION 1 CSEL2OUT 2 SCL I2C Serial-Clock Input 3 SDA Open-Drain I2C Serial-Data Input/ Output 4 TXFOUT Open-Drain Transmit Fault Output 5 LOS Loss-of-Signal Input Chip-Select Output. Part of the 3-wire interface to the MAX3945.
PAGE 16
DS1886 SFP and PON ONU Controller with Digital LDD Interface Block Diagram REFIN A2h MEMORY EEPROM/SRAM SDA I2C INTERFACE SCL VCC EEPROM 256 BYTES AT A0h 10-BIT DELTA-SIGMA DAC ADC CONFIGURATION/RESULTS, SYSTEM STATUS/CONTROL BITS, ALARMS/WARNINGS, LOOKUP TABLES, USER MEMORY SDAOUT VCC TXP RSSIP CSEL1OUT 13-BIT ADC DS1886 POA AND POD RESET RSSIN SCLOUT CSEL2OUT CALCULATED TXP TXMON ANALOG MUX MON_SEL 3-WIRE MASTER TXB TXFOUT TEMPERATURE SENSOR TXD VCC CONFIGURABLE LOGIC TXF TXDOUT
PAGE 17
DS1886 SFP and PON ONU Controller with Digital LDD Interface Typical Operating Circuit—GPON ONU DS3920 CURRENT MONITOR DC-DC OUTPUT APD-TIA MAX3710 LA LOS LOS DAC 3W MD AND DFB MOD DAC FAULT DISABLE BIAS DAC LPD LASER SIGNAL DETECT LDD MDIN BMON 3W 2.
PAGE 18
DS1886 SFP and PON ONU Controller with Digital LDD Interface Typical Operating Circuit—10G PON ONU DS3920 CURRENT MONITOR DC-DC OUTPUT 10G APD-TIA MAX3945 10G LA LOS 3W MAX3710 3W MD AND DFB 1.25G TO 2.5G TOSA MOD DAC FAULT DISABLE BIAS DAC LPD LDD MDIN BMON 3W 2.
PAGE 19
DS1886 SFP and PON ONU Controller with Digital LDD Interface Monitors and Fault Detection Detailed Description Monitors The DS1886 monitors five ADC channels. This monitoring combined with the alarm enables (A2h Table 01h/05h) determines when/if the DS1886 turns off the MAX3710 DACs and triggers the TXFOUT and TXDOUT outputs. All the monitoring levels and interrupt masks are userprogrammable. See Figure 1a.
PAGE 20
DS1886 SFP and PON ONU Controller with Digital LDD Interface ADC Monitors and Alarms The ADC monitors temperature (internal temp sensor), VCC, laser bias (TXB), laser power (TXP), and receive power (RSSIC for coarse, RSSIF for fine) using an analog multiplexer to measure them using a round-robin scheme with a single ADC (see the ADC Timing section).
PAGE 21
DS1886 SFP and PON ONU Controller with Digital LDD Interface RIGHT-SHIFT2 is determined TXCTRL3[2:1] as follows: by KRMD[1:0], KRMD[1:0] TXCTRL3[4:3] NO. OF RIGHT-SHIFTS 00 2 01 1 10 0 11 0 must calibrate the corresponding monitors to achieve the correct LSB weighting.
PAGE 22
DS1886 SFP and PON ONU Controller with Digital LDD Interface Laser Bias and Laser Power Through TXMON The DS1886 measures both laser bias (TXB) and laser power (TXP) through the same input pin, TXMON. The DS1886 commands the MAX3710 laser driver to output the correct monitor signal before each ADC conversions takes place. Figure 4 shows the two conversion paths. Each path has independent gain and offset calibration registers.
PAGE 23
DS1886 SFP and PON ONU Controller with Digital LDD Interface gives the best resolution for the measurement. Table 3 shows the threshold values for each possible number of right-shifts. PIN Mode The PIN mode is intended for systems with a linear relationship between the RSSI input and desired ADC result. The ADC result transitions between the fine and coarse ranges with hysteresis, as shown in Figure 6. Low-Voltage Operation The DS1886 contains two power-on reset (POR) levels.
PAGE 24
DS1886 SFP and PON ONU Controller with Digital LDD Interface circuitry is disabled. When VCC reaches POA, the SEE is recalled, and the analog circuitry is enabled. While VCC remains above POA, the device is in its normal operating state, and it responds based on its nonvolatile configuration. If during operation VCC falls below POA, but is still above POD, the SRAM retains the SEE settings from the first SEE recall, but the device analog is shut down and the outputs are disabled.
PAGE 25
DS1886 SFP and PON ONU Controller with Digital LDD Interface Delta-Sigma Output and Reference One delta-sigma output (DAC) is provided. This provides a 10-bit resolution output. The maximum voltage output is set by the input REFIN. An inexpensive shunt reference is recommended to generate the voltage applied to REFIN, as shown in Figure 8.
PAGE 26
DS1886 SFP and PON ONU Controller with Digital LDD Interface VCC TXDS RPU TXD C TXDC TXD R C D TXDIO Q TXDOUT Q TXDFLT TXFOUTS TXFOUT TXFINT INVTXF TXF tINITR1 FAULT RESET TIMER (130ms) OUT IN IN OUT PINS TXFS POWER-ON RESET IN1EN IN1 IN1S Figure 10. TXFOUT and TXDOUT Logic Diagram. RSELS 3-WIRE SET_LOS_3945 RSEL = PINS Figure 11. RSEL Logic Diagram Digital I/O Pins Five digital inputs and three digital output pins are provided for monitoring and control.
PAGE 27
DS1886 SFP and PON ONU Controller with Digital LDD Interface F8h and FDh). See Figure 12a and Figure 12b for nonlatched and latched operation. Figure 12c describes this TXFOUT behavior during power-on. Latching of the alarms is controlled by CNFGB and CNFGC Registers (A2h Table 02h, Register 8Ah and A2h Table 02h, Register 8Bh). The DS1886 monitors the IMODOVFL and IBIASOVFL bits in the MAX3710 DPCSTAT register. If any of these bits is set, the user can optionally cause TXFOUT to be set.
PAGE 28
DS1886 SFP and PON ONU Controller with Digital LDD Interface DS1886 Master Communication Interface device(s). It is a 3-pin interface consisting of SDAOUT, a bidirectional data line; clock signal SCLOUT; and CSEL1OUT chip-select output (active high). A second, independent chip select (CSEL2OUT) is provided for use with the MAX3945. The DS1886 controls the MAX3710 using a proprietary 3-wire interface.
PAGE 29
DS1886 SFP and PON ONU Controller with Digital LDD Interface 3-Wire Slave Register Map and DS1886 Corresponding Location When the MAX3945 registers are written, the MAX3710 are also written simultaneously (Table 6). 3-Wire Master Flowchart Figure 14 explains the working of the 3-wire master in the DS1886 in all three opreating modes. These modes are described in the DS1886 with MAX3710 Operating Modes section. Table 6.
PAGE 30
DS1886 SFP and PON ONU Controller with Digital LDD Interface READ REGISTERS BIAS REG, MOD REG, RXSTAT, DPCSTAT, TXSTAT1, TXSTAT2, MD0REGH, MD1REGH, SET_2XAPC BURST_MODE = 1 AND MD1REGH <17? Y TXD_STANDBY TOGGLE MONSEL N A TXD = 1 OR POR = 1 Y N RESET (SET TXD_FLAG IF TXD = 1 AND SET POR_FLAG IF POR = 1) N IDLE WAIT FOR TEMP_CONV TXD = 0? EN_3945 = 1? N N Y TEMP_CONV = 1? Y Y Y N VCC > VCC LO? WRITE_LUT REGISTERS TXCTRL5 IMODMAX IBIASMAX SET_IMOD SET_IBIAS BIASINC MODINC SET_2XAPC Y WRITE C
PAGE 31
DS1886 SFP and PON ONU Controller with Digital LDD Interface STEADY STATE NO TXF = 1? YES READ TXSTAT1 YES TXSTAT1 = FFh? NO WRITE_CONTROL RXCTRL1, RXCTRL2, SET_CML, SET_LOS, TXCTRL1, TXCTRL2, TXCTRL3, TXCTRL4 TXF = 1? NO YES FAULT WAIT STATE1, 2 TEMP CONVERSION COMPLETE? WRITE TXCTRL6 YES NO YES TXF = 1? WRITE_LUT REGISTERS TXCTRL5, IMODMAX, IBIASMAX, SET_IMOD, SET_IBIAS, MODINC, BIASINC, SET_2XAPC NO WRITE_LUT REGISTERS TXCTRL5, IMODMAX, IBIASMAX, SET_IMOD, SET_IBIAS, MODINC, BIASINC, SET_2
PAGE 32
DS1886 SFP and PON ONU Controller with Digital LDD Interface DS1886 with MAX3710 Operating Modes The user has the option of selecting among open loop, APC loop, and dual closed-loop operation modes. These can be programmed using the DPC_EN and APC_EN bits in the MAX3710 TXCTRL3 register (Address H0x08), programmed through A2h Table 02h, Register E6h. Table 7 indicates what the values in each LUT corresponds to in each of the modes.
PAGE 33
DS1886 SFP and PON ONU Controller with Digital LDD Interface BIAS, MODULATION, SET_2XAPC, TXCTRL5 LUTs The LUTs have nonlinear temperature indexing. After every temperature conversion, based on the internal temperature read, a TINDEX value is calculated, which then indexes the LUT. The LUTs can index with a resolution as low as 2NC. LUTs allow temperature indexing the BIAS and MODULATION values and their respective offsets.
PAGE 34
DS1886 EACH OFFSET REGISTER CAN BE INDEPENDENTLY SET BETWEEN 0 AND 1020. 1020 = 4 x FFh. THIS EXAMPLE ILLUSTRATES POSITIVE TEMPCO.
PAGE 35
DS1886 SFP and PON ONU Controller with Digital LDD Interface Table 11a. Power Leveling Details (when DS1863_MODE = 0, default) POWER LEVEL (dB) POW_LEV[1:0] (REGISTER 6Fh) MODULATION CHANGE KRMD[2:1] (MAX3710) TXCTRL3 POW_LEV_INIT 0 00 None 1X 1X -3 01 Right-shift SET_IMOD once 01 01 -6 1X Right-shift SET_IMOD twice 00 00 Table 11b.
PAGE 36
DS1886 SFP and PON ONU Controller with Digital LDD Interface a bit read (Figure 19). The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave.
PAGE 37
DS1886 SFP and PON ONU Controller with Digital LDD Interface the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page (one row of the memory map). Attempts to write to additional pages of memory without sending a STOP condition between pages results in the address counter wrapping around to the beginning of the present row.
PAGE 38
DS1886 SFP and PON ONU Controller with Digital LDD Interface Acknowledge Polling: Any time a EEPROM page is written, the device requires the EEPROM write time (tW) after the STOP condition to write the contents of the page to EEPROM. During the EEPROM write time, the device does not acknowledge its slave address because it is busy.
PAGE 39
DS1886 SFP and PON ONU Controller with Digital LDD Interface I2C ADDRESS A0h I2C ADDRESS A2h 00h 00h LOWER MEMORY NOTE: ALARM ENABLE ROW CAN BE CONFIGURED TO EXIST AT TABLE 01h OR TABLE 05h USING MASK BIT IN REGISTERS 89h, TABLE 02h.
PAGE 40
DS1886 SFP and PON ONU Controller with Digital LDD Interface Register Descriptions The register maps show each byte/word (2 bytes) in terms of its row in the memory. The first byte in the row is located in memory at the row address (hexadecimal) in the leftmost column. Each subsequent byte on the row is one/two memory locations beyond the previous byte/word’s address. A total of 8 bytes are present on each row. For more information about each of these bytes, see the corresponding register description.
PAGE 41
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h Register Map A2h TABLE 02h (PW2) ROW (HEX) ROW NAME 80 WORD 0 WORD 1 BYTE 0/8 BYTE 1/9 <0>CONFIG 0 <8>MODE <4>TINDEX 88 <8>CONFIG 1 DACFS CNFGA 90 <8>SCALE 0 XOVER COARSE 98 <8>SCALE 1 A0 <8>OFFSET 0 <8>OFFSET 1 A8 <9>PWD B0 B8 C0 <8>PWD ENABLE C8 <0>MAXROW D0–DF EMPTY E0 <8>3W CONFIG0 WORD 2 BYTE 3/B BYTE 4/C <4>MODULATION VALUE RESERVED CNFGB CNFGC RESERVED WORD 3 BYTE 5/D <4>APC BYTE 6/E
PAGE 42
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 04h Register Map A2h TABLE 04h (MODULATION OR TXCTRL5 LUT) ROW (HEX) 80–A7 WORD 0 ROW NAME BYTE 0/8 WORD 1 BYTE 1/9 BYTE 2/A WORD 2 BYTE 3/B <8>MODULATION/ BYTE 4/C WORD 3 BYTE 5/D BYTE 6/E BYTE 7/F SEE TABLE DESCRIPTION TXCTRL5 A8–EF EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY F0 <8>IMODMAX MOD MAX LUT MOD MAX LUT MOD MAX LUT MOD MAX LUT MOD MAX LUT MOD MAX LUT MOD MAX LUT MOD MAX LUT F8 <8>
PAGE 43
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 08h Register Map A2h TABLE 08h (INC LUT) ROW (HEX) ROW NAME WORD 0 BYTE 0/8 WORD 1 BYTE 1/9 BYTE 2/A WORD 2 BYTE 3/B BYTE 4/C WORD 3 BYTE 5/D BYTE 6/E BYTE 7/F 80–F7 EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY EMPTY F8–FF <8>INCROW INCBYTE INCBYTE INCBYTE INCBYTE INCBYTE INCBYTE INCBYTE INCBYTE A2h Table 09h Register Map A2h TABLE 09h (DAC OFFSET LUT) ROW (HEX) ROW NAME 80–F7 F8–FF EMPTY <8>DAC OFFSE
PAGE 44
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory Register Descriptions A2h Lower Memory, Register 00h–01h: TEMP ALARM HI A2h Lower Memory, Register 04h–05h: TEMP WARN HI FACTORY DEFAULT 7FFFh READ ACCESS All WRITE ACCESS PW2 MEMORY TYPE Nonvolatile (SEE) 00h, 04h S 26 25 24 23 22 21 20 01h, 05h 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 BIT 7 BIT 0 Temperature measurement updates above this two’s complement threshold set its corresponding alarm or warning bit.
PAGE 45
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 08h–09h: VCC ALARM HI A2h Lower Memory, Register 0Ch–0Dh: VCC WARN HI A2h Lower Memory, Register 10h–11h: TXB ALARM HI A2h Lower Memory, Register 14h–15h: TXB WARN HI A2h Lower Memory, Register 18h–19h: TXP ALARM HI A2h Lower Memory, Register 1Ch–1Dh: TXP WARN HI A2h Lower Memory, Register 20h–21h: RSSI ALARM HI A2h Lower Memory, Register 24h–25h: RSSI WARN HI FACTORY DEFAULT FFFFh READ ACCESS All WRITE ACCESS PW2
PAGE 46
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 0Ah–0Bh: VCC ALARM LO A2h Lower Memory, Register 0Eh–0Fh: VCC WARN LO A2h Lower Memory, Register 12h–13h: TXB ALARM LO A2h Lower Memory, Register 16h–17h: TXB WARN LO A2h Lower Memory, Register 1Ah–1Bh: TXP ALARM LO A2h Lower Memory, Register 1Eh–1Fh: TXP WARN LO A2h Lower Memory, Register 22h–23h: RSSI ALARM LO A2h Lower Memory, Register 26h–27h: RSSI WARN LO FACTORY DEFAULT 0000h READ ACCESS All WRITE ACCESS PW2
PAGE 47
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 28h–37h: EMPTY FACTORY DEFAULT READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE These registers are empty. A2h Lower Memory, Register 38h–5Fh: EE FACTORY DEFAULT 00h READ ACCESS All WRITE ACCESS PW2 MEMORY TYPE Nonvolatile (EE) 38h–5Fh EE EE EE EE EE EE EE BIT 7 EE BIT 0 PW2 level access-controlled EEPROM.
PAGE 48
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 62h–63h: VCC VALUE A2h Lower Memory, Register 64h–65h: TXB VALUE A2h Lower Memory, Register 66h–67h: TXP VALUE A2h Lower Memory, Register 68h–69h: RSSI VALUE POWER-ON VALUE 0000h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile 62h, 64h, 66h, 68h 215 214 213 212 211 210 29 28 63h, 65h, 67h, 69h 27 26 25 24 23 22 21 20 BIT 7 BIT 0 Left-justified unsigned voltage measurement.
PAGE 49
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 6Eh: STATUS POWER-ON VALUE X0XX 0XXXb READ ACCESS All WRITE ACCESS See below description MEMORY TYPE Volatile Write Access 6Eh N/A All N/A All All N/A N/A N/A TXDS TXDC TXFIS RSELS RESERVED TXFOUTS RXL RDYB BIT 7 Maxim Integrated BIT 0 BIT 7 TXDS: TXD status bit. Reflects the logic state of the TXD pin (read-only). 0 = TXD pin is logic-low. 1 = TXD pin is logic-high.
PAGE 50
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 6Fh: UPDATE 6Fh POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS All and DS1886 Hardware MEMORY TYPE Volatile TEMP RDY VCC RDY TXB RDY TXP RDY RSSI RDY RSSIR POW_LEV1 BIT 7 BITS 7:3 BIT 2 BITS 1:0 Maxim Integrated POW_LEV0 BIT 0 Update of completed conversions. At power-on, these bits are cleared and are set as each conversion is completed.
PAGE 51
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 70h: ALARM3 70h POWER-ON VALUE 10h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile TEMP HI TEMP LO VCC HI VCC LO TXB HI TXB LO BIT 7 TXP HI TXP LO BIT 0 BIT 7 TEMP HI: High alarm status for temperature measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting.
PAGE 52
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 71h: ALARM2 71h POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile RSSI HI RSSI LO RESERVED RESERVED RESERVED IN1S RESERVED BIT 7 BIT 0 BIT 7 RSSI HI: High alarm status for RSSI measurement. A TXD event does not clear this alarm. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting.
PAGE 53
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 74h: WARN3 74h POWER-ON VALUE 10h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile TEMP HI TEMP LO VCC HI VCC LO TXB HI TXB LO BIT 7 TXP HI TXP LO BIT 0 BIT 7 TEMP HI: High warning status for temperature measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting.
PAGE 54
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 75h: WARN2 75h POWER-ON VALUE 00h READ ACCESS All WRITE ACCESS N/A MEMORY TYPE Volatile RSSI HI RSSI LO RESERVED RESERVED RESERVED RESERVED BIT 7 RESERVED BIT 0 BIT 7 RSSI HI: High warning status for RSSI measurement. 0 = (Default) Last measurement was equal to or below threshold setting. 1 = Last measurement was above threshold setting. BIT 6 RSSI LO: Low warning status for RSSI measurement.
PAGE 55
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Lower Memory, Register 7Bh–7Eh: PASSWORD ENTRY (PWE) POWER-ON VALUE FFFF FFFFh READ ACCESS N/A WRITE ACCESS ALL MEMORY TYPE Volatile 7Bh 231 230 229 228 227 226 225 224 7Ch 223 222 221 220 219 218 217 216 7Dh 215 214 213 212 211 210 29 28 7Eh 27 26 25 24 23 22 21 20 BIT 7 BIT 0 There are two passwords for the DS1886. Each password is 4 bytes long.
PAGE 56
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 01h Register Descriptions A2h Table 05h can be configured to contain the alarm and warning enable bytes from A2h Table 01h, Registers F8h– FFh with the MASK bit enabled (A2h Table 02h, Register 89h). In this case the corresponding bytes in A2h Table 01h are empty.
PAGE 57
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 01h, Register F8h: ALARM EN3 POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) F8h TEMP HI TEMP LO VCC HI VCC LO BIT 7 TXB HI TXB LO TXP HI TXP LO BIT 0 Layout is identical to ALARM3 in Lower Memory, Register 70h. Enables alarms to create TXFINT (Lower Memory, Register 71h) logic.
PAGE 58
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 01h, Register F9h: ALARM EN2 F9h POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) RSSI HI RSSI LO RESERVED RESERVED RESERVED IN1EN RESERVED BIT 7 RESERVED BIT 0 Layout is identical to ALARM2 in Lower Memory, Register 71h. Enables alarms to create TXFINT (Lower Memory, Register 71h) logic.
PAGE 59
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 01h, Register FCh: WARN EN3 POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) FCh TEMP HI TEMP LO VCC HI VCC LO TXB HI BIT 7 TXB LO TXP HI TXP LO BIT 0 Layout is identical to WARN3 in Lower Memory, Register 74h. Enables warnings to create TXFINT (Lower Memory, Register 71h) logic.
PAGE 60
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 01h, Register FDh: WARN EN2 FDh POWER-ON VALUE 00h READ ACCESS PW2 or (PW1 and RWTBL1C) or (PW1 and RTBL1C) WRITE ACCESS PW2 or (PW1 and RWTBL1C) MEMORY TYPE Nonvolatile (SEE) RSSI HI RSSI LO RESERVED RESERVED BIT 7 RESERVED RESERVED RESERVED RESERVED BIT 0 Layout is identical to WARN2 in Lower Memory, Register 75h. Enables warnings to create TXFINT (Lower Memory, Register 71h) logic.
PAGE 61
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h Register Descriptions A2h Table 02h, Register 80h: MODE POWER-ON VALUE READ ACCESS WRITE ACCESS MEMORY TYPE 80h SEEB 7Fh PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) PW2 or (PW1 and RWTBL246) Volatile INCROW LUT EN TXCTRL5 LUT EN BIAS LUT EN AEN MOD LUT EN BIT 7 APC LUT EN DAC LUT EN BIT 0 BIT 7 SEEB: 0 = (Default) Enables EEPROM writes to SEE bytes.
PAGE 62
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register 81h: Temperature Index (TINDEX) 81h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS (PW2 and AEN = 0) or (PW1 and RWTBL246 and AEN = 0) MEMORY TYPE Volatile 27 26 25 24 23 22 21 BIT 7 20 BIT 0 Holds the calculated index based on the temperature measurement. This index is used for the address during lookup of Tables 04h, 06h, and 08h.
PAGE 63
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register 85h: APC VALUE 85h FACTORY DEFAULT 0000h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS (PW2 and APC LUT EN = 0) or (PW1 and RWTBL246 and APC LUT EN = 0) MEMORY TYPE Volatile 27 26 25 24 23 22 21 BIT 7 20 BIT 0 The digital value used for APC and recalled from A2h Table 06h in the APC and dual-closed-loop mode at the adjusted memory address found in TINDEX.
PAGE 64
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register 89h: CNFGA FACTORY DEFAULT 82h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 89h LOSC RESERVED INV LOS RESERVED MASK RESERVED BIT 7 Maxim Integrated BURST_MODE INVTXFI BIT 0 BIT 7 LOSC: Enables LOSOUT due to input pin LOS. 0 = LOSOUT is affected by the LOS input. 1 = LOSOUT is not affected by changed in the LOS input.
PAGE 65
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register 8Ah: CNFGB 8Ah FACTORY DEFAULT 40h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RESERVED RESERVED BIASMOD_RSTEN RESERVED RESERVED ALATCH RESERVED BIT 7 BIT 0 BIT 7 RESERVED BIT 6 BIASMOD_RSTEN: 0 = BIASREG and MODREG when set to 0 do not cause a restart.
PAGE 66
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register 8Bh: CNFGC 8Bh FACTORY DEFAULT 10h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) XOVEREN RESERVED TXDM3 BIASMODOVFL_FLT TXDFLT TXDIO RSSI_FC RSSI_FF BIT 7 BIT 0 BIT 7 XOVEREN: Enables RSSI conversion to use the XOVER (A2h Table 02h, Register 90h–91h) value during RSSI conversions.
PAGE 67
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register 8Dh: CNFGD 8Dh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) INV_DAC RESERVED RESERVED RESERVED DS1863_MODE POW_LEV_DS1863 BIT 7 BIT 7 BITS 6:4 BIT 3 BIT 0 INV_DAC: 0 = DAC output is inverted. 1 = DAC output is not inverted. RESERVED DS1863_MODE: 0 = Normal operation.
PAGE 68
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register 8Fh: RIGHT-SHIFT0 (RSHIFT0) 8Fh FACTORY DEFAULT 30h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RESERVED RSSIF2 RSSIF1 RSSIF0 RESERVED RSSIC2 RSSIC1 BIT 7 RSSIC0 BIT 0 Allows for right-shifting the final answer of RSSI fine and coarse voltage measurements.
PAGE 69
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register 92h–93h: VCC SCALE A2h Table 02h, Register 94h–95h: TXB SCALE A2h Table 02h, Register 96h–97h: TXP SCALE A2h Table 02h, Register 98h–99h: RSSI FINE SCALE A2h Table 02h, Register 9Ah–9Bh: RESERVED A2h Table 02h, Register 9Ch–9Dh: RSSI COARSE SCALE FACTORY CALIBRATED READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 92h, 94h, 96h, 98h, 9Ch 215
PAGE 70
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register A0h–A1h: XOVER FINE FACTORY DEFAULT FFFFh READ ACCESS PW2 or (PW1 and RWTBL2) or (PW1 and RTBL2) WRITE ACCESS PW2 or (PW1 and RWTBL2) MEMORY TYPE Nonvolatile (SEE) A0h 215 214 213 212 211 210 29 28 A1h 27 26 25 24 23 22 21 0 BIT 7 BIT 0 Defines the crossover value for RSSI measurements of nonlinear inputs when XOVEREN is set to 1 (A2h Table 02h, Register 8Bh).
PAGE 71
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register AEh–AFh: INTERNAL TEMP OFFSET FACTORY CALIBRATED READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) AEh S 28 27 26 25 24 23 22 AFh 21 20 2-1 2-2 2-3 2-4 2-5 2-6 BIT 7 BIT 0 Allows for offset control of temp measurement if desired. The final result must be XORed with BB40h before writing to this register.
PAGE 72
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register B4h–B7h: PW2 FACTORY DEFAULT FFFF FFFFh READ ACCESS N/A WRITE ACCESS PW2 MEMORY TYPE Nonvolatile (SEE) B4h 231 230 229 228 227 226 225 224 B5h 223 222 221 220 219 218 217 216 B6h 215 214 213 212 211 210 29 28 B7h 27 26 25 24 23 22 21 20 BIT 7 BIT 0 The PWE value is compared against the value written to this location to enable PW2 access.
PAGE 73
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register C0h: PW_ENA C0h FACTORY DEFAULT 10h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RWTBL89 RWTBL1C RWTBL2 RWTBL1A RWTBL1B WA2 LOWER WAUXA BIT 7 Maxim Integrated WAUXB BIT 0 BIT 7 RWTBL89: Tables 08h–09h. 0 = (Default) read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2.
PAGE 74
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register C1h: PW_ENB C1h FACTORY DEFAULT 03h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) RWTBL46 RTBL1C RTBL2 RTBL1A RTBL1B BIT 7 Maxim Integrated WPW1 WAUXAU WAUXBU BIT 0 BIT 7 RWTBL46: Read and write Tables 04h and 06h. 0 = (Default) Read and write access for PW2 only. 1 = Read and write access for both PW1 and PW2.
PAGE 75
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register C2h–C6h: RESERVED FACTORY DEFAULT 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) These registers are reserved.
PAGE 76
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register CAh: INCBYTE CAh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS (PW2 and BIAS LUT EN = 0) or (PW1 and RWTBL246 and BIAS LUT EN = 0) MEMORY TYPE Volatile 23 22 21 20 23 22 21 BIT 7 20 BIT 0 7:4: Value written to MAX3710 BIASINC[3:0] from LUT. This must be set to 0 in open-loop mode. 3:0: Value written to MAX3710 MODINC[3:0] from LUT.
PAGE 77
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register CDh: IBIASMAX CDh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Volatile 29 28 27 26 25 24 23 BIT 7 22 BIT 0 Value written to MAX3710 IBIASMAX from the BIAS MAX LUT.
PAGE 78
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register D0h–DFh: EMPTY FACTORY DEFAULT 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE None These registers do not exist. A2h Table 02h, Register E0h: RXCTRL1 E0h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register.
PAGE 79
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register E2h: SETCML E2h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register.
PAGE 80
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register E5h: TXCTRL2 FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 E5h 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register.
PAGE 81
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register E8h: TXCTRL5 APC OL E8h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register.
PAGE 82
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register EBh: RESERVED FACTORY DEFAULT 00h READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) This register is reserved.
PAGE 83
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register EEh: SETLOSTIMER_3945 FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 EEh 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register.
PAGE 84
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register F0h: 3WCTRL F0h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Volatile RESERVED RESERVED RESERVED RESERVED RESERVED 3WMAN_3945 BIT 7 BITS 7:3 3WRW 3WDIS BIT 0 RESERVED BIT 2 3WMAN_3945: When this bit is set when 3WRW is set, only the MAX3945 is written using CSELOUT2.
PAGE 85
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register F2h: WRITE F2h FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (SEE) 27 26 25 24 23 22 21 BIT 7 20 BIT 0 This byte is used during manual 3-wire communication. When a manual write is initiated, this register contains the address for the operation.
PAGE 86
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 02h, Register F5h: TXSTAT1 FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS N/A MEMORY TYPE Nonvolatile (SEE) 27 F5h 26 25 24 23 22 21 BIT 7 20 BIT 0 A 3-wire slave register. This value is read from a Maxim laser driver with the 3-wire interface every tRR (see the Analog Voltage Monitoring Characteristics table).
PAGE 87
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 04h Register Descriptions A2h Table 04h, Register 80h–A7h: MODULATION or TXCTRL5 LUT FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (EE) Open Loop and APC Loop (Modulation), Dual Closed Loop (TXCTRL5) 27 80h–A7h 26 25 24 23 22 21 20 The digital value for the modulation DAC output or TXCTRL5 register in MAX3710.
PAGE 88
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 04h, Register F8h–FFh: MOD OFFSET or SET_IMOD LUT FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWTBL246) or (PW1 and RBL246) WRITE ACCESS PW2 or (PW1 and RWTBL246) MEMORY TYPE Nonvolatile (EE) Open Loop, APC Loop, and Dual Closed Loop (SET_IMOD) F8h–FFh 29 28 27 26 25 24 23 BIT 7 22 BIT 0 A2h Table 06h Register Descriptions A2h Table 06h, Register 80h–A7h: BIAS or SET_IBIAS FACTORY DEFAULT 00h READ ACCESS PW2 or (
PAGE 89
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 06h, Register A8h–EFh: EMPTY FACTORY DEFAULT READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE These registers are empty.
PAGE 90
DS1886 SFP and PON ONU Controller with Digital LDD Interface A2h Table 08h Register Descriptions A2h Table 08h, Register 80h–F7h: EMPTY FACTORY DEFAULT READ ACCESS N/A WRITE ACCESS N/A MEMORY TYPE These registers are empty.
PAGE 91
DS1886 SFP and PON ONU Controller with Digital LDD Interface Auxiliary Memory A0h Register Description Auxiliary Memory A0h, Register 00h–FFh: EEPROM 00h–FFh FACTORY DEFAULT 00h READ ACCESS PW2 or (PW1 and RWAUXA) or (PW1 and RWAUXAU) WRITE ACCESS PW2 or (PW1 and RWAUXA) MEMORY TYPE Nonvolatile (EE) 27 26 25 24 23 22 21 20 BIT 7 BIT 0 Accessible with the slave address A0h.
PAGE 92
DS1886 SFP and PON ONU Controller with Digital LDD Interface Revision History REVISION NUMBER REVISION DATE 0 3/12 1 8/12 DESCRIPTION Initial release PAGES CHANGED — Made numerous LUT addressing changes for TXINLOS 30, 32, 33, 39, 83, 87, 88, 89 Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied.