DS1921H/DS1921Z High-Resolution Thermochron iButton Devices SPECIAL FEATURES Digital thermometer measures temperature in 1/8°C increments with ±1°C accuracy Built-in real-time clock (RTC) and timer has accuracy of ±2 minutes per month from 0°C to +45°C Water resistant or waterproof if placed inside DS9107 iButton® capsule (Exceeds Water Resistant 3 ATM requirements) Automatically wakes up and measures temperature at user-programmable intervals from 1 to 255 minutes Logs consecutive te
DS1921H/Z iButton DEVICE DESCRIPTION The DS1921H/Z Thermochron® iButton devices are rugged, self-sufficient systems that measure temperature and record the result in a protected memory section. The recording is done at a user-defined rate, both as a direct storage of temperature values as well as in the form of a histogram. Up to 2048 temperature values taken at equidistant intervals ranging from 1 to 255 minutes can be stored. The histogram provides 64 data bins with a resolution of 0.5°C.
DS1921H/Z DS1921H/Z BLOCK DIAGRAM Figure 1 1-Wire Port ROM Function Control IO 64-Bit Lasered ROM Memory Function Control Parasite Powered Circuitry 256-Bit Scratchpad General-Purpose SRAM Internal Timekeeping & Control Reg. & Counters 32.768kHz Oscillator Register Page Alarm Time Stamp and Duration Logging Memory Temperature Sensor Control Logic Histogram Memory Datalog Memory 3V Lithium PARASITE POWER The block diagram (Figure 1) shows the parasite-powered circuitry.
DS1921H/Z HIERARCHICAL STRUCTURE FOR 1-Wire PROTOCOL Figure 2 1-Wire net Bus Master Other Devices DS1921 Command Level: Available Commands: 1-Wire ROM Function Commands DS1921-Specific Memory/Control Function Commands Cmd. Data Field Codes: Affected: Read ROM Match ROM Search ROM Skip ROM Overdrive Skip Overdrive Match Conditional Search ROM 33h 55h F0h CCh 3Ch 69h ECh 64-bit Reg. # 64-bit Reg. # 64-bit Reg. # N/A OD-Flag 64-bit Reg. #, OD-Flag 64-bit Reg. #, Cond.
1-Wire CRC GENERATOR Figure 4 DS1921H/Z 8 5 4 Polynomial = X + X + X + 1 st nd 1 STAGE X 0 rd 2 STAGE X 1 th 3 STAGE X 2 th 4 STAGE X 3 th X 4 th 6 STAGE 5 STAGE X 5 th 7 STAGE X 6 8 STAGE X 7 X 8 INPUT DATA MEMORY The memory map of the DS1921H/Z is shown in Figure 5. The 4096-bit general-purpose SRAM make up pages 0 through 15. The timekeeping, control, and counter registers fill page 16, called Register Page (see Figure 6).
DS1921H/Z DS1921H/Z REGISTER PAGE MAP Figure 6 ADDR 0200h 0201h 0202h b7 0 0 0 0203h 0204h 0205h 0206h 0207h 0208h 0209h 0 0 CENT 020Ah 020Bh 020Ch 020Dh MD 020Eh 020Fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh EOSC MS MM MH TCB b6 b5 b4 10 Seconds 10 Minutes 12/24 10h. 20h. b3 b2 b1 Single Seconds Single Minutes b0 Single Hours AM/PM 0 0 0 0 Day of Week 0 10 Date Single Date 0 0 10m.
DS1921H/Z RTC and RTC Alarm Register Bitmap ADDR 0200h 0201h 0202h b7 0 0 0 b5 b4 10 Seconds 10 Minutes 12/24 10h. 20h. b3 0203h 0204h 0205h 0206h 0207h 0208h 0209h 0 0 CENT 0 020Ah MD 0 0 0 0 10 Date 0 0 10m. 10 Years 10 Seconds Alarm 10 Minutes Alarm 12/24 10ha. 10h. A/P alm.
DS1921H/Z RTC Alarm Control ALARM REGISTER MASK BITS (Bit 7 of 207h to 20Ah) MS MM MH MD 1 1 1 1 Alarm once per second. 0 1 1 1 Alarm when seconds match (once per minute). 0 0 1 1 Alarm when minutes and seconds match (once every hour). 0 0 0 1 Alarm when hours, minutes and seconds match (once every day). 0 0 0 0 Alarm when day, hours, minutes, and seconds match (once every week).
DS1921H/Z SAMPLE RATE The content of the Sample Rate Register (address 020Dh) determines how many minutes the temperature conversions are apart from each other during a mission. The sample rate may be any value from 1 to 255, coded as an unsigned 8-bit binary number. If the memory has been cleared (Status Register bit MEMCLR = 1) and a mission is enabled (Status Register bit EM = 0), writing a non-zero value to the Sample Rate Register will start a mission.
BIT DESCRIPTION TLS: Temperature Low Alarm Search BIT(S) b2 THS: Temperature High Alarm Search b1 TAS: Timer Alarm Search b0 DS1921H/Z DEFINITION If this bit is 1, the device will respond to a Conditional Search command if during a mission the temperature has reached or is lower than the Low Temperature Threshold stored at address 020Bh.
BIT DESCRIPTION MIP: Mission in Progress BIT(S) b5 SIP: Sample in Progress b4 TLF: Temperature Low Flag b2 THF: Temperature High Flag b1 TAF: Timer Alarm Flag b0 DS1921H/Z DEFINITION If this bit reads 1 the DS1921H/Z has been set up for a mission and this mission is still in progress. A mission is started if the EM bit of the Control Register (address 20Eh) is 0 and a non-zero value is written to the Sample Rate Register, address 20Dh.
DS1921H/Z Mission Samples Counter Register Map ADDR 021Ah 021Bh 021Ch b7 b6 b5 b4 b3 Low Byte Center Byte High Byte b2 b1 b0 DEVICE SAMPLES COUNTER The Device Samples Counter indicates how many temperature measurements have taken place since the device was assembled at the factory. The value is stored as an unsigned 24-bit integer number. The maximum number that can be represented in this format is 16777215, which is higher than the expected lifetime of the DS1921H/Z devices.
HISTOGRAM BIN AND TEMPERATURE CROSS-REFERENCE Figure 7 DS1921H/Z TEMPERATURE READING DS1921H TEMP. EQUIV. IN °C DS1921Z TEMP. EQUIV. IN °C HISTOGRAM BIN NUMBER HISTOGRAM BIN ADDRESS 00h 14.500 -5.500 0 800h to 801h 01h 14.625 -5.375 0 800h to 801h 02h 14.750 -5.250 0 800h to 801h 03h 14.875 -5.125 0 800h to 801h 04h 15.000 -5.000 1 802h to 803h 05h 15.125 -4.875 1 802h to 803h 06h 15.250 -4.750 1 802h to 803h 07h 15.375 -4.625 1 802h to 803h 08h 15.500 -4.
DS1921H/Z and periods (12 periods for too hot and 12 for too cold). The date and time of each of these periods can be determined from the Mission Time Stamp and the time distance between each temperature reading.
DS1921H/Z The state of the Search Condition bits in the Control Register does not affect the mission. If multiple devices are connected to form a 1-Wire net, the setting of the search condition will enable devices to participate in the conditional search if certain events such as timer or temperature alarm have occurred. Details on the search conditions are found in the section ROM Function Commands later in this document and in the Control Register description.
DS1921H/Z byte offset. If the target address for a Write command is 13Ch, for example, then the scratchpad will store incoming data beginning at the byte offset 1Ch and will be full after only 4 bytes. The corresponding ending offset in this example is 1Fh. For best economy of speed and efficiency, the target address for writing should point to the beginning of a new page, (i.e., the byte offset will be 0).
DS1921H/Z byte sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC generator and then shifting in the command code (0Fh) of the Write Scratchpad command, the Target Addresses TA1 and TA2 as supplied by the master and all the data bytes. The master may end the Write Scratchpad command at any time. However, if the ending offset is 11111b, the master may send 16 read time slots and will receive an inverted CRC16 generated by the DS1921H/Z.
DS1921H/Z MEMORY/CONTROL FUNCTION FLOW CHART Figure 10-1 From ROM Functions Flow Chart (Figure 12) Master TX Memory or Control Fkt.
DS1921H/Z MEMORY/CONTROL FUNCTION FLOW CHART Figure 10-2 From Figure 10 st 1 Part 55H Copy Scratchpad To Figure 10 rd 3 Part F0H Read Memory N N Y Y DS1921 sets EMCLR = 0 DS1921 sets EMCLR = 0 Master TX TA1 (T7:T0), TA2 (T15:T8) Master TX TA1 (T7:T0), TA2 (T15:T8) Master TX E/S Byte DS1921 sets Memory Address = (T15:T0) Authorization Code Match? Master RX Data Byte from Memory Address N DS1921 Increments Address Counter Y AA = 1 DS1921 Copies Scratchpad Data to Memory N N Master RX "1"s
DS1921H/Z MEMORY/CONTROL FUNCTION FLOW CHART Figure 10-3 From Figure 10 2nd Part A5H Read Mem.
DS1921H/Z MEMORY/CONTROL FUNCTION FLOW CHART Figure 10-4 From Figure 10 rd 3 Part 3CH Clear Memory 44H Convert Temp. N Y N Y DS1921 sets EMCLR = 0 N EMCLR = 1? Y DS1921 clears Mission Time Stamp, Mission Samples Counter, Mission Start Delay, Sample Rate Register Y Mission in Progress? N DS1921 clears Alarm Time Stamps and Durations DS1921 clears Histogram Memory DS1921 Starts Temperature Conversion Process DS1921 sets MEMCLR = 1 Master TX Reset? DS1921 sets TCB\ = 0 DS1921 Performs a Temp.
DS1921H/Z Read Memory with CRC [A5h] The Read Memory with CRC command is used to read memory data that cannot be packetized, such as the register page and the data recorded by the device during a mission. The command works essentially the same way as the simple Read Memory, except for the 16-bit CRC that the DS1921H/Z generates and transmits following the last data byte of a memory page.
DS1921H/Z Mission Start and Logging Process The DS1921H/Z does not use a special command to start a mission. Instead, a mission is started by writing a non-zero value to the Sample Rate Register using the Copy Scratchpad command. As shown in Figure 11, a new mission can only be started if the previous mission has been stopped (MIP = 0), the memory is cleared (MEMCLR = 1) and the mission is enabled (EM = 0).
DS1921H/Z Stop Mission The DS1921H/Z does not have a special command to stop a mission. A mission can be stopped at any time by writing to any address in the range of 0200h to 0213h or by writing the MIP bit of the Status Register at address 0214h to 0. Either approach involves the use of the Copy Scratchpad command. There is no need for the Mission Start Delay to expire before a mission can be stopped (see Figure 11).
DS1921H/Z HARDWARE CONFIGURATION Figure 12 BUS MASTER VPUP DS1921 1-Wire PORT RPUP RX DATA TX RX = RECEIVE Open Drain Port Pin RX TX 5µA Typ. TX = TRANSMIT 100Ω MOSFET TRANSACTION SEQUENCE The protocol for accessing the DS1921H/Z via the 1-Wire port is as follows: Initialization ROM Function Command Memory/Control Function Command Transaction/Data INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence.
DS1921H/Z Search ROM [F0h] When a system is initially brought up, the bus master might not know the number of devices on the 1Wire bus or their registration numbers. By taking advantage of the wired-AND property of the bus, the master can use a process of elimination to identify the registration numbers of all slave devices. For each bit of the registration number, starting with the least significant bit, the bus master issues a triplet of time slots.
DS1921H/Z ROM FUNCTIONS FLOW CHART Figure 13-1 Master TX Reset Pulse From Memory Functions Flow Chart (Figure 10) N Short Reset Pulse? OD = 0 Y 33H Read ROM? N Y DS1921 TX Presence Pulse 2) Master TX ROM Function Command 1) 55H Match ROM? From Figure 13 nd 2 Part F0H Search ROM? N Y To Figure 13 nd 2 Part ECH Cond. Search ROM? N Y N Y N Cond.
DS1921H/Z ROM FUNCTIONS FLOW CHART Figure 13-2 To Figure 13 st 1 Part From Figure 13 st 1 Part N CCH Skip ROM? 3CH Overdrive Skip ROM? Y N 69H Overdrive Match? Y OD = 1 N Y OD = 1 Master TX Bit 0 Bit 0 Match? 3) N Y Master TX Bit 1 Y Master TX Reset Pulse? Bit 1 Match? N Y Master TX Bit 63 Bit 63 Match? From Figure 13 st 1 Part To Figure 13 st 1 Part Y 3) Always to be transmitted at Overdrive speed.
DS1921H/Z Overdrive Skip ROM [3Ch] On a single-drop bus this command can save time by allowing the bus master to access the memory/control functions without providing the 64-bit ROM code. Unlike the normal Skip ROM command, the Overdrive Skip ROM sets the DS1921H/Z in the Overdrive mode (OD = 1). All communication following this command has to occur at Overdrive speed until a reset pulse of minimum 480µs duration resets all devices on the bus to standard speed (OD = 0).
DS1921H/Z INITIALIZATION PROCEDURE (RESET AND PRESENCE PULSES) Figure 14 After the bus master has released the line it goes into receive mode (RX). Now, the 1-Wire bus is pulled to VPUP via the pull-up resistor or, in case of a DS2480B driver, by active circuitry. When the threshold VTH is crossed, the DS1921H/Z waits for tPDH and then transmits a presence pulse by pulling the line low for tPDL. To detect a presence pulse, the master must test the logical state of the 1-Wire line at tMSP.
DS1921H/Z READ/WRITE TIMING DIAGRAM Figure 15 Write-One Time Slot VPUP tW1L VIHMASTER VTH VTL VILMAX 0V tF ε tSLOT RESISTOR MASTER Write-Zero Time Slot tW0L VPUP VIHMASTER VTH VTL VILMAX 0V tF tSLOT RESISTOR ε tREC MASTER Read-Data Time Slot Slave to Master A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below VTL until the read low time tRL is expired.
DS1921H/Z CRC GENERATION With the DS1921H/Z there are two different types of Cyclic Redundancy Checks (CRCs). One CRC is an 8-bit type and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS1921H/Z to determine if the ROM data has been received error-free. The equivalent polynomial function of this CRC is X8 + X5 + X4 + 1.
CRC-16 HARDWARE DESCRIPTION AND POLYNOMIAL Figure 16 16 Polynomial = X st nd 1 STAGE 0 th 8 2 X th 10 STAGE 9 X th 10 X 11 X 12 X 13 X 8 STAGE 7 X th 14 STAGE X th 7 STAGE 6 X th th th 6 STAGE 5 X 13 STAGE th 5 STAGE 4 X 12 STAGE 11 STAGE 2 +X +1 th 4 STAGE 3 X th 9 STAGE th 3 STAGE 1 X X rd 2 STAGE 15 +X th 15 STAGE 14 X DS1921H/Z 16 STAGE 15 X 16 X INPUT DATA CRC OUTPUT Command-Specific 1-Wire Communication Protocol — Legend Symbol RST PD Se
Command-Specific 1-Wire Communication Protocol — Color Codes Master to slave DS1921H/Z Slave to master Write Scratchpad, reaching the end of the Scratchpad RST PD Select WS TA CRC16\ FF loop Write Scratchpad, not reaching the end of the Scratchpad RST PD Select WS TA RS TA-E/S RST PD Read Scratchpad RST PD Select CRC16\ FF loop Copy Scratchpad (success) RST PD Select CPS TA-E/S Busy AA loop Copy Scratchpad (invalid TA-E/S) RST PD Select
DS1921H/Z Read Memory with CRC (invalid address) RST PD Select RMC TA <00 to EOP> CRC16\ The "32 bytes" are all 00h. <32 bytes> CRC16\ Loop Clear Memory RST PD Select CM FF loop To verify success, read the Status Register at address 0214h. If MEMCLR is 1, the command was executed successfully. Convert Temperature RST PD Select CT FF loop To read the result and to verify success, read the addresses 0211h (result) and the Device Samples Counter at address 021Dh to 021Fh.
DS1921H/Z MISSION EXAMPLE: PREPARE AND START A NEW MISSION Assumption: The previous mission has come to an end. To end an ongoing mission write the MIP bit in the Status Register to 0.
DS1921H/Z STEP 2 Set the EMCLR bit to 1, enable the RTC and then execute the Clear Memory command. The RTC oscillator must be stable before the Clear Memory command is issued. Wait 500 µs after issuing the Clear Memory command before proceeding to Step 3.
DS1921H/Z STEP 3 In this example, the rollover is disabled and the search condition is set for a high temperature only. The mission is to start with a delay of 90 (005Ah) minutes and the alarm flags TLF, THF, and TAF are cleared.
DS1921H/Z STEP 4 In this example, the temperature alarms are set to 0°C for the low temperature threshold and 10°C for the high temperature threshold, assuming it is a DS1921Z device. The sample rate is once every 10 minutes, allowing the mission to last up to 14 days.
PHYSICAL SPECIFICATION Size Weight ABSOLUTE MAXIMUM RATINGS* IO Voltage to GND IO Sink Current Temperature Range DS1921H, DS1921Z Storage Temperature Range * DS1921H/Z See mechanical drawing 3.3g -0.5V, +6V 20mA -40°C to +85°C** -40°C to +50°C** This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
DS1921H/Z PARAMETER SYMBOL CONDITIONS Presence Detect High tPDH Standard Speed Time Overdrive Speed Presence Detect Low tPDL Standard Speed Time Overdrive Speed Presence Detect tMSP Standard Speed Sample Time Overdrive Speed IO pin, 1-Wire Write Write-0 Low Time tW0L Standard Speed Overdrive Speed Write-1 Low Time tW1L Standard Speed Overdrive Speed IO pin, 1-Wire Read Read Low Time tRL Standard Speed Overdrive Speed Read Sample Time tMSR Standard Speed Overdrive Speed Real-Time Clock Frequency Deviation -
DS1921H/Z 11) ε in Figure 15 represents the time required for the pull-up circuitry to pull the voltage on IO up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF ε and tW0LMAX + tF - ε, respectively. 12) δ in Figure 15 represents the time required for the pull-up circuitry to pull the voltage on IO up from VIL to the input high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
DS1921H/Z RTC Frequency Deviation vs Temperature Lower Limit Upper Limit Frequency Deviation (PPM) 50 25 0 -25 -50 -75 -100 -125 -150 -175 -200 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature (°C) Minimum Product Lifetime vs Temperature at Different Sample Rates Every Minute Every 3 Min. No Samples Osc. Off Every 10 Min. Min. Product Lifetime (years) 11.00 10.00 9.00 8.00 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.
Minimum Product Lifetime vs Sample Rate at Different Temperatures -5°C 15 °C 26°C 37°C DS1921H/Z 46°C Minimum Product Lifetime (years) 12.00 11.00 10.00 9.00 8.00 7.00 6.00 5.00 4.00 3.00 2.00 1.00 1 10 100 1000 Minutes between Samples PACKAGE INFORMATION For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only.
DS1921H/Z REVISION HISTORY REVISION DESCRIPTION DATE 020402 Initial release 091202 Various updates to the Electrical Characteristics table, note 16 added. Branding change from Dallas to iButton, style updates, more detailed register page map, various text updates regarding mission start and 1-Wire communication, added sections Mission Start and Logging 100703 Process plus graphic, Memory Access Conflicts and Command-Specific 1-Wire Communication Protocol, note 17 added to Electrical Characteristics table.
