Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsIntegrated Circuits (ICs)1 kBit 256 x 4

SPECIAL FEATURES

 1024 bits Electrically Programmable Read-

Only Memory (EPROM) communicates with

the economy of one signal plus ground

 EPROM partitioned into four 256-bit pages for

randomly accessing packetized data

 Each memory page can be permanently write-

protected to prevent tampering

 Device is an “add only” memory where

additional data can be programmed into

EPROM without disturbing existing data

 Architecture allows software to patch data by

superseding an old page in favor of a newly

programmed page

 Reduces control, address, data, power, and

programming signals to a single data pin

 8-bit family code specifies DS1982

communications requirements to reader

 Reads over a wide voltage range of 2.8V to

6.0V from -40°C to +85°C; programs at 11.5V

to 12.0V from -40°C to +50°C

ORDERING INFORMATION

DS1982-F3+ F3 MicroCan

DS1982-F5+ F5 MicroCan

+Denotes a lead(Pb)-free/RoHS-compliant product.

EXAMPLES OF ACCESSORIES

DS9096P Self-Stick Adhesive Pad

DS9101 Multi-Purpose Clip

DS9093RA Mounting Lock Ring

DS9093F Snap-In Fob

DS9092 iButton Probe

F3 MicroCan

COMMON iButton FEATURES

 Unique, factory-lasered and tested 64-bit

registration number (8-bit family code + 48-bit

serial number + 8-bit CRC tester) assures

absolute traceability because no two parts are

alike

 Multidrop controller for MicroLAN

 Digital identification and information by

momentary contact

 Chip-based data carrier compactly stores

information

 Data can be accessed while affixed to object

 Economically communicates to bus master

with a single digital signal at 16.3kbps

 Standard 16mm diameter and 1-Wire

protocol

ensure compatibility with iButton

family

 Button shape is self-aligning with cup-shaped

probes

 Durable stainless steel case engraved with

registration number withstands harsh

environments

 Easily affixed with self-stick adhesive backing,

latched by its flange, or locked with a ring

pressed onto its rim

 Presence detector acknowledges when reader

first applies voltage

F5 MicroCan

DS1982

1Kb Add-Only i

Button

19-4891; Rev 8/09

iButton and 1-Wire are registered trademarks of Maxim Integrated Products, Inc.

Page 1 of 24

Summary of content (24 pages)

PAGE 1
9-4891; Rev 8/09 DS1982 1Kb Add-Only iButton SPECIAL FEATURES COMMON iButton FEATURES          1024 bits Electrically Programmable ReadOnly Memory (EPROM) communicates with the economy of one signal plus ground EPROM partitioned into four 256-bit pages for randomly accessing packetized data Each memory page can be permanently writeprotected to prevent tampering Device is an “add only” memory where additional data can be programmed into EPROM without disturbing existing data Architecture allo
PAGE 2
DS1982 iButton DESCRIPTION The DS1982 1Kb Add-Only iButton is a rugged read/write data carrier that identifies and stores relevant information about the product or person to which it is attached. This information can be accessed with minimal hardware, for example, a single port pin of a microcontroller. The DS1982 consists of a factorylasered registration number that includes a unique 48-bit serial number, an 8-bit CRC, and an 8-bit Family Code (09h) plus 1Kb of EPROM that is user-programmable.
PAGE 3
DS1982 64-BIT LASERED ROM Each DS1982 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits (see Figure 3). The 64-bit ROM and ROM Function Control section allow the DS1982 to operate as a 1-Wire device and follow the 1-Wire protocol detailed in the section “1-Wire Bus System.
PAGE 4
DS1982 DS1982 BLOCK DIAGRAM Figure 1 Page 4 of 24
PAGE 5
DS1982 HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 OTHER DEVICES BUS MASTER DS 1982 COMMAND LEVEL: 1-WIRE ROM FUNCTION COMMANDS (SEE FIGURE 9) DS1982-SPECIFIC MEMORY FUNCTION COMMANDS (SEE FIGURE 6) AVAILABLE COMMANDS: DATA FIELD AFFECTED: READ ROM MATCH ROM SEARCH ROM SKIP ROM 64-BIT ROM 64-BIT ROM 64-BIT ROM N/A WRITE MEMORY WRITE STATUS BYTE READ MEMORY READ STATUS BYTE READ DATA/GENERATE 8-BIT CRC 1024-BIT EPROM EPROM STATUS BYTES 1024-BIT EPROM EPROM STATUS BYTES 1024-BIT EPROM 64-B
PAGE 6
DS1982 1024-BIT EPROM The memory map in Figure 5 shows the 1024-bit EPROM section of the DS1982 that is configured as four pages of 32 bytes each. The 8-bit scratchpad is an additional register that acts as a buffer when programming the memory. Data is first written to the scratchpad and then verified by reading an 8-bit CRC from the DS1982 that confirms proper receipt of the data.
PAGE 7
DS1982 MEMORY FUNCTION COMMANDS The “Memory Function Flow Chart” (Figure 6) describes the protocols necessary for accessing the various data fields within the DS1982. The Memory Function Control section, 8-bit scratchpad, and the Program Voltage Detect circuit combine to interpret the commands issued by the bus master and create the correct control signals within the device. A 3-byte protocol is issued by the bus master.
PAGE 8
DS1982 MEMORY FUNCTION FLOW CHART Figure 6 Page 8 of 24
PAGE 9
DS1982 MEMORY FUNCTION FLOW CHART (cont’d) Figure 6 Page 9 of 24
PAGE 10
DS1982 MEMORY FUNCTION FLOW CHART (cont’d) Figure 6 Page 10 of 24
PAGE 11
DS1982 READ MEMORY [F0h] The Read Memory command is used to read data from the 1024-bit EPROM data field. The bus master follows the command byte with a 2-byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field. An 8–bit CRC of the command byte and address bytes is computed by the DS1982 and read back by the bus master to confirm that the correct command word and starting address were received.
PAGE 12
DS1982 initial address and continuing until the end of a 32-byte page is reached. At that point the bus master will send eight additional read time slots and receive an 8-bit CRC that is the result of shifting into the CRC generator all of the data bytes from the initial starting byte to the last byte of the current page. Once the 8-bit CRC has been received, data is again read from the 1024-bit EPROM data field starting at the next page.
PAGE 13
DS1982 significant byte of the new 2-byte address will also be loaded into the 8-bit CRC generator as a starting value. The bus master will issue the next byte of data using eight write time slots. As the DS1982 receives this byte of data into the scratchpad, it also shifts the data into the CRC generator that has been preloaded with the LSB of the current address, and the result is an 8-bit CRC of the new data byte and the LSB of the new address.
PAGE 14
DS1982 contains 0s in the same bit positions as the data byte, the programming was successful and the DS1982 will automatically increment its address counter to select the next byte in the EPROM Status data field. The least significant byte of the new 2-byte address will also be loaded into the 8-bit CRC generator as a starting value. The bus master will issue the next byte of data using eight write time slots.
PAGE 15
DS1982 A multidrop bus consists of a 1-Wire bus with multiple slaves attached. The 1-Wire bus has a maximum data rate of 16.3kbps. If the bus master is also required to perform programming of the EPROM portions of the DS1982, a programming supply capable of delivering up to 10 milliamps at 12 volts for 480 s is required. The idle state for the 1-Wire bus is high. If, for any reason, a transaction needs to be suspended, the bus MUST be left in the idle state if the transaction is to resume.
PAGE 16
DS1982 DS1982 EQUIVALENT CIRCUIT Figure 7 BUS MASTER CIRCUIT Figure 8 Page 16 of 24
PAGE 17
DS1982 ROM FUNCTIONS FLOW CHART Figure 9 Page 17 of 24
PAGE 18
DS1982 Skip ROM [CCh] This command can save time in a single-drop bus system by allowing the bus master to access the memory functions without providing the 64-bit ROM code. If more than one slave is present on the bus and a read command is issued following the Skip ROM command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pull–downs will produce a wired-AND result).
PAGE 19
DS1982 CRC GENERATION The DS1982 has an 8-bit CRC stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the first 56 bits of the 64-bit ROM and compare it to the value stored within the DS1982 to determine if the ROM data has been received error-free by the bus master. The equivalent polynomial function of this CRC is: X8 + X5 + X4 + 1.
PAGE 20
DS1982 READ/WRITE TIMING DIAGRAM Figure 11 Write-1 Time Slot 60 s  tSLOT < 120 s 1 s  tLOW1 < 15 s 1 s  tREC <  Write-0 Time Slot RESISTOR 60 s  tLOW0 < tSLOT < 120 s 1 s  tREC <  MASTER DS1982 Page 20 of 24
PAGE 21
DS1982 Read-data Time Slot RESISTOR MASTER DS1982 60 s  tSLOT < 120 s 1 s  tLOWR < 15 s 0  tRELEASE < 45 s 1 s  tREC <  tRDV = 15 s tSU < 1 s PROGRAM PULSE TIMING DIAGRAM Figure 12 Page 21 of 24
PAGE 22
DS1982 ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature  –0.5V to +12.0V –40°C to +85°C –55°C to +125°C This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. (VPUP=2.8V to 6.
PAGE 23
DS1982 NOTES: 1. All voltages are referenced to ground. 2. VPUP = external pullup voltage. 3. Input load is to ground. 4. An additional reset or communication sequence cannot begin until the reset high time has expired. 5. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 1 s of this falling edge and will remain valid for 14 s minimum. (15 s total from falling edge on 1-Wire bus.) 6.
PAGE 24
DS1982 REVISION HISTORY REVISION DATE 7/08 8/09 DESCRIPTION Updated the F3 MicroCan and F5 MicroCan face brands with the latest per PCN H020201. Added plus signs (+) to the Ordering Information to reflect the conversion to a lead-free product. Deleted the UL bullet from the Features section. PAGES CHANGED 1 1 24 of 24 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.