Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsIntegrated Circuits (ICs)64 kBit 256 x 256

AVAILABLE

Functional Diagrams

Pin Configurations appear at end of data sheet.

Functional Diagrams continued at end of data sheet.

UCSP is a trademark of Maxim Integrated Products, Inc.

For pricing, delivery, and

ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

SPECIAL FEATURES

 65,536 bits of read/write nonvolatile memory

 Overdrive mode boosts communication

speed to 142 kbits per second

 256-bit scratchpad ensures integrity of data

transfer

 Memory partitioned into 256-bit pages for

packetizing data

 Data integrity assured with strict read/write

protocols

 Operating temperature range from -40°C to

+70°C

 Over 10 years of data retention

F5 MICROCAN

DATA

GROUND

0.51

5.89

16.25

17.35

000000FBC52B

1-Wire



All dimensions are shown in millimeters

COMMON iButton FEATURES

 Unique, factory-lasered and tested 64-bit

registration number (8-bit family code + 48-

bit serial number 8-bit CRC tester) assures

absolute traceability because no two parts are

alike

 Multidrop controller for MicroLAN

 Digital identification and information by

momentary contact

 Chip-based data carrier compactly stores

information

 Data can be accessed while affixed to object

 Economically communicates to bus master

with a single digital signal at 16.3 kbits per

second

 Standard 16 mm diameter and 1-Wire

protocol ensure compatibility with iButton

family

 Button shape is self-aligning with cup-

shaped probes

 Durable stainless steel case engraved with

registration number withstands harsh

environments

 Easily affixed with self-stick adhesive

backing, latched by its flange, or locked with

a ring pressed onto its rim

 Presence detector acknowledges when reader

first applies voltage

ORDERING INFORMATION

PART

TEMP

RANGE

PIN-

PACKAGE

DS1996L-F5+

-40°C to +70°C

F5 MicroCan

+Denotes a lead(Pb)-free/RoHS-compliant package.

EXAMPLES OF ACCESSORIES

DS9096P Self-Stick Adhesive Pad

DS9101 Multi-Purpose Clip

DS9093RA Mounting Lock Ring

DS9093F Snap-In Fob

DS9092 iButton Probe

DS1996

64Kb Memory iButton

iButton and 1-Wire are registered trademarks of Maxim Integrated Products, Inc.

19-4896; Rev 8/09

Summary of content (19 pages)

PAGE 1
LE AVAILAB DS1996 64Kb Memory iButton SPECIAL FEATURES        65,536 bits of read/write nonvolatile memory Overdrive mode boosts communication speed to 142 kbits per second 256-bit scratchpad ensures integrity of data transfer Memory partitioned into 256-bit pages for packetizing data Data integrity assured with strict read/write protocols Operating temperature range from -40°C to +70°C Over 10 years of data retention COMMON iButton FEATURES         Unique, factory-lasered and tested 6
PAGE 2
DS1996 iButton DESCRIPTION The DS1996 Memory iButton is a rugged read/write data carrier that acts as a localized database that can be easily accessed with minimal hardware. The nonvolatile memory offers a simple solution to storing and retrieving vital information pertaining to the object to which the iButton is attached. Data is transferred serially via the 1-Wire protocol which requires only a single data lead and a ground return.
PAGE 3
DS1996 DS1996 BLOCK DIAGRAM Figure 1 3 of 19
PAGE 4
DS1996 HIERARCHICAL STRUCTURE FOR 1-WIRE PROTOCOL Figure 2 BUS MASTER OTHER DEVICES 1-WIRE BUS DS 1996 COMMAND LEVEL: 1-WIRE ROM FUNCTION COMMANDS (SEE FIGURE 9) DS 1996- SPECIFIC MEMORY FUNCTION COMMANDS (SEE FIGURE 7) AVAILABLE COMMANDS: DATA FIELDS AFFECTED: READ ROM MATCH ROM SEARCH ROM SKIP ROM OVERDRIVE SKIP ROM OVERDRIVE MATCH ROM 64-BIT ROM 64-BIT ROM 64-BIT ROM N/A N/A 64-BIT ROM WRITE SCRATCHPAD READ SCRATCHPAD COPY SCRATCHPAD READ MEMORY 256-BIT SCRATCHPAD 256-BIT SCRATCHPAD 64K-BIT
PAGE 5
DS1996 MEMORY The memory map in Figure 5 shows a 32-byte page called the scratchpad and additional 32-byte pages called memory. The DS1996 contains 256 pages which comprise the 65536-bit SRAM. The scratchpad is an additional page that acts as a buffer when writing to memory. ADDRESS REGISTERS AND TRANSFER STATUS Because of the serial data transfer, the DS1996 employs three address registers, called TA1, TA2 and E/S (Figure 6).
PAGE 6
DS1996 Write Scratchpad Command [0FH] After issuing the write scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at the byte offset (T4:T0). The ending offset (E4: E0) will be the byte offset at which the bus master has stopped writing data. Read Scratchpad Command [AAH] This command is used to verify scratchpad data and target address.
PAGE 7
MEMORY FUNCTION FLOW CHART Figure 7 1) 2) TO BE TRANSMITTED OR RECEIVED AT OVERDRIVE SPEED IF OD=1 RESET PULSE TO BE TRANSMITTED AT OVERDRIVE SPEED IF OD=1; RESET PULSE TO BE TRANSMITTED AT REGULAR SPEED IF OD=0 OR IF THE DS1996 IS TO BE RESET FROM OVERDRIVE SPEED TO REGULAR SPEED 7 of 19 DS1996
PAGE 8
DS1996 MEMORY FUNCTION EXAMPLES Example: Write two data bytes to memory locations 0026h and 0027h (the seventh and 8th bytes of page 1). Read entire memory.
PAGE 9
DS1996 Copy Scratchpad [55H] This command is used to copy data from the scratchpad to memory. After issuing the copy scratchpad command, the master must provide a 3-byte authorization pattern which is obtained by reading the scratchpad for verification. This pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that order). If the pattern matches, the AA (Authorization Accepted) flag will be set and the copy will begin.
PAGE 10
HARDWARE CONFIGURATION Figure 8 DS1996 Rx= RECEIVE Tx = TRANSMIT TRANSACTION SEQUENCE The protocol for accessing the DS1996 via the 1-Wire port is as follows:  Initialization  ROM Function Command  Memory Function Command  Transaction/Data INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s).
PAGE 11
DS1996 Match ROM [55H] The match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific DS1996 on a multidrop bus. Only the DS1996 that exactly matches the 64-bit ROM sequence will respond to the subsequent memory function command. All slaves that do not match the 64-bit ROM sequence will wait for a reset pulse. This command can be used with a single or multiple devices on the bus.
PAGE 12
DS1996 1-WIRE SIGNALING The DS1996 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1 and Read Data. All these signals except presence pulse are initiated by the bus master. The DS1996 can communicate at two different speeds, regular speed and Overdrive speed. If not explicitly set into the overdrive mode, the DS1996 will communicate at regular speed.
PAGE 13
ROM FUNCTIONS FLOW CHART Figure 9 1) TO BE TRANSMITTED OR RECEIVED AT OVERDRIVE SPEED IF OD=1 2) THE PRESENCE PULSE WILL BE SHORT IF OD=1 13 of 19 DS1996
PAGE 14
ROM FUNCTIONS FLOW CHART Figure 9 (cont’d) 3) ALWAYS TO BE TRANSMITTED AT OVERDRIVE SPEED 14 of 19 DS1996
PAGE 15
DS1996 INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 10 RESISTOR MASTER DS1996 Regular Speed 480 µs ≤ tRSTL < ∞ * 480 µs ≤ tRSTH < ∞ (includes recovery time) 15 µs ≤ PDH < 60 µs 60 µs ≤ tPDL < 240 µs Overdrive Speed 48 µs ≤ tRSTL < 80 µs 48 µs ≤ tRSTH < ∞ 2 µs ≤ tPDH < 6 µs 7 µs ≤ tPDL < 24 µs * In order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should always be less than 960 µs.
PAGE 16
READ/WRITE TIMING DIAGRAM Figure 11 (cont’d) Write-Zero Time Slot Regular Speed 60 µs ≤ tLOW0 < tSLOT < 120 µs 1 µs ≤ tREC < ∞ Overdrive Speed 6 µs ≤ tLOW0 < tSLOT < 16 µs 1 µs ≤ tREC < ∞ Read-Data Time Slot RESISTOR MASTER DS1996 Regular Speed 60 µs ≤ tSLOT < 120 µs 1 µs ≤ tLOWR < 15 µs 0 ≤ tRELEASE < 45 µs 1 µs ≤ tREC < ∞ tRDV = 15 µs tSU < 1 µs 16 of 19 Overdrive Speed 6 µs ≤ tSLOT < 16 µs 1 µs ≤ tLOWR < 2 µs 0 ≤ tRELEASE < 4 µs 1 µs ≤ tREC < ∞ tRDV = 2 µs tSU < 1 µs DS1996
PAGE 17
DS1996 PHYSICAL SPECIFICATIONS Size Weight Humidity Altitude Expected Service Life See mechanical drawing 3.3 grams (F5 package) 90% RH at 50°C 10,000 feet 10 years at 25°C ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature ∗ -0.5V to +7.
PAGE 18
AC ELECTRICAL CHARACTERISTICS: OVERDRIVE SPEED PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Data Valid Release Time Read Data Setup Recovery Time Reset Time High Reset Time Low Presence Detect High Presence Detect Low SYMBOL tSLOT tLOW1 tLOW0 tRDV tRELEASE tSU tREC tRSTH tRSTL tPDH tPDL MIN 6 1 6 0 1 48 48 2 7 TYP exactly 2 1.5 MAX 16 2 16 4 1 80 6 24 DS1996 (-40°C to 70°C) UNITS µs µs µs µs µs µs µs µs µs µs µs NOTES 4 3 NOTES: 1. All voltages are referenced to ground. 2.
PAGE 19
DS1996 REVISION HISTORY REVISION DATE 070808 8/09 DESCRIPTION Updated the Ordering Information table to only show the lead-free version (DS1996-F5+). Updated the F5 MicroCan marking to match PCN H020201. Updated the wording in the Parasite Power section. PAGES CHANGED 1 1 2 Changed the tPDL(MIN) spec from 8µs to 7µs in Figure 10 and in the AC Electrical Characteristics: Overdrive Speed table.