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ManualsBrandsMAXIM INTEGRATED ManualsInterface ICsInterface IC - telecommunication Parallel, Serial TQFP 44

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FEATURES

 Complete E1, T1, or J1 Line Interface Unit

(LIU)

 Supports Both Long-Haul And Short-Haul

Trunks

 Internal Software-Selectable Receive-Side

Termination for 75Ω/100Ω/120Ω

 3.3V Power Supply

 32-Bit or 128-Bit Crystal-Less Jitter

Attenuator Requires Only a 2.048MHz

Master Clock for Both E1 and T1 with

Option to Use 1.544MHz for T1

 Generates the Appropriate Line Build-Outs,

with and without Return loss, for E1 and

DSX-1 and CSU Line Build-Outs for T1

 AMI, HDB3, and B8ZS, Encoding/Decoding

 16.384MHz, 8.192MHz, 4.096MHz, or

2.048MHz Clock Output Synthesized to

Recovered Clock

 Programmable Monitor Mode for Receiver

 Loopbacks and PRBS Pattern Generation/

Detection with Output for Received Errors

 Generates/Detects In-Band Loop Codes,

1 to 16 Bits Including CSU Loop Codes

 8-Bit Parallel or Serial Interface with

Optional Hardware Mode

 Muxed and Nonmuxed Parallel Bus Supports

Intel or Motorola

 Detects/Generates Blue (AIS) Alarms

 NRZ/Bipolar Interface for Tx/Rx Data I/O

 Transmit Open-Circuit Detection

 Receive Carrier Loss (RCL) Indication

(G.775)

 High-Impedance State for TTIP and TRING

 50mA (RMS) Current Limiter

PIN CONFIGURATIONS

ORDERING INFORMATION

+ Denotes lead-free/RoHS-compliant package.

PART CHANNEL

TEMP

RANGE

PIN-PACKAGE

DS21348TN Single -40°C to +85°C 44 TQFP

DS21348TN+ Single -40°C to +85°C 44 TQFP

DS21348T Single 0°C to +70°C 44 TQFP

DS21348T+ Single 0°C to +70°C 44 TQFP

DS21348GN Single -40°C to +85°C 49 CSBGA

DS21348GN+ Single -40°C to +85°C 49 CSBGA

DS21348G Single 0°C to +70°C 49 CSBGA

DS21348G+ Single 0°C to +70°C 49 CSBGA

DS21Q348N Four -40°C to +85°C 144 CSBGA

DS21Q348 Four 0°C to +70°C 144 CSBGA

111

PRELMINARY

DS21348/DS21Q348

3.3V E1/T1/J1 Line Interface

www.maxim-ic.com

44 TQFP

DS21348

49 CSBGA

(7mm x 7mm)

DS21Q348

TOP VIEW

See Section 8 for 144-pin CSBGA pinout.

Summary of content (76 pages)

PAGE 1
DS21348/DS21Q348 3.3V E1/T1/J1 Line Interface www.maxim-ic.com FEATURES PIN CONFIGURATIONS 111 Complete E1, T1, or J1 Line Interface Unit (LIU) Supports Both Long-Haul And Short-Haul Trunks Internal Software-Selectable Receive-Side Termination for 75Ω/100Ω/120Ω 3.3V Power Supply 32-Bit or 128-Bit Crystal-Less Jitter Attenuator Requires Only a 2.048MHz Master Clock for Both E1 and T1 with Option to Use 1.
PAGE 2
DS21348/DS21Q348 DETAILED DESCRIPTION The DS21348 is a complete selectable E1 or T1 line interface unit (LIU) for short-haul and long-haul applications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0dB to 12dB or 0dB to 43dB for E1 applications and 0dB to 30dB or 0dB to 36dB for T1 applications. The device can generate the necessary G.
PAGE 3
DS21348/DS21Q348 TABLE OF CONTENTS 1. INTRODUCTION.................................................................................................................. 6 1.1 2. DOCUMENT REVISION HISTORY...............................................................................................6 PIN DESCRIPTION............................................................................................................ 10 2.1 3. PIN DESCRIPTIONS ..........................................................
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DS21348/DS21Q348 LIST OF FIGURES Figure 1-1. DS21348 Block Diagram ..........................................................................................................7 Figure 1-2. Receive Logic...........................................................................................................................8 Figure 1-3. Transmit Logic..........................................................................................................................9 Figure 2-1.
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DS21348/DS21Q348 LIST OF TABLES Table 2-1. Bus Interface Selection ...........................................................................................................10 Table 2-2. Pin Assignment in Parallel Port Mode .....................................................................................10 Table 2-3. Pin Assignment in Serial Port Mode ........................................................................................11 Table 2-4. Pin Assignment in Hardware Mode ..................
PAGE 6
DS21348/DS21Q348 1. INTRODUCTION The analog AMI/HDB3 waveform off of the E1 line or the AMI/B8ZS waveform off of the T1 line is transformer coupled into the RTIP and RRING pins of the DS21348. The user has the option to use internal termination, software selectable for 75Ω/100Ω/120Ω applications, or external termination.
PAGE 7
DS21348/DS21Q348 MCLK VSM VDD VSS Figure 1-1. DS21348 Block Diagram 2 2 JACLK Jitter Attenuator MUX Power Connections 2.048MHz to 1.
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DS21348/DS21Q348 Figure 1-2. Receive Logic Clock Invert From Remote Loopback Routed to All Blocks RCLK CCR2.0 RPOS mux B8ZS/HDB3 Decoder NRZ Data RNEG BPV/CV/EXZ CCR1.6 4 or 8 Zero Detect 16 Zero Detect CCR2.3 CCR6.2/ RIR1.5 CCR6.0/ CCR6.1 All Ones Detector SR.4 RIR1.3 RIR1.7 Loop Code Detector SR.6 SR.7 PBEO PRBS Detector SR.0 mux CCR6.0 RIR1.6 CCR1.
PAGE 9
DS21348/DS21Q348 Figure 1-3. Transmit Logic CCR3.3 CCR1.6 CCR3.4 CCR2.2 CCR3.1 PRBS Generator CCR3.0 OR Gate mux 1 To Remote Loopback BPV Insert B8ZS/ HDB3 Coder Loop Code Generator Logic Error Insert TPOS OR Gate TNEG mux 0 0 0 Clock Invert mux Routed to All Blocks JACLK (derived from MCLK) 1 mux 1 RCLK OR Gate CCR2.1 AND Gate CCR1.1 Loss Of Transmit Clock Detect CCR1.2 CCR1.0 tx bd To LOTC Output Pin 9 of 76 SR.
PAGE 10
DS21348/DS21Q348 2. PIN DESCRIPTION The DS21348 can be controlled in a parallel port mode, serial port mode, or hardware mode (Table 2-2, Table 2-3, and Table 2-4). Table 2-1. Bus Interface Selection BIS1 0 0 0 0 1 1 BIS0 0 0 1 1 0 1 PBTS 0 1 0 1 — — MODE Muxed Intel Muxed Motorola Nonmuxed Intel Nonmuxed Motorola Serial Port Hardware Table 2-2.
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DS21348/DS21Q348 PIN DS21348T 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 DS21348G D7 C6 C7 B6 B7 A7 C5 B5 A6 B4 C4 A4 B3 A3 B2 A2 A1 I/O I I I O I I O — — O O O O I I I I PARALLEL PORT MODE RRING HRST MCLK BPCLK BIS0 BIS1 TTIP VSS VDD TRING RPOS RNEG RCLK TPOS TNEG TCLK PBTS Table 2-3.
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DS21348/DS21Q348 PIN DS21348T 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 DS21348G E5 E6 F7 D6 D5 D7 C6 C7 B6 B7 A7 C5 B5 A6 B4 C4 A4 B3 A3 B2 A2 A1 I/O I/O O O I I I I I O I I O — — O O O O I I I I SERIAL PORT MODE INT PBEO RCL/LOTC TEST RTIP RRING HRST MCLK BPCLK BIS0 BIS1 TTIP VSS VDD TRING RPOS RNEG RCLK TPOS TNEG TCLK NA Table 2-4.
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DS21348/DS21Q348 PIN DS21348T 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 DS21348G E4 G4 F5 G5 F6 G6 E5 E6 F7 D6 D5 D7 C6 C7 B6 B7 A7 C5 B5 A6 B4 C4 A4 B3 A3 B2 A2 A1 I/O I/O I/O I/O I — — I/O O O I I I I I O I I O — — O O O O I I I I HARDWARE MODE LOOP1 MM0 MM1 VSM VDD VSS RT1 PBEO RCL TEST RTIP RRING HRST MCLK BPCLK BIS0 BIS1 TTIP VSS VDD TRING RPOS RNEG RCLK TPOS TNEG TCLK RT0 13 of 76
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DS21348/DS21Q348 2.1 Pin Descriptions Table 2-5. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name, DS21348T Pin Numbering) NAME PIN I/O A0 to A4 11 to 7 I ALE (AS) 4 I BIS0/BIS1 32/33 I BPCLK 31 O CS 1 I D0/AD0 to D7/AD7 19 to 12 I/O HRST 29 I INT 23 O MCLK 30 I N/A — I PBEO 24 O FUNCTION Address Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 = 1), serves as the address bus.
PAGE 15
DS21348/DS21Q348 NAME PIN I/O PBTS 44 I RCLK 40 O RD (DS) 2 I RCL/ LOTC 25 O RNEG 39 O RPOS 38 O RTIP/ RRING 27/28 I TCLK 43 I TEST 26 I TNEG 42 I TPOS 41 I FUNCTION Parallel Bus Type Select. When using the parallel port (BIS1 = 0), set high to select Motorola bus timing, set low to select Intel bus timing. This pin controls the function of the RD (DS), ALE (AS), and WR (R/W) pins.
PAGE 16
DS21348/DS21Q348 NAME PIN I/O TTIP/ TRING 34/37 O VDD VSM VSS 21/36 20 22/35 — I — WR (R/W) 3 I FUNCTION Transmit Tip and Ring [TTIP AND TRING]. Analog line driver outputs. These pins connect via a step-up transformer to the line. See Section 5 for details. Positive Supply. 3.3V ±5% Voltage Supply Mode. Should be low for 3.3V operation. Signal Ground Write Input (Read/Write), Active Low. See the bus timing diagrams in Section 11. Table 2-6.
PAGE 17
DS21348/DS21Q348 NAME PIN I/O RCLK 40 O RCL/LOTC 25 O RNEG 39 O RPOS 38 O RTIP/ RRING 27/28 I SCLK 5 I SDI 6 I SDO 7 O TCLK 43 I TEST 26 I TNEG 42 I TPOS 41 I TTIP/TRIN G 34/37 O VDD VSM VSS 21/36 20 22/35 — I — FUNCTION Receive Clock. Buffered recovered clock from the line. Synchronous to MCLK in absence of signal at RTIP and RRING. Receive Carrier Loss/Loss of Transmit Clock. An output which will toggle high during a receive carrier loss (CCR2.
PAGE 18
DS21348/DS21Q348 Table 2-7. Pin Descriptions in Hardware Mode (Sorted By Pin Name, DS21348T Pin Numbering) NAME PIN I/O BIS0/BIS1 32/33 I BPCLK 31 O CES 12 I DJA 8 I EGL 1 I ETS 2 I HBE 11 I HRST 29 I JAMUX 9 I JAS 10 I L0/L1/L2 7/6/5 I LOOP0/ LOOP1 16/17 I FUNCTION Bus Interface Select Bits 0 and 1. Used to select bus interface option. BIS0 = 1 and BIS1 = 1 selects hardware mode. Backplane Clock. 16.384MHz output. Receive and Transmit Clock Edge Select.
PAGE 19
DS21348/DS21Q348 NAME PIN I/O MCLK 30 I MM0/MM1 18/19 I NA — I NRZE 3 I PBEO 24 O RCLK 40 O RCL 25 O RNEG 39 O RPOS 38 O RT0/RT1 44/23 I RTIP/ RRING 27/28 I SCLKE 4 I TCLK 43 I FUNCTION Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and for jitter attenuation. Use of a T1 1.544MHz clock source is optional. G.703 requires an accuracy of ±50ppm for both T1 and E1.
PAGE 20
DS21348/DS21Q348 NAME PIN I/O TEST 26 I TNEG 42 I TPD 13 I TPOS 41 I TTIP/TRING 34/37 O TX0/TX1 14/15 I VDD VSM VSS 21/36 20 22/35 — I — FUNCTION Tri-State Control. Set high to tri-state all outputs and I/O pins (including the parallel control port). Set low for normal operation. Useful in board-level testing. Transmit Negative Data. Sampled on the falling edge (CES = 0) or the rising edge (CES = 1) of TCLK for data to be transmitted out onto the line.
PAGE 21
DS21348/DS21Q348 Table 2-8. Loopback Control in Hardware Mode LOOPBACK SYMBOL Remote Loopback Local Loopback Analog Loopback No Loopback RLB LLB ALB — CONTROL BIT CCR6.6 CCR6.7 CCR6.4 — LOOP1 LOOP0 1 1 0 0 1 0 1 0 Table 2-9. Transmit Data Control in Hardware Mode TRANSMIT DATA Transmit Unframed All Ones Transmit Alternating Ones and Zeros Transmit PRBS TPOS and TNEG SYMBOL CONTROL BIT TX1 TX0 TUA1 CCR3.7 1 1 TAOZ CCR3.5 1 0 TPRBSE — CCR3.4 — 0 0 1 0 Table 2-10.
PAGE 22
DS21348/DS21Q348 Table 2-13. MCLK Selection MCLK (MHz) 2.048 2.048 1.544 JAMUX (CCR1.3) 0 1 0 ETS (CCR1.7) 0 1 1 Figure 2-1.
PAGE 23
DS21348/DS21Q348 Figure 2-2.
PAGE 24
DS21348/DS21Q348 Figure 2-3.
PAGE 25
DS21348/DS21Q348 3. HARDWARE MODE In hardware mode (BIS1 = 1, BIS0 = 1), pins 1–19, 23, 25, 31, and 44 are redefined to be used for initializing the DS21348. BPCLK (pin 31) defaults to a 16.384MHz output when in hardware mode. The RCL/LOTC (pin 25) is designated to RCL when in hardware mode. JABDS (CCR4.2) defaults to logic 0. The RHBE (CCR2.3) and THBE (CCR2.2) control bits are combined and controlled by HBE at pin 11 while the RSCLKE (CCR5.3) and TSCLKE (CCR5.
PAGE 26
DS21348/DS21Q348 3.2 Parallel Port Operation When using the parallel interface on the DS21348 (BIS1 = 0) the user has the option for either multiplexed bus operation (BIS1 = 0, BIS0 = 0) or non-multiplexed bus operation (BIS1 = 0, BIS0 = 1). The DS21348 can operate with either Intel or Motorola bus timing configurations. If the PBTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parentheses ().
PAGE 27
DS21348/DS21Q348 Figure 3-1. Serial Port Operation for Read Access (R = 1) Mode 1 ICES = 1 (sample SDI on the falling edge of SCLK) OCES = 1 (update SDO on rising edge of SCLK) 1 SCLK 2 3 4 5 6 A0 A1 A2 A32 A4 7 8 9 10 11 12 13 14 15 16 D0 D1 D2 D3 D4 D5 D6 CS SDI 1 0 B (lsb) (msb) READ ACCESS ENABLED SDO D7 (lsb) (msb) Figure 3-2.
PAGE 28
DS21348/DS21Q348 Figure 3-4. Serial Port Operation for Read Access Mode 4 ICES = 0 (sample SDI on the rising edge of SCLK) OCES = 1 (update SDO on rising edge of SCLK) 1 SCLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CS SDI A0 1 A1 A2 A3A5 A4 B 0 (lsb) (msb) SDO D0 D1 D2 D3 D4 D5 D6 D7 (lsb) (msb) Figure 3-5.
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DS21348/DS21Q348 4. CONTROL REGISTERS CCR1 (00H): COMMON CONTROL REGISTER 1 (MSB) ETS NRZE SYMBOL POSITION ETS CCR1.7 NRZE CCR1.6 RCLA CCR1.5 ECUE CCR1.4 JAMUX CCR1.3 TTOJ CCR1.2 TTOR CCR1.1 LOTCMC CCR1.0 RCLA ECUE JAMUX TTOJ TTOR (LSB) LOTCMC DESCRIPTION E1/T1 Select. 0 = E1 1 = T1 NRZ Enable. 0 = Bipolar data at RPOS/RNEG and TPOS/TNEG 1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a positive going pulse when device receives a BPV, CV, or EXZ. See Figure 1-2 and Figure 1-3.
PAGE 30
DS21348/DS21Q348 Table 4-1. MCLK Selection MCLK (MHz) 2.048 2.048 1.544 JAMUX (CCR1.3) 0 1 0 ETS (CCR1.7) 0 1 1 CCR2 (01H): COMMON CONTROL REGISTER 2 (MSB) P25S n/a SYMBOL POSITION P25S CCR2.7 SCLD CCR2.6 CCR2.5 CLDS CCR2.4 RHBE CCR2.3 THBE CCR2.2 TCES CCR2.1 RCES CCR2.0 SCLD CLDS RHBE THBE TCES (LSB) RCES DESCRIPTION Pin 25 Select. Forced to logic 0 in hardware mode.
PAGE 31
DS21348/DS21Q348 CCR3 (02H): COMMON CONTROL REGISTER 3 (MSB) TUA1 ATUA1 SYMBOL POSITION TUA1 CCR3.7 ATUA1 CCR3.6 TAOZ CCR3.5 TPRBSE CCR3.4 TLCE CCR3.3 LIRST CCR3.2 IBPV CCR3.1 IBE CCR3.0 TAOZ TPRBSE TLCE LIRST IBPV (LSB) IBE DESCRIPTION Transmit Unframed All Ones. The polarity of this bit is set such that the device will transmit an all ones pattern on power-up or device reset. This bit must be set to a one to allow the device to transmit data.
PAGE 32
DS21348/DS21Q348 4.1 Device Power-Up and Reset The DS21348 will reset itself upon power-up setting all writeable registers to 00h and clear the status and information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After the power supplies have settled following power-up, initialize all control registers to the desired settings, then toggle the LIRST bit (CCR3.2).
PAGE 33
DS21348/DS21Q348 CCR5 (04H): COMMON CONTROL REGISTER 5 (MSB) BPCS1 BPCS0 MM1 MM0 RSCLKE TSCLKE RT1 (LSB) RT0 SYMBOL POSITION DESCRIPTION BPCS1 CCR5.7 Backplane Clock Select 1. See Table 4-3 for details. BPCS0 CCR5.6 Backplane Clock Select 0. See Table 4-3 for details MM1 CCR5.5 Monitor Mode 1. See Table 4-4. MM0 CCR5.4 Monitor Mode 0. See Table 4-4. RSCLKE CCR5.3 TSCLKE CCR5.2 RT1 CCR5.1 Receive Synchronization Clock Enable.
PAGE 34
DS21348/DS21Q348 Table 4-3. Backplane Clock Select BPCS1 (CCR5.7) 0 0 1 1 BPCS0 (CCR5.6) 0 1 0 1 BPCLK FREQUENCY 16.384MHz 8.192MHz 4.096MHz 2.048MHz Table 4-4. Monitor Gain Settings MM1 (CCR5.5) MM0 (CCR5.4) 0 0 0 1 1 1 0 1 INTERNAL LINEAR GAIN BOOST Normal operation (no boost) 20dB 26dB 32dB Table 4-5. Internal Rx Termination Select RT1 (CCR5.1) 0 0 1 1 RT0 (CCR5.
PAGE 35
DS21348/DS21Q348 CCR6 (05H): COMMON CONTROL REGISTER 6 (MSB) LLB RLB ARLBE ALB RJAB ECRS2 ECRS1 (LSB) ECRS0 SYMBOL POSITION DESCRIPTION LLB CCR6.7 RLB CCR6.6 ARLBE CCR6.5 ALB CCR6.4 Analog Loopback. In Analog Loopback (ALB), signals at TTIP and TRING will be internally connected to RTIP and RRING. The incoming signals, from the line, at RTIP and RRING will be ignored. The signals at TTIP and TRING will be transmitted as normal. See Figure 1-1 and Section 6.2.3 for more details.
PAGE 36
DS21348/DS21Q348 5. STATUS REGISTERS There are three registers that contain information on the current real-time status of the device, Status Register (SR) and Receive Information Registers 1 and 2 (RIR1/RIR2). When a particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one. Some of the bits in SR, RIR1, and RIR2 are latched bits and some are real time bits.
PAGE 37
DS21348/DS21Q348 SR (06H): STATUS REGISTER (MSB) LUP LDN SYMBOL POSITION LUP (latched) LDN (latched) SR.7 LOTC (real time) RUA1 (latched) RCL (latched) TCLE (real time) TOCD (real time) PRBSD (real time) SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0 LOTC RUA1 RCL TCLE TOCD (LSB) PRBSD DESCRIPTION Loop-Up Code Detected. Set when the loop-up code defined in registers RUPCD1 and RUPCD2 is being received. See Section 4 for details. Loop-Down Code Detected.
PAGE 38
DS21348/DS21Q348 IMR (07H): INTERRUPT MASK REGISTER (MSB) LUP LDN LOTC SYMBOL POSITION LUP IMR.7 LDN IMR.6 LOTC IMR.5 RUA1 IMR.4 RCL IMR.3 TCLE IMR.2 TOCD IMR.1 PRBSD IMR.0 RUA1 RCL TCLE DESCRIPTION Loop-Up Code Detected. 0 = interrupt masked 1 = interrupt enabled Loop-Down Code Detected. 0 = interrupt masked 1 = interrupt enabled Loss of Transmit Clock. 0 = interrupt masked 1 = interrupt enabled Receive Unframed All Ones.
PAGE 39
DS21348/DS21Q348 RIR1 (08H): RECEIVE INFORMATION REGISTER 1 (MSB) ZD 16ZD HBD SYMBOL POSITION ZD (latched) RIR1.7 16ZD (latched) RIR1.6 HBD (latched) RIR1.5 RCLC (latched) RUA1C (latched) JALT (latched) RIR1.4 RCLC RUA1C JALT n/a (LSB) n/a DESCRIPTION N/A RIR1.1 Zero Detect. Set when a string of at least four (ETS = 0) or eight (ETS = 1) consecutive zeros (regardless of the length of the string) have been received. Will be cleared when read. Sixteen Zero Detect.
PAGE 40
DS21348/DS21Q348 RIR2 (09H): RECEIVE INFORMAION REGISTER 2 (MSB) RL3 RL2 RL1 RL0 N/A N/A ARLB (LSB) SEC SYMBOL POSITION DESCRIPTION RL3 (real time) RL2 (real time) RL1 (real time) RL0 (real time) N/A RIR2.7 Receive Level Bit 3. See Table 5-2. RIR2.6 Receive Level Bit 2. See Table 5-2. RIR2.5 Receive Level Bit 1. See Table 5-2. RIR2.4 Receive Level Bit 0. See Table 5-2. RIR2.3 Not Assigned. Could be any value when read. N/A RIR2.2 Not Assigned. Could be any value when read.
PAGE 41
DS21348/DS21Q348 6. DIAGNOSTICS 6.1 In-Band Loop Code Generation and Detection The DS21348 can generate and detect a repeating bit pattern that is from one to eight or sixteen bits in length. To transmit a pattern, the user will load the pattern to be sent into the Transmit Code Definition (TCD1 and TCD2) registers and select the proper length of the pattern by setting the TC0 and TC1 bits in the In-Band Code Control (IBCC) register.
PAGE 42
DS21348/DS21Q348 TC1 TC0 0 0 1 1 0 1 0 1 LENGTH SELECTED (BITS) 5 6/3 7 16/8/4/2/1 Table 6-2. Receive Code Length RUP2/RDN2 RUP1/ RDN1 0 0 0 0 1 1 1 1 RUP0/RDN0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LENGTH SELECTED (BITS) 1 2 3 4 5 6 7 16/8 TCD1 (0BH): TRANSMIT CODE DEFINITION REGISTER 1 (MSB) C7 C6 C5 C4 C3 C2 C1 (LSB) C0 SYMBOL POSITION DESCRIPTION C7 TCD1.7 C6 TCD1.6 Transmit Code Definition Bit 7. First bit of the repeating pattern. Transmit Code Definition Bit 6. C5 TCD1.
PAGE 43
DS21348/DS21Q348 TCD2 (0CH): TRANSMIT CODE DEFINITION REGISTER 2 (MSB) C15 C14 C13 C12 C11 C10 SYMBOL POSITION C15 TCD2.7 Transmit Code Definition Bit 15 C14 TCD2.6 Transmit Code Definition Bit 14 C13 TCD2.5 Transmit Code Definition Bit 13 C12 TCD2.4 Transmit Code Definition Bit 12 C11 TCD2.3 Transmit Code Definition Bit 11 C10 TCD2.2 Transmit Code Definition Bit 10 C9 TCD2.1 Transmit Code Definition Bit 9 C8 TCD2.
PAGE 44
DS21348/DS21Q348 RUPCD2 (0EH): RECEIVE UP CODE DEFINITION REGISTER 2 (MSB) C15 C14 C13 C12 C11 C10 SYMBOL POSITION DESCRIPTION C15 RUPCD2.7 Receive Up Code Definition Bit 15 C14 RUPCD2.6 Receive Up Code Definition Bit 14 C13 RUPCD2.5 Receive Up Code Definition Bit 13 C12 RUPCD2.4 Receive Up Code Definition Bit 12 C11 RUPCD2.3 Receive Up Code Definition Bit 11 C10 RUPCD2.2 Receive Up Code Definition Bit 10 C9 RUPCD2.1 Receive Up Code Definition Bit 9 C8 RUPCD2.
PAGE 45
DS21348/DS21Q348 RDNCD2 (10H): RECEIVE DOWN CODE DEFINITION REGISTER 2 (MSB) C15 C14 C13 C12 C11 C10 SYMBOL POSITION DESCRIPTION C15 RDNCD2.7 Receive Down Code Definition Bit 15 C14 RDNCD2.6 Receive Down Code Definition Bit 14 C13 RDNCD2.5 Receive Down Code Definition Bit 13 C12 RDNCD2.4 Receive Down Code Definition Bit 12 C11 RDNCD2.3 Receive Down Code Definition Bit 11 C10 RDNCD2.2 Receive Down Code Definition Bit 10 C9 RDNCD2.1 Receive Down Code Definition Bit 9 C8 RDNCD2.
PAGE 46
DS21348/DS21Q348 6.2 Loopbacks 6.2.1 Remote Loopback (RLB) When RLB (CCR6.6) is enabled, the DS21348 is placed into remote loopback. In this loopback, data from the clock/data recovery state machine will be looped back to the transmit path passing through the jitter attenuator if it is enabled. The data at the RPOS and RNEG pins will be valid while data presented at TPOS and TNEG will be ignored. See Figure 1-1 for details. If the Automatic Remote Loop Back Enable (CCR6.
PAGE 47
DS21348/DS21Q348 6.3 PRBS Generation and Detection Setting TPRBSE (CCR3.4) = 1 enables the DS21348 to transmit a 215 - 1 (E1) or a 220 - 1 (T1) PseudoRandom Bit Sequence (PRBS) depending on the ETS bit setting in CCR1.7. The receive-side of the DS21348 will always search for these PRBS patterns independent of CCR3.4.
PAGE 48
DS21348/DS21Q348 Table 6-4. Function of ECRS Bits and RNEG Pin E1 or T1 (CCR1.7) 0 0 0 0 1 1 1 1 X ECRS2 (CCR6.2) 0 0 0 0 0 0 0 0 1 ECRS1 (CCR6.1) 0 0 1 1 X X X X X ECRS0 (CCR6.0) 0 1 0 1 0 1 0 1 X RHBE (CCR2.3) X X X X 0 0 1 1 X FUNCTION OF ECR COUNTERS/RNEG1 CVs BPVs (HDB3 code words not counted) CVs + EXZs BPVs + EXZs BPVs (B8ZS code words not counted) BPVs + 8 EXZs BPVs BPVs + 16 EXZs PRBS Errors2 Note 1: RNEG outputs error data only when in NRZ mode (CCR1.
PAGE 49
DS21348/DS21Q348 7. ANALOG INTERFACE 7.1 Receiver The DS21348 contains a digital clock recovery system. The DS21348 couples to the receive E1 or T1 twisted pair (or coaxial cable in 75Ω E1 applications) via a 1:1 transformer. See Table 7-3 for transformer details. Figure 7-1, Figure 7-2, and Figure 7-3 along with Table 7-1 and Table 7-2 show the receive termination requirements. The DS21348 has the option of using internal termination resistors.
PAGE 50
DS21348/DS21Q348 7.2 Transmitter The DS21348 uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter (DAC) to create the waveforms that are transmitted onto the E1 or T1 line. The waveforms created by the DS21348 meet the latest ETSI, ITU, ANSI, and AT&T specifications. The user will select which waveform is to be generated by setting the ETS bit (CCR1.
PAGE 51
DS21348/DS21Q348 7.4 G.703 Synchronization Signal The DS21348 can receive a 2.048MHz square-wave synchronization clock as specified in Section 13 of ITU G.703(10/98). To use the DS21348 in this mode, set the Receive Synchronization Clock Enable (CCR5.3) = 1. The DS21348 can also transmit the 2.048MHz square-wave synchronization clock as specified in Section 10 of G.703. To transmit the 2.048MHz clock, set the Transmit Synchronization Clock Enable (CCR5.2) = 1. Table 7-1.
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DS21348/DS21Q348 Figure 7-1. Basic Interface DS21348 Rt Transmit Line TTIP 1.0µF (nonpolarized) Rt VDD (21) VSS (22) TRING N:1 (larger winding toward the network) VDD (36) VSS (35) RTIP Receive Line RRING MCLK +VDD 0.1µF 0.01µF 10µF 0.1µF 10µF 2.048MHz (this clock can also be 1.544MHz for T1 only applications) 1:1 Rr Rr 0.1µF NOTES: 1) All resistor values are ±1%. 2) In E1 applications, the Rt resistors are used to increase the transmitter return loss (Table 7-1).
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DS21348/DS21Q348 Figure 7-2. Protected Interface Using Internal Receive Termination +VDD D1 (optional) Rp Fuse Rt Transmit Line Fuse TTIP 1.0µF (nonpolarized) S C1 TRING Rt Rp D3 N:1 (larger winding toward the network) DS21348 D2 D4 VDD (21) VSS (22) VDD (36) VSS (35) +VDD 0.1µF 0.01µF 10µF 68µF 0.1µF 10µF +VDD D6 D5 Fuse Rp RTIP Receive Line S Fuse Rp (optional) C2 RRING MCLK 2.048MHz (this clock can also be 1.544MHz for T1 only applications) 1:1 60 60 D7 D8 0.
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DS21348/DS21Q348 Figure 7-3. Protected Interface Using External Receive Termination +VDD D1 (optional) Rp Fuse Rt Transmit Line D3 N:1 (larger winding toward the network) Fuse Rp Fuse Rp C1 TRING Rt Rp D4 470 RTIP Receive Line (optional) RRING 470 1:1 Rr DS21348 TTIP 1.0µF (nonpolarized) S Fuse D2 VDD (21) VSS (22) VDD (36) VSS (35) MCLK +VDD 0.1µF 0.01µF 10µF 68µF 0.1µF 10µF 2.048MHz (this clock can also be 1.544MHz for T1 only applications) Rr 0.1µF NOTES: 1. 2. 3. 4.
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DS21348/DS21Q348 Figure 7-4. E1 Transmit Pulse Template 1.2 1.1 269ns SCALED AMPLITUDE (in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 1.0 0.9 0.8 0.7 G.703 Template 194ns 0.6 0.5 219ns 0.4 0.3 0.2 0.1 0 -0.1 -0.
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DS21348/DS21Q348 Figure 7-5. T1 Transmit Pulse Template 1.2 MAXIMUM CURVE UI Time Amp. 1.1 1.0 -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 0.9 0.8 NORMALIZED AMPLITUDE 0.7 0.6 -500 -255 -175 -175 -75 0 175 225 600 750 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 0.5 MINIMUM CURVE UI Time Amp. -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.16 -500 -150 -150 -100 0 100 150 150 300 430 600 750 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05 0.4 0.
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DS21348/DS21Q348 Figure 7-6. Jitter Tolerance UNIT INTERVALS (UIP-P) 1k 100 DS21348 TR 62411 (Dec. 90) Tolerance 10 ITU-T G.823 1 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k Figure 7-7. Jitter Attenuation ITU G.7XX Prohibited Area TBR12 Prohibited Area -20dB C ur ve A E1 T1 TR 62411 (Dec.
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DS21348/DS21Q348 8. DS21Q348 QUAD LIU The DS21Q348 is a quad version of the DS21348G utilizing CSBGA on carrier packaging technology. The four LIUs are controlled via the parallel port mode. Serial and hardware modes are unavailable in this package. Table 8-1.
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DS21348/DS21Q348 PIN I/O F9 J7 A1 A4 A7 A10 B2 B5 B8 B11 H4 D6 F10 L8 A2 A5 A8 A11 B3 B6 B9 B12 K4 E1 D11 K11 G2 E2 F11 M10 H3 F1 E11 L11 G1 F2 E12 M11 H2 M1 D12 K12 M2 L2 O O I I I I I I I I O O O O O O O O O O O O O O O O O O O O O O O O I I I I I I I I I I PARALLEL PORT MODE RCL/LOTC3 RCL/LOTC4 RTIP1 RTIP2 RTIP3 RTIP4 RRING1 RRING2 RRING3 RRING4 BPCLK1 BPCLK2 BPCLK3 BPCLK4 TTIP1 TTIP2 TTIP3 TTIP4 TRING1 TRING2 TRING3 TRING4 RPOS1 RPOS2 RPOS3 RPOS4 RNEG1 RNEG2 RNEG3 RNEG4 RCLK1 RCLK2 RCLK3 RCLK4 TPOS
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DS21348/DS21Q348 PIN I/O F12 L12 J5 D2 G9 M9 L5 E4 D8 J8 J4 D1 E9 L10 M4 F4 D9 H9 I I — — — — — — — — — — — — — — — — PARALLEL PORT MODE TCLK3 TCLK4 VDD1 VDD2 VDD3 VDD4 VDD1 VDD2 VDD3 VDD4 VSS1 VSS2 VSS3 VSS4 VSS1 VSS2 VSS3 VSS4 60 of 76
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DS21348/DS21Q348 Figure 8-1.
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DS21348/DS21Q348 9. DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………..-1.0V to +6.0V Operating Temperature Range for DS21348TN……………………………………………-40°C to +85°C Storage Temperature Range……………………………………………………………….-55°C to +125°C Soldering Temperature………………………………………….
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DS21348/DS21Q348 10. THERMAL CHARACTERISTICS Table 10-1. Thermal Characteristics—DS21Q348 CSBGA Package PARAMETER Ambient Temperature Junction Temperature Theta-JA (θJA) in Still Air Theta-JC (θJC) in Still Air MIN -40ºC TYP +24ºC/W +4.1ºC/W MAX +85ºC +125ºC NOTES 1 2 3 NOTES: 1) The package is mounted on a four-layer JEDEC-standard test board. 2) Theta-JA (θJA) is the junction to ambient thermal resistance, when the package is mounted on a fourlayer JEDEC-standard test board.
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DS21348/DS21Q348 11. AC CHARACTERISTICS Table 11-1. AC Characteristics—Multiplexed Parallel Port (BIS1 = 0, BIS0 = 0) (VDD = 3.3V ± 5%, TA = -40°C to +85°C.) (See Figure 11-1, Figure 11-2, and Figure 11-3.
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DS21348/DS21Q348 Figure 11-1. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 0) t CYC ALE WR PWASH t ASD t ASD RD PWEL t ASED PWEH t CH t CS CS t ASL AD0-AD7 t DHR t DDR t AHL Figure 11-2.
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DS21348/DS21Q348 Figure 11-3.
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DS21348/DS21Q348 Table 11-2. AC Characteristics—Nonmultiplexed Parallel Port (BIS1 = 0, BIS0 = 1) (VDD = 3.3V ± 5%, TA = -40°C to +85°C.) (See Figure 11-4, Figure 11-5, Figure 11-6, and Figure 11-7.
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DS21348/DS21Q348 Figure 11-4. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 1) Address Valid A0 to A4 D0 to D7 Data Valid t5 5ns min/20ns max WR CS t1 0ns min. 0ns min. t2 RD t3 75ns max. t4 0ns min. Figure 11-5. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 1) Address Valid A0 to A4 D0 to D7 t7 RD t1 CS 0ns min. WR 10ns min. t8 10ns min. 0ns min. t2 t6 75ns min. 68 of 76 t4 0ns min.
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DS21348/DS21Q348 Figure 11-6. Motorola Bus Read Timing (PBTS = 1, BIS1 = 0, BIS0 = 1) Address Valid A0 to A4 Data Valid D0 to D7 5ns min. / 20ns max. R/W t1 CS t5 0ns min. 0ns min. t2 t3 t4 0ns min. 75ns max. DS Figure 11-7. Motorola Bus Write Timing (PBTS = 1, BIS1 = 0, BIS0 = 1) Address Valid A0 to A4 D0 to D7 10ns min. R/W t1 CS 0ns min. DS t7 t8 10ns min. 0ns min. t2 t6 75ns min. 69 of 76 t4 0ns min.
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DS21348/DS21Q348 Table 11-3. AC Characteristics—Serial Port (BIS1 = 1, BIS0 = 0) (VDD = 3.3V ± 5%, TA = -40°C to +85°C.) (See Figure 11-8.
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DS21348/DS21Q348 Table 11-4. AC Characteristics—Receive Side (VDD = 3.3V ± 5%, TA = -40°C to +85°C.) (See Figure 11-9.) PARAMETER SYMBOL MIN TYP RCLK Period tCP RCLK Pulse Width RCLK Pulse Width Delay RCLK to RPOS, RNEG, PBEO, RBPV Valid MAX UNITS NOTES 488 ns 1 648 ns 2 tCH 200 ns 3 tCL tCH 200 150 ns ns 3 4 tCL 150 ns 4 tDD 50 ns NOTES: 1) E1 mode. 2) T1 or J1 mode. 3) Jitter attenuator enabled in the receive path. 4) Jitter attenuator disabled or enabled in the transmit path.
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DS21348/DS21Q348 Table 11-5. AC Characteristics—Transmit Side (VDD = 3.3V ± 5%, TA = -40°C to +85°C.) (Figure 11-10) PARAMETER SYMBOL MIN TCLK Period tCP TCLK Pulse Width tCH tCL 75 75 UNITS ns ns ns ns TPOS/TNEG Setup to TCLK Falling or Rising tSU 20 ns TPOS/TNEG Hold from TCLK Falling or Rising tHD 20 ns TCLK Rise and Fall Times TYP 488 648 MAX tR, tF 25 NOTES: 1) E1 mode. 2) T1 or J1 mode. Figure 11-10.
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DS21348/DS21Q348 12. PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 12.1 44-Pin TQFP (56-G4012-001) SUGGESTED PAD LAYOUT 44 PIN TQFP, 10*10*1.
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DS21348/DS21Q348 12.
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DS21348/DS21Q348 12.3 144-Ball CSBGA (17mm x 17mm) (56-G6011-001) A1 CORNER 3 A1 CORNER 12 11 10 9 8 7 6 5 17.00 13.97 0.20 1.52 17.00 4X 1.27 X 13.97 1.52 DETAIL A 0.05 2.6 0 1.99 0.76 Z DETAIL B 75 of 76 3 2 1 A B C D E F G H I J K L 1.27 Y 4 0.6 0.
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DS21348/DS21Q348 SOLDER BALL φ 0.76 REF φ 0.76 L X φ 0.76 L Z Y Z 0.05 LABEL THICKNESS // 0.24 Z 2.60 REF 0.17 // Z 0.10 SEATING PLANE 2 0.76 REF Z 76 of 76 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.