3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers www.maxim-ic.com FEATURES § § § § § § § § § § § § § § § § Complete DS1/ISDN–PRI/J1 transceiver functionality Long and Short haul LIU Crystal–less jitter attenuator Generates DSX–1 and CSU line build-outs HDLC controller with 64-byte buffers Configurable for FDL or DS0 operation Dual two–frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192MHz 8.
DS21352/DS21552 TABLE OF CONTENTS 1. 2. 3. 4. 5. 6. 7. 8. 9. LIST OF FIGURES .........................................................................................................................5 LIST OF TABLES ...........................................................................................................................6 INTRODUCTION............................................................................................................................7 3.1 FUNCTIONAL DESCRIPTION..
DS21352/DS21552 10. 11. 12. 13. 14. 15. SIGNALING OPERATION..........................................................................................................58 10.1 PROCESSOR-BASED SIGNALING ....................................................................................58 10.2 HARDWARD-BASED SIGNALING ...................................................................................60 10.2.1 Receive Side......................................................................................
DS21352/DS21552 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. LINE INTERFACE FUNCTION .................................................................................................85 16.1 RECEIVE CLOCK AND DATA RECOVERY ....................................................................85 16.2 TRANSMIT WAVE SHAPING AND LINE DRIVING.......................................................86 16.3 JITTER ATTNUATOR.................................................................................................
DS21352/DS21552 1. LIST OF FIGURES Figure 3-1 SCT BLOCK DIAGRAM.........................................................................................................9 Figure 16-1 EXTERNAL ANALOG CONNECTIONS ..........................................................................87 Figure 16-2 OPTIONAL CRYSTAL CONNECTIONS ..........................................................................88 Figure 16-3 TRANSMIT WAVEFORM TEMPLANE....................................................................
DS21352/DS21552 2. LIST OF TABLES Table 4-1 PIN DESCRIPTION SORTED BY PIN NUMBER................................................................11 Table 4-2 PIN DESCRIPTION SORTED BY PIN SYMBOL ................................................................14 Table 5-1 REGISTER MAP SORTED BY ADDRESS...........................................................................29 Table 6-1 DEVICE ID BIT MAP ........................................................................................................
DS21352/DS21552 3. INTRODUCTION The DS21352/552 are 3.3V/5V superset versions of the popular DS2152 T1 single-chip transceiver offering the new features listed below. All of the original features of the DS2152 have been retained and software created for the original devices is transferable into the DS21352/552. NEW FEATURES (after the DS2152) § § § § Interleaving PCM Bus Operation Integral HDLC controller with 64-byte buffers Configurable for FDL or DS0 operation IEEE 1149.
DS21352/DS21552 3.1 FUNCTIONAL DESCRIPTION The analog AMI/B8ZS waveform off of the T1 line is transformer coupled into the RRING and RTIP pins of the DS21352/552. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive side framer where the digital serial stream is analyzed to locate the framing/multi-frame pattern.
of 137 TTIP Local Loopback JTAG PORT Receive Line I/F Clock / Data Recovery TRING RTIP RRING MCLK VCO / PLL XTALD 12.352 MHz 8XCLK 24.7MHz MUX RPOSI RCLKI RNEGI RNEGO RCLKO RPOSO MUX LIUC FDL Transmit Line I/F Framer Loopback Jitter Attenuator Either transmit or receive path 7 8 HDLC/BOC Controller FDL / DS0 LOTC MUX Elastic Store Sync Control Elastic Store Timing Control RSYSCLK Interleave Bus Interleave Bus 8.
DS21352/DS21552 3.2 DOCUMENT REVISION HISTORY Revision 12-10-98 12-18-98 1-4-99 1-18-99 1-18-99 1-28-99 2-2-99 2-11-99 4-1-99 4-15-99 5-7-99 5-17-99 5-19-99 7-27-99 8-16-99 Notes Initial Release Add LIUODO (LIU Open Drain Output) to CCR7.0 Add CDIG (Customer Disconnect Indication Generator) to CCR7.1 Add LIUSI (Line Interface Unit Synchronization Interface) to CCR7.2 Correct IBO register bit functions order Add bit level description to CCR3.
DS21352/DS21552 4.
DS21352/DS21552 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 TDATA TSYSCLK TSSYNC TCHCLK CO MUX D0/AD0 D1/AD1 D2/AD2 D3/AD3 DVSS DVDD D4/AD4 D5/AD5 D6/AD6 D7/AD7 A0 A1 A2 A3 A4 A5 A6 ALE (AS)/A7 RD*(DS*) CS* FMS WR*(R/W*) RLINK RLCLK DVSS DVDD RCLK DVDD DVSS RDATA RPOSI RNEGI RCLKI I I I O O I I/O I/O I/O I/O – I/O I/O I/O I/O I I I I I I I I I I I I O O – – O – – O I I I Transmit Data Transmit System Clock Transmit System Sync Trans
DS21352/DS21552 Table 4-1 PIN DESCRIPTION SORTED BY PIN SYMBOL PIN 3 13 66 67 68 69 70 71 72 73 11 36 54 75 56 57 58 59 62 63 64 65 44 81 45 60 80 84 76 61 83 25 4 7 10 2 5 12 21 55 8 9 15 23 26 SYMBOL 8MCLK 8XCLK A0 A1 A2 A3 A4 A5 A6 ALE (AS)/A7 BTS CI CO CS* D0/AD0 D1/AD1 D2/AD2 D3/AD3 D4/AD4 D5/AD5 D6/AD6 D7/AD7 DVDD DVDD DVSS DVSS DVSS DVSS FMS DVDD DVDD INT* JTCLK JTDI JTDO JTMS JTRST LIUC MCLK MUX NC NC NC NC NC TYPE O O I I I I I I I I I I O I I/O I/O I/O I/O I/O I/O I/O I/O – – – – – – I – O I I
DS21352/DS21552 88 89 74 85 97 79 78 99 96 87 90 86 91 17 95 94 93 98 100 16 18 19 20 24 33 53 46 40 41 50 49 14 34 35 39 42 38 43 32 RCLKI RCLKO RD*(DS*) RDATA RFSYNC RLCLK RLINK RLOS/LOTC RMSYNC RNEGI RNEGO RPOSI RPOSO RRING RSER RSIG RSIGF RSYNC RSYSCLK RTIP RVDD RVSS RVSS RVSS TCHBLK TCHCLK TCLK TCLKI TCLKO TDATA TESO TEST TLCLK TLINK TNEGI TNEGO TPOSI TPOSO TRING I O I O O O O O O I O I O I O O O I/O I I – – – – O O I I O I O I O I I O I O O Receive Clock Input Receive Clock Output Read Input(Data S
DS21352/DS21552 4. PIN FUNCTION DESCRIPTION 4.1.1 TRANSMIT SIDE PINS Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 1.544 MHz primary clock. Used to clock data through the transmit side formatter. Signal Name: TSER Signal Description: Transmit Serial Data Signal Type: Input Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is disabled. Sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled.
DS21352/DS21552 4.1.1 TRANSMIT SIDE PINS (cont.) Signal Name: TLINK Signal Description: Transmit Link Data Signal Type: Input If enabled via TCR1.2, this pin will be sampled on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs–bit position (D4) or the Z–bit position (ZBTSI). See Section 15 for details.
DS21352/DS21552 4.1.1 TRANSMIT SIDE PINS (cont.) Signal Name: TNEGO Signal Description: Transmit Negative Data Output Signal Type: Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit side formatter. This pin is normally tied to TNEGI. Signal Name: TCLKO Signal Description: Transmit Clock Output Signal Type: Output Buffered clock that is used to clock data through the transmit side formatter (i.e., either TCLK or RCLKI). This pin is normally tied to TCLKI.
DS21352/DS21552 4.1.2 RECEIVE SIDE PINS Signal Name: RLINK Signal Description: Receive Link Data Signal Type: Output Updated with either FDL data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK before the start of a frame. See Section 20 for details. Signal Name: RLCLK Signal Description: Receive Link Clock Signal Type: Output A 4 kHz or 2 kHz (ZBTSI) clock for the RLINK output. Signal Name: RCLK Signal Description: Receive Clock Signal Type: Output 1.
DS21352/DS21552 4.1.2 RECEIVE SIDE PINS (cont.) Signal Name: RFSYNC Signal Description: Receive Frame Sync Signal Type: Output An extracted 8 kHz pulse, one RCLK wide, is output at this pin which identifies frame boundaries. Signal Name: RMSYNC Signal Description: Receive Multiframe Sync Signal Type: Output Only used when the receive side elastic store is enabled. An extracted pulse, one RSYSCLK wide, is output at this pin which identifies multiframe boundaries.
DS21352/DS21552 Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied to RPOSI. Signal Name: RNEGO Signal Description: Receive Negative Data Input Signal Type: Output Updated on the rising edge of RCLKO with the bipolar data out of the line interface. This pin is normally tied to RPOSI. Signal Name: RCLKO Signal Description: Receive Clock Output Signal Type: Output Buffered recovered clock from the T1 line. This pin is normally tied to RCLKI.
DS21352/DS21552 4.1.3 PARALLEL CONTROL PORT PINS Signal Name: INT* Signal Description: Interrupt Signal Type: Output Flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2 and the HDLC Status Register. Active low, open drain output Signal Name: FMS Signal Description: Framer Mode Select Signal Type: Input Selects the DS2152 mode when high or the DS21352/552 mode when low. If high, the JTRST is internally pulled low.
DS21352/DS21552 4.1.3 PARALLEL CONTROL PORT PINS (cont.) Signal Name: CS* Signal Description: Chip Select Signal Type: Input Must be low to read or write to the device. CS* is an active low signal. Signal Name: ALE(AS)/A7 Signal Description: Address Latch Enable(Address Strobe) or A7 Signal Type: Input In non–multiplexed bus operation (MUX = 0), serves as the upper address bit. In multiplexed bus operation (MUX = 1), serves to de-multiplex the bus on a positive–going edge.
DS21352/DS21552 4.1.4 JTAG TEST ACCESS PORT PINS Signal Name: JTRST Signal Description: IEEE 1149.1 Test Reset Signal Type: Input If FMS = 1: JTAG functionality is not available and JTRST is held LOW internally. If FMS = 0: JTAG functionality is available and JTRST is pulled up internally by a 10kΩ resistor. If FMS = 0 and boundary scan is not used, this pin should be held low. This signal is used to asynchronously reset the test access port controller.
DS21352/DS21552 4.1.6 LINE INTERFACE PINS Signal Name: MCLK Signal Description: Master Clock Input Signal Type: Input A 1.544 MHz (50 ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and for jitter attenuation. A quartz crystal of 1.544 MHz may be applied across MCLK and XTALD instead of the TTL level clock source. Signal Name: XTALD Signal Description: Quartz Crystal Driver Signal Type: Output A quartz crystal of 1.
DS21352/DS21552 4.1.7 SUPPLY PINS Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 5.0 volts +/-5% (DS21552) or 3.3 volts +/-5% (DS21352). Should be tied to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal Type: Supply 5.0 volts +/-5% (DS21552) or 3.3 volts +/-5% (DS21352). Should be tied to the DVDD and TVDD pins. Signal Name: TVDD Signal Description: Transmit Analog Positive Supply Signal Type: Supply 5.
DS21352/DS21552 5. PARALLEL PORT The SCT is controlled via either a non–multiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The SCT can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C. Electrical Characteristics in Section 24 for more details.
ADDRESS R/W 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W REGISTER NAME Multiframe Out of Sync Count 2 Receive FDL Register Receive FDL Match 1 Receive FDL Match 2 Receive Control 1 Receive Control 2 Receive Mark 1 Receive Mark 2 Receive Mark 3 Common Control 3 Receive Information 2 Transmit
DS21352/DS21552 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Receive Channel 19 Receive Channel 20 Receive Channel 21 Receive Channel 22 Receive Channel 23 Receive Channel 24 Receive Signaling 1 Receive Signaling 2 Receive Signaling 3 Receive Signaling 4 Receive Signaling 5 Receive Signaling 6 Receive Signaling 7 Receive Signaling 8 Receive Signaling 9 Receive
8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F R/W R/W R/W R/W R/W R/W R/W R/W - DS21352/DS21552 RC16 RDC1 RDC2 TDC1 TDC2 IBO TEST3 (set to 00h) TEST4 (set to 00h) - Receive Channel 16 Receive HDLC DS0 Control Register 1 Receive HDLC DS0 Control Register 2 Transmit HDLC DS0 Control Register 1 Transmit HDLC DS0 Control Register 2 Interleave Bus Operation Register Test 3 SEE NOTE 1 Test 4 SEE NOTE 1 not present not present not present not present not present not present not present not present not pres
DS21352/DS21552 Bit 6 IDR.6 0=T1 chip 1=E1 chip Bit 6. Bit 5 IDR.5 Bit 5. Bit 4 IDR.4 Bit 4. ID3 ID2 IDR.3 IDR.1 Chip Revision Bit 3. MSB of a decimal code that represents the chip revision. Chip Revision Bit 2. ID1 IDR.2 Chip Revision Bit 1.
DS21352/DS21552 Table 6-1 DEVICE ID BIT MAP SCT DS2152 DS21352 DS21552 DS2154 DS21354 DS21554 T1/E1 0 0 0 1 1 1 Bit 6 0 0 0 0 0 0 Bit 5 0 0 1 0 0 1 Bit 4 0 1 0 0 1 0 The lower four bits of the IDR are used to display the die revision of the chip. RCR1: RECEIVE CONTROL REGISTER 1 (Address=2B Hex) (MSB) LCVCRF ARC OOF1 OOF2 SYNCC SYMBOL POSITION NAME AND DESCRIPTION LCVCRF RCR1.7 ARC RCR1.6 OOF1 RCR1.5 OOF2 RCR1.4 SYNCC RCR1.3 SYNCT RCR1.2 SYNCE RCR1.1 RESYNC RCR1.
DS21352/DS21552 RCR2: RECEIVE CONTROL REGISTER 2 (Address=2C Hex) (MSB) RCS RZBTSI SYMBOL POSITION RCS RCR2.7 RZBTSI RCR2.6 RSDW RCR2.5 RSM RCR2.4 RSIO RCR2.3 RD4YM RCR2.2 FSBE RCR2.1 MOSCRF RCR2.0 RSDW RSM RSIO RD4YM FSBE (LSB) MOSCRF NAME AND DESCRIPTION Receive Code Select. 0 = idle code (7F Hex) 1 = digital milliwatt code (1E/0B/0B/1E/9E/8B/8B/9E Hex) Receive Side ZBTSI Support Enable. Allows ZBTSI information to be output on RLINK pin.
DS21352/DS21552 TCR1: TRANSMIT CONTROL REGISTER 1 (Address=35 Hex) (MSB) LOTCMC TFPT TCPT TSSE GB7S SYMBOL POSITION NAME AND DESCRIPTION LOTCMC TCR1.7 TFPT TCR1.6 TCPT TCR1.5 TSSE TCR1.4 GB7S TCR1.3 TFDLS TCR1.2 TBL TCR1.1 TYEL TCR1.0 TFDLS TBL (LSB) TYEL Loss Of Transmit Clock Mux Control. Determines whether the transmit side formatter should switch to RCLK if the TCLK input should fail to transition.
DS21352/DS21552 TCR2: TRANSMIT CONTROL REGISTER 2 (Address=36 Hex) (MSB) TEST1 TEST0 TZBTSI TSDW TSM TSIO TD4YM (LSB) TB7ZS SYMBOL POSITION NAME AND DESCRIPTION TEST1 TCR2.7 Test Mode Bit 1 for Output Pins. See Table 6-2.. TEST0 TCR2.6 Test Mode Bit 0 for Output Pins. See Table 6-2. TZBTSI TCR2.5 TSDW TCR2.4 TSM TCR2.3 TSIO TCR2.2 TD4YM TCR2.1 TB7ZS TCR2.0 Transmit Side ZBTSI Support Enable. Allows ZBTSI information to be input on TLINK pin.
DS21352/DS21552 CCR1: COMMON CONTROL REGISTER 1 (Address=37 Hex) (MSB) TESE ODF RSAO TSCLKM RSCLKM SYMBOL POSITION NAME AND DESCRIPTION TESE CCR1.7 ODF CCR1.6 Transmit Elastic Store Enable. 0 = elastic store is bypassed 1 = elastic store is enabled Output Data Format. RESE PLB (LSB) FLB 0 = bipolar data at TPOSO and TNEGO RSAO CCR1.5 1 = NRZ data at TPOSO; TNEGO = 0 Receive Signaling All One’s. This bit should not be enabled if hardware signaling is being utilized.
DS21352/DS21552 3. All receive side signals will take on timing synchronous with TCLK instead of RCLKI. Please note that it is not acceptable to have RCLK tied to TCLK during this loopback because this will cause an unstable condition. CCR2: COMMON CONTROL REGISTER 2 (Address=38 Hex) (MSB) TFM TB8ZS SYMBOL POSITION TFM CCR2.7 TB8ZS CCR2.6 TSLC96 CCR2.5 TFDL CCR2.4 RFM CCR2.3 RB8ZS CCR2.2 RSLC96 CCR2.1 RZSE CCR2.
RSMS CCR3.4 PDE CCR3.3 ECUS CCR3.2 TLOOP CCR3.1 TESMDM CCR3.0 DS21352/DS21552 1 = Loss of Transmit Clock (LOTC) RSYNC Multiframe Skip Control. Useful in framing format conversions from D4 to ESF. This function is not available when the receive side elastic store is enabled. 0 = RSYNC will output a pulse at every multiframe 1 = RSYNC will output a pulse at every other multiframe note: for this bit to have any affect, the RSYNC must be set to output multiframe pulses (RCR2.4=1 and RCR2.3=0).
DS21352/DS21552 6.5 PULSE DENSITY ENFORCER The Framer always examines both the transmit and receive data streams for violations of the following rules which are required by ANSI T1.403: – no more than 15 consecutive zeros – at least N ones in each and every time window of 8 x (N +1) bits where N = 1 through 23 Violations for the transmit and receive data streams are reported in the RIR2.0 and RIR2.1 bits respectively. When the CCR3.
DS21352/DS21552 CCR4: COMMON CONTROL REGISTER 4 (Address=11 Hex) (MSB) RSRE RPCSI SYMBOL POSITION RSRE CCR4.7 RPCSI CCR4.6 RFSA1 CCR4.5 RFE CCR4.4 RFF CCR4.3 THSE CCR4.2 TPCSI CCR4.1 TIRFS CCR4.0 RFSA1 RFE RFF THSE TPCSI (LSB) TIRFS NAME AND DESCRIPTION Receive Side Signaling Re–Insertion Enable. See Section 10.2 for details.
DS21352/DS21552 CCR5: COMMON CONTROL REGISTER 5 (Address=19 Hex) (MSB) TJC TCM4 TCM3 LIAIS SYMBOL POSITION NAME AND DESCRIPTION TJC CCR5.7 LLB CCR5.6 LIAIS CCR5.5 TCM4 CCR5.4 TCM3 CCR5.3 Transmit Japanese CRC6 Enable. 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT–G704 CRC6 calculation Local Loopback. 0 = loopback disabled 1 = loopback enabled Line Interface AIS Generation Enable.
DS21352/DS21552 CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex) (MSB) RJC RCM4 RCM3 TESA SYMBOL POSITION NAME AND DESCRIPTION RJC CCR6.7 RESA CCR6.6 TESA CCR6.5 RCM4 CCR6.4 RCM3 CCR6.3 Receive Japanese CRC6 Enable. 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT–G704 CRC6 calculation Receive Elastic Store Align. Setting this bit from a zero to a one will force the receive elastic store’s write/read pointers to a minimum separation of half a frame.
DS21352/DS21552 CCR7: COMMON CONTROL REGISTER 7 (Address=0A Hex) (MSB) LIRST RLB SYMBOL LIRST POSITION CCR7.7 RLB CCR7.6 RESR CCR7.5 TESR CCR7.4 - CCR7.3 LIUSI CCR7.2 CDIG CCR7.1 LIUODO CCR7.0 RESR TESR – LIUSI CDIG (LSB) LIUODO NAME AND DESCRIPTION Line Interface Reset. Setting this bit from a zero to a one will initiate an internal reset that affects the clock recovery state machine and jitter attenuator. Normally this bit is only toggled on power–up.
DS21352/DS21552 7. STATUS AND INFORMATION REGISTERS There is a set of nine registers that contain information on the current real time status of the device, Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Registers 1 to 3 (RIR1/RIR2/RIR3) and a set of four registers for the onboard HDLC and BOC controller. The specific details on the four registers pertaining to the HDLC controller are covered in Section 15.3.
DS21352/DS21552 RIR1: RECEIVE INFORMATION REGISTER 1 (Address=22 Hex) (MSB) COFA 8ZD 16ZD RESF RESE SYMBOL POSITION NAME AND DESCRIPTION COFA RIR1.7 8ZD RIR1.6 16ZD RIR1.5 RESF RIR1.4 RESE RIR1.3 SEFE RIR1.2 B8ZS RIR1.1 FBE RIR1.0 SEFE (LSB) FBE B8ZS Change of Frame Alignment. Set when the last resync resulted in a change of frame or multiframe alignment. Eight Zero Detect.
LORC RIR3.4 FRCL RIR3.3 – RIR3.2 DS21352/DS21552 bits of its limit; useful for debugging jitter attenuation operation. Loss of Receive Clock. Set when the RCLKI pin has not transitioned for at least 2 us (4 ms max). Framer Receive Carrier Loss. Set when 192 consecutive zeros have been received at the RPOSI and RNEGI pins; allowed to be cleared when 14 or more ones out of 112 possible bit positions are received. Not Assigned. Could be any value when read. – RIR3.1 Not Assigned.
DS21352/DS21552 SR1: STATUS REGISTER 1 (Address=20 Hex) (MSB) LUP LDN LOTC SYMBOL POSITION LUP SR1.7 LDN SR1.6 LOTC SR1.5 RSLIP SR1.4 RBL SR1.3 RYEL LRCL SR1.2 SR1.1 RLOS SR1.0 RSLIP RBL RYEL LRCL (LSB) RLOS NAME AND DESCRIPTION Loop Up Code Detected. Set when the loop up code as defined in the RUPCD register is being received. See Section 16.5 for details. Loop Down Code Detected. Set when the loop down code as defined in the RDNCD register is being received. See Section 16.
DS21352/DS21552 Table 7-2 ALARM CRITERIA ALARM Blue Alarm (AIS) (see note 1 below) Yellow Alarm (RAI) 1. D4 bit 2 mode(RCR2.2=0) SET CRITERIA when over a 3 ms window, 5 or less zeros are received when bit 2 of 256 consecutive channels is set to zero for at least 254 occurrences 2. D4 12th F–bit mode (RCR2.2=1; this mode is also referred to as the “Japanese Yellow Alarm”) when the 12th framing bit is set to one for two consecutive occurrences 3.
DS21352/DS21552 SR2: STATUS REGISTER 2 (Address=21 Hex) (MSB) RMF RFDL TFDL SEC SYMBOL POSITION NAME AND DESCRIPTION RMF SR2.7 Receive Multiframe. Set on receive multiframe boundaries. TMF SR2.6 Transmit Multiframe. Set on transmit multiframe boundaries. SEC SR2.5 RFDL SR2.4 TFDL RMTCH SR2.3 SR2.2 RAF RSC SR2.1 SR2.0 One Second Timer. Set on increments of one second based on RCLK; will be set in increments of 999 ms, 999 ms, and 1002 ms every 3 seconds. Receive FDL Buffer Full.
DS21352/DS21552 IMR1: INTERRUPT MASK REGISTER 1 (Address=7F Hex) (MSB) LUP LDN LOTC SLIP RBL SYMBOL POSITION NAME AND DESCRIPTION LUP IMR1.7 LDN IMR1.6 LOTC IMR1.5 SLIP IMR1.4 RBL IMR1.3 RYEL IMR1.2 Loop Up Code Detected. 0 = interrupt masked 1 = interrupt enabled Loop Down Code Detected. 0 = interrupt masked 1 = interrupt enabled Loss of Transmit Clock. 0 = interrupt masked 1 = interrupt enabled Elastic Store Slip Occurrence.
DS21352/DS21552 IMR2: INTERRUPT MASK REGISTER 2 (Address=6F Hex) (MSB) RMF TMF SEC RFDL TFDL SYMBOL POSITION NAME AND DESCRIPTION RMF IMR2.7 TMF IMR2.6 SEC IMR2.5 RFDL IMR2.4 TFDL IMR2.3 RMTCH IMR2.2 RAF IMR2.1 RSC IMR2.0 RMTCH RAF (LSB) RSC Receive Multiframe. 0 = interrupt masked 1 = interrupt enabled Transmit Multiframe. 0 = interrupt masked 1 = interrupt enabled One Second Timer. 0 = interrupt masked 1 = interrupt enabled Receive FDL Buffer Full.
DS21352/DS21552 8.1 LINE CODE VIOLATION COUNT REGISTER (LCVCR) Line Code Violation Count Register 1 (LCVCR1) is the most significant word and LCVCR2 is the least significant word of a 16–bit counter that records code violations (CVs). CVs are defined as Bipolar Violations (BPVs) or excessive zeros. See Table 8-1 for details of exactly what the LCVCRs count. If the B8ZS mode is set for the receive side via CCR2.2, then B8ZS code words are not counted.
DS21352/DS21552 8.2 PATH CODE VIOLATION COUNT REGISTER (PCVCR) When the receive side of a framer is set to operate in the ESF framing mode (CCR2.3=1), PCVCR will automatically be set as a 12–bit counter that will record errors in the CRC6 code words. When set to operate in the D4 framing mode (CCR2.3=0), PCVCR will automatically count errors in the Ft framing bit position. Via the RCR2.1 bit, a framer can be programmed to also report errors in the Fs framing bit position.
DS21352/DS21552 8.3 Multiframes Out Of Sync Count Register (MOSCR) Normally the MOSCR is used to count the number of multiframes that the receive synchronizer is out of sync (RCR2.0=1). This number is useful in ESF applications needing to measure the parameters Loss Of Frame Count (LOFC) and ESF Error Events as described in AT&T publication TR54016. When the MOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOS=1) conditions.
DS21352/DS21552 9. DS0 MONITORING FUNCTION The device has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR5 register. In the receive direction, the RCM0 to RCM4 bits in the CCR6 register need to be properly set.
DS21352/DS21552 TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address=1A Hex) (MSB) B1 B2 B3 B4 B5 B6 B7 (LSB) B8 SYMBOL POSITION NAME AND DESCRIPTION B1 B2 TDS0M.7 TDS0M.6 Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be transmitted). Transmit DS0 Channel Bit 2. B3 TDS0M.5 Transmit DS0 Channel Bit 3. B4 TDS0M.4 Transmit DS0 Channel Bit 4. B5 TDS0M.3 Transmit DS0 Channel Bit 5. B6 TDS0M.2 Transmit DS0 Channel Bit 6. B7 TDS0M.1 Transmit DS0 Channel Bit 7. B8 TDS0M.
DS21352/DS21552 B5 RDS0M.3 Receive DS0 Channel Bit 5. B6 RDS0M.2 Receive DS0 Channel Bit 6. B7 RDS0M.1 Receive DS0 Channel Bit 7. B8 RDS0M.0 Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit to be received). 10. SIGNALING OPERATION Processor based (i.e., software based) signaling access and hardware based access are available. Processor based access and hardware based access can be used simultaneously if necessary.
DS21352/DS21552 RS1 TO RS12: RECEIVE SIGNALING REGISTERS (Address=60 to 6B Hex) (MSB) A(8) A(16) A(24) B(8) B(16) B(24) A/C(8) A/C(16) A/C(24) B/D(8) B/D(16) B/D(24) A(7) A(15) A(23) B(7) B(15) B(23) A/C(7) A/C(15) A/C(23) B/D(7) B/D(15) B/D(23) A(6) A(14) A(22) B(6) B(14) B(22) A/C(6) A/C(14) A/C(22) B/D(6) B/D(14) B/D(22) A(5) A(13) A(21) B(5) B(13) B(21) A/C(5) A/C(13) A/C(21) B/D(5) B/D(13) B/D(21) A(4) A(12) A(20) B(4) B(12) B(20) A/C(4) A/C(12) A/C(20) B/D(4) B/D(12) B/D(20) SYMBOL POSITION NA
DS21352/DS21552 TS1 TO TS12: TRANSMIT SIGNALING REGISTERS (Address=70 to 7B Hex) (MSB) A(8) A(16) A(24) B(8) B(16) B(24) A/C(8) A/C(16) A/C(24) B/D(8) B/D(16) B/D(24) A(7) A(15) A(23) B(7) B(15) B(23) A/C(7) A/C(15) A/C(23) B/D(7) B/D(15) B/D(23) A(6) A(14) A(22) B(6) B(14) B(22) A/C(6) A/C(14) A/C(22) B/D(6) B/D(14) B/D(22) A(5) A(13) A(21) B(5) B(13) B(21) A/C(5) A/C(13) A/C(21) B/D(5) B/D(13) B/D(21) A(4) A(12) A(20) B(4) B(12) B(20) A/C(4) A/C(12) A/C(20) B/D(4) B/D(12) B/D(20) SYMBOL POSITION N
DS21352/DS21552 multiframe boundary. In this mode, the elastic store must be enabled however the backplane clock can be either 1.544 MHz or 2.048 MHz. If the signaling re–insertion mode is enabled, the user can control which channels have signaling re– insertion performed on a channel–by–channel basis by setting the RPCSI control bit high (CCR4.6) and then programming the RCHBLK output pin to go high in the channels in which the signaling re–insertion should not occur.
DS21352/DS21552 11.1 TRANSMIT SIDE CODE GENERATION In the transmit direction there are two methods by which channel data from the backplane can be overwritten with data generated by the framer. The first method which is covered in Section 11.1 was a feature contained in the original DS2151 while the second method which is covered in Section 11.2 is a new feature of the DS2152/352/552. 11.1.
DS21352/DS21552 TC1 TO TC24: TRANSMIT CHANNEL REGISTERS (Address=50 to 57 and 40 to 4F Hex) (for brevity, only channel one is shown; see Table 5-1 for other register address) (MSB) C7 C6 C5 C4 C3 C2 C1 SYMBOL POSITION C7 TC1.7 MSB of the Code (this bit is transmitted first) C0 TC1.
DS21352/DS21552 11.2.1 FIXED PER-CHANNEL IDLE CODE INSERTION The first method on the receive side involves using the Receive Mark Registers (RMR1/2/3) to determine which of the 24 T1 channels should be overwritten with either a 7Fh idle code or with a digital milliwatt pattern. The RCR2.7 bit will determine which code is used. The digital milliwatt code is an eight byte repeating pattern that represents a 1 kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the RMRs, represents a particular channel.
DS21352/DS21552 RCC1/RCC2/RCC3: RECEIVE CHANNEL CONTROL REGISTER (ADDRESS=1B TO 1D Hex) (MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 SYMBOL CH24 POSITION RCC3.7 CH1 RCC1.
DS21352/DS21552 0 = force the TCHBLK pin to remain low during this channel time 1 = force the TCHBLK pin high during this channel time 14. ELASTIC STORES OPERATION The device contains dual two–frame (386 bits) elastic stores, one for the receive direction, and one for the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert the T1 data stream to 2.048 Mbps (or a multiple of 2.048 Mbps) which is the E1 rate.
DS21352/DS21552 14.2 TRANSMIT SIDE The operation of the transmit elastic store is very similar to the receive side. The transmit side elastic store is enabled via CCR1.7. A 1.544 MHz (CCR1.4=0) or 2.048 MHz (CCR1.4=1) clock can be applied to the TSYSCLK input. If the user selects to apply a 2.048 MHz clock to the TSYSCLK pin, then the data input at TSER will be ignored every fourth channel. Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be ignored.
DS21352/DS21552 TBOC.6 = 1 and TDC1.7 = 1 cannot exist without corrupting the data in the FDL. See Table 15-1 for configuring the transmit HDLC controller. Table 15-1 TRANSMIT HDLC CONFIGURATION Function DS0(s) FDL Disable TBOC.6 0 1 0 TDC1.7 1 0 0 TCR1.2 1 or 0 1 1 or 0 Note that the BOC controller is functional when the HDLC controller is used for DS0s. Section 15.3 contains all of the HDLC and BOC registers and information on FDL/Fs Extraction and Insertion with and without the HDLC controller.
DS21352/DS21552 Firmware, which can be retrieved from the Web site (www.dalsemi.com/Prod_info /Telecom/t1_e1_tools.html), was developed to implement the FDL. The code for the DS2151 incorporates the LAPD protocol and can be used with any of the 51/52/352/552 SCTs. The code for the DS2152 can be used with the 52/352/552 SCTs. 15.3 HDLC AND BOC CONTROLLER FOR THE FDL 15.3.
DS21352/DS21552 Table 15-2 HDLC/BOC CONTROLLER REGISTERS NAME HDLC Control Register (HCR) HDLC Status Register (HSR) HDLC Interrupt Mask Register (HIMR) Receive HDLC Register (RHIR) Receive BOC Register (RBOC) Receive HDLC FIFO Register (RHFR) Receive HDLC DS0 Control Register 1 (RDC1) Receive HDLC DS0 Control Register 2 (RDC2) Transmit HDLC Register (THIR) Transmit BOC Register (TBOC) Transmit HDLC FIFO Register (THFR) Transmit HDLC DS0 Control Register 1 (TDC1) Transmit HDLC DS0 Control Register 2 (TDC2)
DS21352/DS21552 Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware interrupt via the INT* output pin. Each of the events in the HSR can be either masked or unmasked from the interrupt pin via the HDLC Interrupt Mask Register (HIMR). Interrupts will force the INT* pin low when the event occurs. The INT pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur. 15.3.
DS21352/DS21552 15.3.3.2 TRANSMIT AN HDLC MESSAGE 1) Make sure HDLC controller is done sending any previous messages and is current sending flags by checking that the FIFO is empty by reading the TEMPTY status bit in the TPRM register. 2) Enable either the THALF or TNF interrupt. 3) Read THIR to obtain TFULL status.
RPE HSR.6 RPS HSR.5 RHALF HSR.4 RNE HSR.3 THALF HSR.2 TNF HSR.1 TMEND HSR.0 DS21352/DS21552 Receive Packet End. Set when the HDLC controller detects either the finish of a valid message (i.e., CRC check complete) or when the controller has experienced a message fault such as a CRC checking error, or an overrun condition, or an abort has been seen. The setting of this bit prompts the user to read the RPRM register for details. Receive Packet Start.
DS21352/DS21552 HIMR: HDLC INTERRUPT MASK REGISTER (Address=02 Hex) (MSB) RBOC RPE RPS RHALF RNE SYMBOL POSITION NAME AND DESCRIPTION RBOC HIMR.7 RPE HIMR.6 RPS HIMR.5 RHALF HIMR.4 RNE HIMR.3 THALF HIMR.2 TNF HIMR.1 TMEND FIMR.0 Receive BOC Detector Change of State. 0 = interrupt masked 1 = interrupt enabled Receive Packet End. 0 = interrupt masked 1 = interrupt enabled Receive Packet Start. 0 = interrupt masked 1 = interrupt enabled Receive FIFO Half Full.
DS21352/DS21552 RHIR: RECEIVE HDLC INFORMATION REGISTER (Address=03 Hex) (MSB) RABT RCRCE SYMBOL RABT POSITION RHIR.7 RCRCE RHIR.6 ROVR RHIR.5 RVM RHIR.4 REMPTY RHIR.3 POK RHIR.2 CBYTE RHIR.1 OBYTE RHIR.0 ROVR RVM REMPTY POK CBYTE (LSB) OBYTE NAME AND DESCRIPTION Abort Sequence Detected. Set whenever the HDLC controller sees 7 or more ones in a row. CRC Error. Set when the CRC checksum is in error. Overrun.
DS21352/DS21552 RBOC: RECEIVE BIT ORIENTED CODE REGISTER (Address=04 Hex) (MSB) LBD BD BOC5 BOC4 BOC3 BOC2 BOC1 (LSB) BOC0 SYMBOL POSITION NAME AND DESCRIPTION LBD RBOC.7 BD RBOC.6 BOC5 RBOC.5 Latched BOC Detected. A latched version of the BD status bit (RBOC.6). Will be cleared when read. BOC Detected. A real–time bit that is set high when the BOC detector is presently seeing a valid sequence and set low when no BOC is currently being detected. BOC Bit 5.
DS21352/DS21552 RHFR: RECEIVE HDLC FIFO (Address=05 Hex) (MSB) RHFR7 SYMBOL RHFR6 RHFR5 RHFR4 RHFR3 POSITION NAME AND DESCRIPTION RHFR2 RHFR7 RHFR.7 HDLC Data Bit 7. MSB of a HDLC packet data byte. RHFR6 RHFR.6 HDLC Data Bit 6. RHFR5 RHFR.5 HDLC Data Bit 5. RHFR4 RHFR.4 HDLC Data Bit 4. RHFR3 RHFR.3 HDLC Data Bit 3. RHFR2 RHFR.2 HDLC Data Bit 2. RHFR1 RHFR.1 HDLC Data Bit 1. RHFR0 RHFR.0 HDLC Data Bit 0. LSB of a HDLC packet data byte.
DS21352/DS21552 BOC5 TBOC.5 0 = source FDL data from the TLINK pin 1 = source FDL data from the onboard HDLC and BOC controller BOC Bit 5. Last bit transmitted of the 6–bit codeword. BOC4 TBOC.4 BOC Bit 4. BOC3 TBOC.3 BOC Bit 3. BOC2 TBOC.2 BOC Bit 2. BOC1 TBOC.1 BOC Bit 1. BOC0 TBOC.0 BOC Bit 0. First bit transmitted of the 6–bit codeword. THFR: TRANSMIT HDLC FIFO (Address=08 Hex) (MSB) THFR7 THFR6 THFR5 THFR4 THFR3 THFR2 SYMBOL POSITION THFR7 THFR.7 HDLC Data Bit 7.
DS21352/DS21552 RD1 RDC1.1 DS0 Channel Select Bit 1. RD0 RDC1.0 DS0 Channel Select Bit 0. LSB of the DS0 channel select.
DS21352/DS21552 RDC2: RECEIVE HDLC DS0 CONTROL REGISTER 2 (Address=91 Hex) (MSB) RDB8 RDB7 SYMBOL POSITION RDB8 RDC2.7 RDB7 RDB6 RDB5 RDB4 RDB3 RDB2 RDB1 RDC2.6 RDC2.5 RDC2.4 RDC2.3 RDC2.2 RDC2.1 RDC2.0 RDB6 RDB5 RDB4 RDB3 RDB2 (LSB) RDB1 NAME AND DESCRIPTION DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to stop this bit from being used. DS0 Bit 7 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 6 Suppress Enable. Set to one to stop this bit from being used.
DS21352/DS21552 TDC1: TRANSMIT HDLC DS0 CONTROL REGISTER 1 (Address=92 Hex) (MSB) TDS0E - TDS0M TD4 TD3 TD2 TD1 (LSB) TD0 SYMBOL POSITION NAME AND DESCRIPTION TDS0E TDC1.7 - TDC1.6 TDS0M TDC1.5 TD4 TDC1.4 DS0 Selection Mode. 0 = utilize the TD0 to TD4 bits to select which single DS0 channel to use. 1 = utilize the TCHBLK control registers to select which DS0 channels to use. DS0 Channel Select Bit 4. MSB of the DS0 channel select. TD3 TDC1.3 DS0 Channel Select Bit 3. TD2 TDC1.
DS21352/DS21552 TDC2: TRANSMIT HDLC DS0 CONTROL REGISTER 2 (Address=93 Hex) (MSB) TDB8 TDB7 TDB6 SYMBOL POSITION TDB8 TDC2.7 TDB7 TDB6 TDB5 TDB4 TDB3 TDB2 TDB1 TDC2.6 TDC2.5 TDC2.4 TDC2.3 TDC2.2 TDC2.1 TDC2.0 TDB5 TDB4 TDB3 TDB2 (LSB) TDB1 NAME AND DESCRIPTION DS0 Bit 8 Suppress Enable. MSB of the DS0. Set to one to stop this bit from being used. DS0 Bit 7 Suppress Enable. Set to one to stop this bit from being used. DS0 Bit 6 Suppress Enable. Set to one to stop this bit from being used.
DS21352/DS21552 The framer also contains a zero destuffer which is controlled via the CCR2.0 bit. In both ANSI T1.403 and TR54016, communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no more than 5 ones should be transmitted in a row so that the data does not resemble an opening or closing flag (01111110) or an abort signal (11111111). If enabled via CCR2.0, the DS21352/552 will automatically look for 5 ones in a row, followed by a zero.
DS21352/DS21552 15.4.3 TRANSMIT SECTION The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing T1 data stream.
DS21352/DS21552 16. LINE INTERFACE FUNCTION The line interface function in the DS21352/552 contains three sections; (1) the receiver which handles clock and data recovery, (2) the transmitter which waveshapes and drives the T1 line, and (3) the jitter attenuator. Each of the these three sections is controlled by the Line Inter-face Control Register (LICR) which is described below. LICR: LINE INTERFACE CONTROL REGISTER (Address=7C Hex) (MSB) L2 L1 SYMBOL L2 L1 L0 EGL POSITION LICR.7 LICR.6 LICR.5 LICR.
DS21352/DS21552 16.2 TRANSMIT WAVE SHAPING AND LINE DRIVING The DS21352/552 uses a set of laser–trimmed delay lines along with a precision Digital–to–Analog Converter (DAC) to create the waveforms that are transmitted onto the T1 line. The waveforms created by the DS21352/552 meet the latest ANSI, AT&T, and ITU specifications. See Figure 16-3. The user will select which waveform is to be generated by properly programming the L2/L1/L0 bits in the Line Interface Control Register (LICR).
DS21352/DS21552 Figure 16-1 EXTERNAL ANALOG CONNECTIONS 0.47uF (nonpolarized) Rt T1 Transmit Line DS21352 / 552 DVDD DVSS TTIP TRING Rt N:1 (see table below) 1:1 VDD 0.1uF 0.01uF RVDD RVSS 0.1uF TVDD TVSS 0.1uF XTALD NC MCLK 1.544MHz RTIP T1 Receive Line RRING 50 50 0.1uF Table 16-2 TRANSMIT TRANSFORMER SELECTION DEVICE DS21552 TRANSFORMER 1.15 : 1 1.36 : 1 DS21352 2:1 See separate application note on line interface design criteria for full details. RESISTOR Rt 0 ohms Ideal, 2.
DS21352/DS21552 Figure 16-2 OPTIONAL CRYSTAL CONNECTIONS DS21352/552 XTALD 1.544MHz MCLK C1 C2 NOTES: 1. C1 and C2 should be 5 pF lower than two times the nominal loading capacitance of the crystal to adjust for the input capacitance of the DS21352/552.
DS21352/DS21552 Figure 16-3 TRANSMIT WAVEFORM TEMPLATE 1.2 1.1 1.0 0.9 0.8 NORMALIZED AMPLITUDE 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 T1.102/87, T1.403, CB 119 (Oct. 79), & I.431 Template -0.4 -0.
DS21352/DS21552 Table 16-4 PULSE TEMPLATE CORNER POINTS TIME (ns) UI MAX CURVE MIN CURVE -500 -0.77 0.05 -0.05 -255 -0.39 0.05 -175 -0.27 0.80 -175 -.027 1.15 -150 -0.23 -0.05 -150 -0.23 0.05 -100 0.95 -75 -0.12 1.15 0 0.00 1.05 100 0.15 0.90 150 0.23 0.50 150 0.23 -0.45 175 0.27 1.05 225 0.35 -0.07 300 0.46 -0.45 430 0.66 -0.20 600 0.93 0.05 -0.05 750 1.16 0.05 -0.05 88 of 137 0.
DS21352/DS21552 Figure 16-4 JITTER TOLERANCE UNIT INTERVALS (UIpp) 1K DS2152 Tolerance 100 10 MimimumTolerance Level as per TR 62411 (Dec. 90) 1 0.
DS21352/DS21552 16.4 PROTECTED INTERFACES In certain applications, such as connecting to the PSTN, it is required that the network interface be protected from and resistant to certain electrical conditions. These conditions are divided into two categories, surge and power line cross. A typical cause of surge is lightening strike. Power line cross refers to accidental contact with high voltage power wiring.
DS21352/DS21552 Figure 16-6 PROTECTED INTERFACE EXAMPLE FOR THE DS21552 +VDD D1 Fuse Transmit Line R1 N:1 Rt S R2 Fuse Fuse Receive Line X1 R3 Rt TTIP C2 C1 D3 1:1 DS21552 D2 TRING D4 RVDD RVSS TVDD TVSS 470 RTIP R4 DVDD DVSS 470 MCLK +5V 0.1uF 0.01uF + 68uf 0.1uF 0.1uF 1.544MHz RRING Fuse X2 Rterm Rterm 0.1uF Note: The 68uf cap is required to maintain VDD during a transient event.
DS21352/DS21552 Figure 16-7 PROTECTED INTERFACE EXAMPLE FOR THE DS21352 +VDD D1 Fuse DS21352 D2 2:1 TTIP Transmit Line S Fuse Fuse X1 C2 C1 D3 1:1 TRING D4 DVDD DVSS RVDD RVSS TVDD TVSS 470 RTIP Receive Line 470 MCLK RRING Fuse X2 50 50 0.1uF Note: The 68uf cap is required to maintain VDD levels during a transient event. COMPONET D1 – D4 C1 C2 Fuse S X1, X2 DESCRIPTION Schottky Diode, International Rectifier 11DQ04 0.1uf ceramic in parallel with 10uf tantalum .
DS21352/DS21552 16.5 RECEIVE MONITOR MODE When connecting to a monitor port a large resistive loss is incurred due to the voltage divider between the T1 line termination resistors (Rt) and the monitor port isolation resistors (Rm) as shown below. The Rm resistors are typically 470 ohm. This, along with the 100 ohm termination (Rt), produces 20dB of loss. The receiver of the DS21352/552 can provide gain to overcome the resistive loss of a monitor connection.
DS21352/DS21552 17. PROGRAMMABLE IN–BAND LOOP CODE GENERATION AND DETECTION Each framer in the DS21352/552 has the ability to generate and detect a repeating bit pattern that is from one to eight bits in length. To transmit a pattern, the user will load the pattern to be sent into the Transmit Code Definition (TCD) register and select the proper length of the pattern by setting the TC0 and TC1 bits in the In–Band Code Control (IBCC) register.
DS21352/DS21552 Table 17-1 TRANSMIT CODE LENGTH TC1 0 0 1 1 TC0 0 1 0 1 LENGTH SELECTED 5 bits 6 bits / 3 bits 7 bits 8 bits / 4 bits / 2 bits / 1 bits Table 17-2 RECEIVE CODE LENGTH RUP2/ RDN2 0 0 0 0 1 1 1 1 RUP1/ RDN1 0 0 1 1 0 0 1 1 RUP0/ RDN0 0 1 0 1 0 1 0 1 LENGTH SELECTED 1 bits 2 bits 3 bits 4 bits 5 bits 6 bits 7 bits 8 bits TCD: TRANSMIT CODE DEFINITION REGISTER (Address=13 Hex) (MSB) C7 C6 C5 C4 C3 C2 C1 (LSB) C0 SYMBOL POSITION NAME AND DESCRIPTION C7 TCD.
DS21352/DS21552 RUPCD: RECEIVE UP CODE DEFINITION REGISTER (Address=14 Hex) (MSB) C7 C6 C5 C4 C3 C2 C1 (LSB) C0 SYMBOL POSITION NAME AND DESCRIPTION C7 RUPCD.7 Receive Up Code Definition Bit 7. First bit of the repeating pattern. C6 C5 C4 C3 C2 C1 C0 RUPCD.6 RUPCD.5 RUPCD.4 RUPCD.3 RUPCD.2 RUPCD.1 RUPCD.0 Receive Up Code Definition Bit 6. A Don’t Care if a 1 bit length is selected. Receive Up Code Definition Bit 5. A Don’t Care if a 1 or 2 bit length is selected.
DS21352/DS21552 18. TRANSMIT TRANSPARENCY Each of the 24 T1 channels in the transmit direction of the framer can be either forced to be transparent or in other words, can be forced to stop Bit 7 Stuffing and/or Robbed Signaling from overwriting the data in the channels. Transparency can be invoked on a channel by channel basis by properly setting the TTR1, TTR2, and TTR3 registers.
DS21352/DS21552 The DS21352/552 are enhanced versions of the DS2152 and are backward pin-compatible. The JTAG feature uses pins that had no function in the DS2152. When using the JTAG feature, be sure FMS (pin 76) is tied LOW enabling the newly defined pins of the DS21352/552. Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE 1149.1a-1993, and IEEE 1149.1b-1994. The Test Access Port has the necessary interface pins; JTRST, JTCLK, JTMS, JTDI, and JTDO.
DS21352/DS21552 19.2 TAP CONTROLLER STATE MACHINE The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 19-1. TEST-LOGIC-RESET Upon power up, the TAP Controller will be in the Test-Logic-Reset state. The Instruction register will contain the IDCODE instruction. All system logic of the device will operate normally. RUN-TEST-IDLE The Run-Test-Idle is used between scan operations or during specific tests.
DS21352/DS21552 SELECT-IR-SCAN All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and will initiate a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the Test-Logic-Reset state. CAPTURE-IR The Capture-IR state is used to load the shift register in the instruction register with a fixed value.
DS21352/DS21552 Figure 19-2 TAP CONTROLLER STATE DIAGRAM 1 Test Logic Reset 0 0 Run Test/ Idle 1 Select DR-Scan 1 Select IR-Scan 0 1 0 1 Capture DR Capture IR 0 Shift DR 0 Shift IR 0 1 Exit DR 1 Exit IR Exit2 DR Pause IR 0 1 0 0 1 0 Exit2 IR 1 Update DR 1 0 1 0 0 1 0 Pause DR 1 1 Update IR 1 0 19.3 INSTRUCTION REGISTER The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.
DS21352/DS21552 Table 19-1 INSTRUCTION CODES FOR IEEE 1149.1 ARCHITECTURE Instruction Selected Register Instruction Codes SAMPLE/PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification 010 111 000 011 100 001 SAMPLE/PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions.
DS21352/DS21552 IDCODE When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected. The device identification code will be loaded into the identification register on the rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output.
DS21352/DS21552 IDENTIFICATION REGISTER The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-LogicReset state. See Table 19-2. Table 19-3 lists the device ID codes for the SCT devices.
DS21352/DS21552 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 45 46 47 48 49 50 51 52 53 54 55 – DVSS TCLK TSER TSIG TESO TDATA TSYSCLK TSSYNC TCHCLK CO MUX BUS.
DS21352/DS21552 7 6 97 – RFSYNC RSYNC.
DS21352/DS21552 20. INTERLEAVED PCM BUS OPERATION In many architectures, the outputs of individual framers are combined into higher speed serial buses to simplify transport across the system. The DS21352/552 can be configured to allow data and signaling buses to be multiplexed into higher speed data and signaling buses eliminating external hardware saving board space and cost. The interleaved PCM bus option (IBO) supports two bus speeds. The 4.096 MHz bus speed allows two SCTs to share a common bus. The 8.
DS21352/DS21552 Table 20-1 MASTER DEVICE BUS SELECT MSEL1 0 0 1 1 MSEL0 0 1 0 1 Function Slave device. Master device with 1 slave device (4.096 MHz bus rate) Master device with 3 slave devices (8.192 MHz bus rate) Reserved Figure 20-1 IBO BASIC CONFIGURATION USING 4 SCTS CI RSYSCLK TSYSCLK MASTER SCT CI RSYSCLK TSYSCLK RSYNC TSSYNC RSYNC TSSYNC RSIG TSIG TSER RSER CO SLAVE #2 RSIG TSIG TSER RSER CO 8.
DS21352/DS21552 20.1 CHANNEL INTERLEAVE In channel interleave mode data is output to the PCM Data Out bus one channel at a time from each of the connected SCTs until all channels of frame n from all each SCT has been place on the bus. This mode can be used even when the connected SCTs are operating asynchronous to each other. The elastic stores will manage slip conditions. See Figure 21-13 for details. 20.
DS21352/DS21552 Figure 21-2 RECEIVE SIDE ESF TIMING FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 1 RSYNC RFSYNC RSYNC RSYNC RLCLK 2 3 4 5 RLINK TLCLK 6 TLINK 7 Notes: 1. RSYNC in frame mode (RCR2.4 = 0) and double wide frame sync is not enabled (RCR2.5 = 0) 2. RSYNC in frame mode (RCR2.4 = 0) and double wide frame sync is enabled (RCR2.5 = 1) 3. RSYNC in multiframe mode (RCR2.4 = 1) 4. ZBTSI mode disabled (RCR2.6 = 0) 5.
DS21352/DS21552 Figure 21-3 RECEIVE SIDE BOUNDARY TIMING (with elastic store disabled) RCLK CHANNEL 23 RSER CHANNEL 24 CHANNEL 1 LSB LSB MSB F MSB RSYNC RFSYNC RSIG CHANNEL 23 A B C/A D/B CHANNEL 24 A B C/A D/B CHANNEL 1 A RCHCLK RCHBLK1 RLCLK RLINK 2 Notes: 1. RCHBLK is programmed to block channel 24 2. Shown is RLINK/RLCLK in the ESF framing mode Figure 21-4 RECEIVE SIDE 1.
DS21352/DS21552 Figure 21-5 RECEIVE SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) RSYSCLK 1 RSER CHANNEL 31 CHANNEL 32 LSB MSB CHANNEL 1 LSB F5 2 RSYNC RMSYNC 3 RSYNC RSIG CHANNEL 32 A B C/A D/B CHANNEL 31 A B C/A D/B RCHCLK RCHBLK 4 Notes: 1. RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to one 2. RSYNC is in the output mode (RCR2.3 = 0) 3. RSYNC is in the input mode (RCR2.3 = 1) 4. RCHBLK is forced to one in the same channels as RSER (see Note 1) 5.
DS21352/DS21552 Figure 21-6 RECEIVE SIDE INTERLEAVE BUS OPERATION, BYTE MODE RSYNC RSER1 FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2 RSIG1 FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2 RSER2 FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2 RSIG2 FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2 BIT DETAIL RSYSCLK RSYNC3 FRAMER 3, CHANNEL 32 RSER FRAMER 3, CHANNEL 32 RSIG A B C D FRAMER 1, CHANNEL 1 FRAMER 0, CHA
DS21352/DS21552 Figure 21-7 RECEIVE SIDE INTERLEAVE BUS OPERATION, FRAME MODE RSYNC RSER1 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 RSIG FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 RSER 2 RSIG2 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 BIT DETAIL RSYSCLK RSYNC3 FRAMER 3, CHANNEL 32 RSER A
DS21352/DS21552 Figure 21-8 TRANSMIT SIDE D4 TIMING FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 1 2 1 TSYNC TSSYNC 2 TSYNC 3 TSYNC TLCLK TLINK 4 Notes: 1. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is not enabled (TCR2.4 = 0) 2. TSYNC in the frame mode (TCR2.3 = 0) and double-wide frame sync is enabled (TCR2.4 = 1) 3. TSYNC in the multiframe mode (TCR2.3 = 1) 4.
DS21352/DS21552 Figure 21-9 TRANSMIT SIDE ESF TIMING FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 TSYNC1 TSSYNC TSYNC 2 3 TSYNC TLCLK 4 TLINK TLCLK 5 TLINK 6 Notes: 1. 2. 3. 4. 5. 6. 7. TSYNC in frame mode (TCR2.3 = 0) and double-wide frame sync is not enabled (TCR2.4 = 0) TSYNC in frame mode (TCR2.3 = 0) and double-wide frame sync is enabled (TCR2.4 = 1) TSYNC in multiframe mode (TCR2.
DS21352/DS21552 Figure 21-10 TRANSMIT SIDE BOUNDARY TIMING (with elastic store disabled) TCLK CHANNEL 1 LSB TSER F CHANNEL 2 MSB LSB MSB LSB MSB TSYNC1 TSYNC2 CHANNEL 1 TSIG D/B A B CHANNEL 2 C/A D/B A B C/A D/B TCHCLK TCHBLK 3 TLCLK TLINK DON'T CARE 4 Notes: 1. TSYNC is in the output mode (TCR2.2 = 1) 2. TSYNC is in the input mode (TCR2.2 = 0) 3. TCHBLK is programmed to block channel 2 4. Shown is TLINK/TLCLK in the ESF framing mode Figure 21-11 TRANSMIT SIDE 1.
DS21352/DS21552 Figure 21-12 TRANSMIT SIDE 2.048 MHz BOUNDARY TIMING (with elastic store enabled) TSYSCLK CHANNEL 31 TSER1 CHANNEL 32 LSB MSB CHANNEL 1 LSB F 4 TSSYNC CHANNEL 31 TSIG A B CHANNEL 32 C/A D/B A B CHANNEL 1 C/A D/B TCHCLK TCHBLK 2,3 Notes: 1. TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored 2. TCHBLK is programmed to block channel 31 (if the TPCSI bit is set, then the signaling data at TSIG will be ignored). 3.
DS21352/DS21552 Figure 21-13 TRANSMIT SIDE INTERLEAVE BUS OPERATION, BYTE MODE TSSYNC TSER1 FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2 TSIG1 FR1 CH32 FR0 CH1 FR1 CH1 FR0 CH2 FR1 CH2 TSER2 FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2 TSIG2 FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR1 CH2 FR2 CH2 FR3 CH2 BIT DETAIL TSYSCLK 3 TSSYNC FRAMER 3, CHANNEL 32 TSER TSIG LSB MSB LSB MSB FRAMER 3, CHANNEL 32 A B C/A D/B FRAMER 0
DS21352/DS21552 Figure 21-14 TRANSMIT INTERLEAVE BUS OPERATION, FRAME MODE TSSYNC TSER1 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 TSIG1 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 FR0 CH1-32 FR1 CH1-32 TSER2 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 TSIG2 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 FR0 CH1-32 FR1 CH1-32 FR2 CH1-32 FR3 CH1-32 BIT DETAIL TSYSCLK TSSYNC FRAMER 3, CHANNEL 32 TSER TSIG
DS21352/DS21552 22. RECEIVE AND TRANSMIT DATA FLOW DIAGRAMS Figure 22-1 RECEIVE DATA FLOW RNEGI RSYNC RPOSI B8ZS Decoder 0 RMR1 to RMR3 RCR2.7 1 Receive Mark Code Insertion 0 RCC1 to RCC3 RC1 to RC24 1 Per Channel Code Insertion Signaling All Ones CCR4.5 Elastic Store Freeze SIGNALING EXTRACTION 0 RCBR1 to RCBR3 Per Channel Signaling Re-Insert Enable (CCR4.6) SIGNALING BUFFER 1 Receive Signaling Re-insertion Signaling Re-insertion enable (CCR4.
DS21352/DS21552 Figure 22-2 TRANSMIT DATA FLOW TSER & TDATA HDLC ENGINE TCBR1/2/3 0 CCR4.1 TSIG Hardware Signaling Insertion CCR4.2 DS0 insertion enable (TDC1.7) TCD2 Figure 15.11 DS2152 TRANSMIT DATA FLOW 0 TCD1 4:0 1 0 Source Mux TCHBLK 1 TC1 to TC24 1 TDC1.5 TCC1 to TCC3 0 Per-Channel Code Generation IBCC TIR Function Select (CCR4.0) 0 TIDR In-Band Loop Code Generator TCD CCR3.1 RSER 1 (note#1) 1 0 Idle Code / Per Channel LB TIR1 to TIR3 0 Software Signaling Enable (TCR1.
DS21352/DS21552 23. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature for DS21352L/DS21552L Operating Temperature for DS21352LN/DS21552LN Storage Temperature Soldering Temperature –1.0V to +6.0V 0°C to 70°C –40°C to +85°C –55°C to +125°C 260°C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
DS21352/DS21552 24. AC TIMING PARAMETERS AND DIAGRAMS 24.
DS21352/DS21552 Figure 24-1 INTEL BUS READ TIMING (BTS=0 / MUX = 1) t CYC ALE WR* PWASH t ASD t ASD t ASED PWEH RD* t CH t CS PWEL CS* t ASL t DHR t DDR AD0-AD7 t AHL Figure 24-2 INTEL BUS WRITE TIMING (BTS=0 / MUX=1) t CYC ALE RD* PWASH t ASD t ASED t ASD WR* PWEL PWEH t CH t CS CS* t ASL t DHW AD0-AD7 t AHL 125 of 137 t DSW
DS21352/DS21552 Figure 24-3 MOTOROLA BUS TIMING (BTS = 1 / MUX = 1) PWASH AS DS PWEH t ASED t ASD PWEL t CYC t RWS t RWH R/W* AD0-AD7 (read) t DDR t ASL t AHL t DHR t CH t CS CS* AD0-AD7 (write) t DSW t ASL t DHW t AHL 126 of 137
DS21352/DS21552 24.
DS21352/DS21552 Figure 24-4 INTEL BUS READ TIMING (BTS=0 / MUX=0) A0 to A7 Address Valid D0 to D7 Data Valid 5ns min. / 20ns max. t5 WR* t1 0ns min. CS* 0ns min. t2 RD* t3 75ns max. t4 0ns min. Figure 24-5 INTEL BUS WRITE TIMING (BTS=0 / MUX=0) A0 to A7 Address Valid D0 to D7 t7 10ns min. RD* t1 CS* 0ns min. WR* t8 10ns min. 0ns min. t2 t6 75ns min. 128 of 137 t4 0ns min.
DS21352/DS21552 Figure 24-6 MOTOROLA BUS READ TIMING (BTS=1 / MUX=0) A0 to A7 Address Valid D0 to D7 Data Valid 5ns min. / 20ns max. t5 R/W* t1 0ns min. CS* 0ns min. t2 t3 t4 0ns min. 75ns max. DS* Figure 24-7 MOTOROLA BUS WRITE TIMING (BTS=1 / MUX=0) A0 to A7 Address Valid D0 to D7 10ns min. R/W* t1 t7 t8 10ns min. 0ns min. CS* 0ns min. DS* t2 t6 75ns min. 129 of 137 t4 0ns min.
DS21352/DS21552 24.
DS21352/DS21552 RCLK t D1 F Bit RSER / RDATA / RSIG t D2 RCHCLK t D2 RCHBLK t D2 RFSYNC / RMSYNC t D2 RSYNC 1 RLCLK t D2 2 t D1 RLINK Notes: 1. RSYNC is in the output mode (RCR2.3 = 0). 2. Shown is RLINK/RLCLK in the ESF framing mode 3.
DS21352/DS21552 Figure 24.9 RECEIVE SIDE TIMING, ELASTIC STORE ENABLED t SL tF tR RSYSCLK t SH t SP t D3 SEE NOTE 3 RSER / RSIG t D4 RCHCLK t D4 RCHBLK t D4 RMSYNC / CO t D4 RSYNC1 t HD t SU RSYNC2 t SC t WC CI Notes: 1. RSYNC is in the output mode (RCR2.3 = 0) 2. RSYNC is in the input mode (RCR2.3 = 1) 3. F-BIT when CCR1.3 = 0, MSB of TS0 when CCR1.
DS21352/DS21552 Figure 24-10 RECEIVE LINE INTERFACE TIMING t LL RCLKO t LH t LP t DD RPOSO, RNEGO tR t CL tF RCLKI t CH t CP t SU RPOSI, RNEGI t HD 133 of 137
DS21352/DS21552 24.
DS21352/DS21552 Figure 24-11 TRANSMIT SIDE TIMING t CP t CL tF tR t CH TCLK t D1 TESO t SU TSER / TSIG / TDATA t HD t D2 TCHCLK t D2 TCHBLK t D2 TSYNC1 t HD t SU TSYNC2 5 TLCLK t D2 t HD TLINK t SU Notes: 1. TSYNC is in the output mode (TCR2.2 = 1). 2. TSYNC is in the input mode (TCR2.2 = 0). 3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled. 4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled. 5.
DS21352/DS21552 Figure 24-12 TRANSMIT SIDE TIMING, ELASTIC STORE ENABLED t SP t SL tF tR t SH TSYSCLK t SU TSER t D3 t HD TCHCLK t D3 TCHBLK t HD t SU TSSYNC Notes: 1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. 2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is enabled.
DS21352/DS21552 25.