DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS21354/DS213554 single-chip transceivers (SCTs) contain all the necessary functions to connect to E1 lines. The devices are upward-compatible versions of the DS2153 and DS2154 SCTs. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. Both devices automatically adjust to E1 22AWG (0.6mm) twistedpair cables from 0 to over 2km in length.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TABLE OF CONTENTS 1. INTRODUCTION.................................................................................................................. 6 1.1. FUNCTIONAL DESCRIPTION..............................................................................................................................7 1.2. DOCUMENT REVISION HISTORY .............................................................................................................8 2.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 12. ELASTIC STORES OPERATION...................................................................................... 65 12.1. RECEIVE SIDE .......................................................................................................................................65 12.2. TRANSMIT SIDE.....................................................................................................................................65 13.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers LIST OF FIGURES Figure 2-1. DS21354/554 Block Diagram ............................................................................................................................. 9 Figure 15-1. Basic External Analog Connections .............................................................................................................. 83 Figure 15-2. Optional Crystal Connection............................................................................
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers LIST OF TABLES Table 3-1. Pin Description Sorted by Pin Number............................................................................................................. 10 Table 3-2. Pin Description by Symbol ................................................................................................................................. 12 Table 4-1. Register Map Sorted by Address ........................................................................
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 1. INTRODUCTION The DS21354/DS21554 are superset versions of the popular DS2153 and DS2154 SCTs offering the new features listed below. All the original features of the DS2153 and DS2154 have been retained, and the software created for the original devices is transferable into the DS21354/DS21554. New Features in the DS21354 and DS21554 FEATURE HDLC controller with 64-Byte Buffers for Sa Bits or DS0s or Sub DS0s Interleaving PCM Bus Operation IEEE 1149.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 1.1. Functional Description The analog AMI/HDB3 waveform off the E1 line is transformer coupled into the RRING and RTIP pins of the DS21354/554. The device recovers clock and data from the analog signal and passes it through the jitter attenuation mux to the receive-side framer where the digital serial stream is analyzed to locate the framing/multiframe pattern.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 1.2. Document Revision History REVISION DESCRIPTION 012799 Initial release 012899 Corrected TSYSCLK and RSYSCLK timing and added 4.096MHz and 8.192MHz timing 020399 Corrected definition and label of TUDR bit in the THIR register. 021199 Corrected address of IBO register in text.
32.768MHz Local Loopback 9 of 124 JTAG PORT Receive Line I/F Clock / Data Recovery TTIP TRING MCLK RTIP XTALD 16.384 MHz RRING 8XCLK VCO / PLL MUX RPOSI RCLKI RNEGI RNEGO RCLKO RPOSO MUX LIUC DS21354/ DS21554 Sa Transmit Line I/F Framer Loopback Jitter Attenuator Either transmit or receive path 7 8 HDLC/BOC Controller Sa / DS0 LOTC MUX Elastic Store Sync Control Elastic Store Timing Control RSYSCLK Interleave Bus Interleave Bus 8.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 3. PIN DESCRIPTION Table 3-1. Pin Description Sorted by Pin Number PIN 1 2 3 4 5 6 7 8, 9, 15, 23, 26, 27, 28 10 11 12 13 14 16 17 18 19, 20, 24 21 22 25 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44, 61, 81,83 45, 60, 80, 84 46 47 48 NAME RCHBLK JTMS 8MCLK JTCLK JTRST RCL JTDI TYPE O I O I I O I FUNCTION Receive Channel Block IEEE 1149.1 Test Mode Select 8.192 MHz Clock IEEE 1149.1 Test Clock Signal IEEE 1149.
DS21354/DS21554 3.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Table 3-2.
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 3.1. 3.1.1. Pin Function Description Transmit-Side Pins Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 2.048MHz primary clock. Used to clock data through the transmit side formatter. Signal Name: TSER Signal Description: Transmit Serial Data Signal Type: Input Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit side elastic store is disabled.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Signal Name: TLINK Signal Description: Transmit Link Data Signal Type: Input If enabled, this pin will be sampled on the falling edge of TCLK for data insertion into any combination of the Sa bit positions (Sa4 to Sa8). See Section 13 for details. Signal Name: TSYNC Signal Description: Transmit Sync Signal Type: Input/Output A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Via TCR1.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Signal Name: TNEGO Signal Description: Transmit Negative Data Output Signal Type: Output Updated on the rising edge of TCLKO with the bipolar data out of the transmit-side formatter. This pin is normally tied to TNEGI. Signal Name: TCLKO Signal Description: Transmit Clock Output Signal Type: Output Buffered output of signal that is clocking data through the transmit-side formatter. This pin is normally tied to TCLKI.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 3.1.2. Receive-Side Pins Signal Name: RLINK Signal Description: Receive Link Data Signal Type: Output Updated with the fully recovered E1 data stream on the rising edge of RCLK. Signal Name: RLCLK Signal Description: Receive Link Clock Signal Type: Output 4kHz to 20kHz clock (Sa bits) for the RLINK output. See Section 13 for details. Signal Name: RCLK Signal Description: Receive Clock Signal Type: Output 2.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Signal Name: RFSYNC Signal Description: Receive Frame Sync Signal Type: Output An extracted 8kHz pulse, one RCLK wide, is output at this pin that identifies frame boundaries. Signal Name: RMSYNC Signal Description: Receive Multiframe Sync Signal Type: Output If the receive-side elastic store is enabled, an extracted pulse, one RSYSCLK wide, is output at this pin that identifies multiframe boundaries.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Signal Name: 8MCLK Signal Description: 8MHz Clock Signal Type: Output An 8.192MHz clock output that is referenced to the clock that is output at the RCLK pin. Signal Name: RPOSO Signal Description: Receive Positive Data Input Signal Type: Output Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied to RPOSI.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 3.1.3. Parallel Control Port Pins Signal Name: INT Signal Description: Interrupt Signal Type: Output Active-low, open-drain output that flags host controller during conditions and change of conditions defined in the Status Registers 1 and 2 and the HDLC Status Register. Signal Name: FMS Signal Description: Framer Mode Select Signal Type: Input Selects the DS2154 mode when high or the DS21354/DS21554 mode when low.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Signal Name: RD (DS) Signal Description: Read Input—Data Strobe Signal Type: Input In Intel Mode, RD determines when data is read from the device. In Motorola Mode, DS is used to write to the device. See the Bus Timing Diagrams section. CS Signal Name: Signal Description: Chip Select Signal Type: Input Must be low to read or write to the device. CS is an active-low signal.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 3.1.4. JTAG Test Access Port Pins JTRST Signal Name: Signal Description: IEEE 1149.1 Test Reset Signal Type: Input This signal is used to asynchronously reset the test access port controller. At power up, JTRST must be toggled from low to high. This action will set the device into JTAG DEVICE ID mode enabling the test access port features. This pin has a 10kW pullup resistor. When FMS = 1, this pin is tied low internally.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 3.1.6. Line Interface Pins Signal Name: MCLK Signal Description: Master Clock Input Signal Type: Input A 2.048MHz (±50ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both clock/data recovery and for jitter attenuation. A quartz crystal of 2.048MHz may be applied across MCLK and XTALD instead of the TTL level clock source.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 3.1.7. Supply Pins Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 5.0V ±5% (DS21554) or 3.3V ±5% (DS21354). Should be tied to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal Type: Supply 5.0V ±5% (DS21554) or 3.3V ±5% (DS21354). Should be tied to the DVDD and TVDD pins. Signal Name: TVDD Signal Description: Transmit Analog Positive Supply Signal Type: Supply 5.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 4. PARALLEL PORT The DS21354/DS21554 are controlled through either a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The device can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing is selected; if tied high, Motorola timing is selected. All Motorola bus signals are listed in parentheses ().
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DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 5. CONTROL, ID, AND TEST REGISTERS The operation of the DS21354/DS21554 is configured via a set of 10 control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers need only to be accessed when there is a change in the system configuration.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers IDR: DEVICE IDENTIFICATION REGISTER (Address = 0F Hex) (MSB) T1E1 Bit 6 Bit 5 Bit 4 ID3 ID2 SYMBOL POSITION T1E1 IDR.7 Bit 6 Bit 5 Bit 4 IDR.6 IDR.5 IDR.4 ID3 IDR.3 ID2 ID1 IDR.1 IDR.2 ID0 IDR.0 POSITION RSMF RCR1.7 RSM RCR1.6 RSIO RCR1.5 — — RCR1.4 RCR1.3 FRC RCR1.2 SYNCE RCR1.1 RESYNC RCR1.0 (LSB) ID0 NAME AND DESCRIPTION T1 or E1 Chip Determination Bit. Set to 1. 0 = T1 chip 1 = E1 chip Bit 6. See Table 5-1. Bit 5.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 5.2. Synchronization And Resynchronization Once synchronization is accomplished there are certain criteria that can cause a resynchronization. These criteria are detailed in Table 5-2. Also see Figure 18-14 for a flow chart of the synchronization process. Table 5-2.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers RCR2: RECEIVE CONTROL REGISTER 2 (Address = 11 Hex) (MSB) Sa8S Sa7S Sa6S Sa5S Sa4S RBCS SYMBOL POSITION Sa8S RCR2.7 Sa7S RCR2.6 Sa6S RCR2.5 Sa5S RCR2.4 Sa4S RCR2.3 RBCS RCR2.2 RESE RCR2.1 — RCR2.0 RESE (LSB) — NAME AND DESCRIPTION Sa8 Bit Select. Set to one to have RLCLK pulse at the Sa8 bit position; set to zero to force RLCLK low during Sa8 bit position. See Section 18.1 for timing details. Sa7 Bit Select.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TCR1: TRANSMIT CONTROL REGISTER 1 (Address = 12 Hex) (MSB) ODF TFPT T16S TUA1 TSiS TSA1 SYMBOL POSITION ODF TCR1.7 TFPT TCR1.6 T16S TCR1.5 TUA1 TCR1.4 TSiS TCR1.3 TSA1 TCR1.2 TSM TCR1.1 TSIO TCR1.0 TSM (LSB) TSIO NAME AND DESCRIPTION Output Data Format. 0 = bipolar data at TPOSO and TNEGO 1 = NRZ data at TPOSO; TNEGO=0 Transmit Time Slot 0 Pass Through.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TCR2: TRANSMIT CONTROL REGISTER 2 (Address = 13 Hex) (MSB) Sa8S Sa7S Sa6S Sa5S Sa4S ODM SYMBOL POSITION Sa8S TCR2.7 Sa7S TCR2.6 Sa6S TCR2.5 Sa5S TCR2.4 Sa4S TCR2.3 ODM TCR2.2 AEBE TCR2.1 PF TCR2.0 AEBE (LSB) PF NAME AND DESCRIPTION Sa8 Bit Select. Set to one to source the Sa8 bit from the TLINK pin; to zero to not source the Sa8 bit. See Section 18.2 for timing details. Sa7 Bit Select.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers CCR1: COMMON CONTROL REGISTER 1 (Address = 14 Hex) (MSB) FLB THDB3 TG802 TCRC4 RSM RHDB3 SYMBOL POSITION FLB CCR1.7 THDB3 CCR1.6 TG802 CCR1.5 TCRC4 CCR1.4 RSM CCR1.3 RHDB3 CCR1.2 RG802 CCR1.1 RCRC4 CCR1.0 RG802 (LSB) RCRC4 NAME AND DESCRIPTION Framer Loopback. 0 = loopback disabled 1 = loopback enabled Transmit HDB3 Enable. 0 = HDB3 disabled 1 = HDB3 enabled Transmit G.802 Enable. See Section 18 for details.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers CCR2: COMMON CONTROL REGISTER 2 (Address = 1A Hex) (MSB) ECUS VCRFS AAIS ARA RSERC LOTCMC SYMBOL POSITION ECUS CCR2.7 VCRFS CCR2.6 AAIS CCR2.5 ARA CCR2.4 RSERC CCR2.3 LOTCMC CCR2.2 RFF CCR2.1 RFE CCR2.0 RFF (LSB) RFE NAME AND DESCRIPTION Error Counter Update Select. See Section 7 for details. 0 = update error counters once a second 1 = update error counters every 62.5ms (500 frames) VCR Function Select. See Section 7.1 for details.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 5.4. Automatic Alarm Generation The device can be programmed to automatically transmit AIS or Remote Alarm. When automatic AIS generation is enabled (CCR2.5 = 1), the device monitors the receive-side framer to determine if any of the following conditions are present: loss-of-receive frame synchronization, AIS alarm (all ones) reception, or loss of receive carrier (or signal).
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers CCR3: COMMON CONTROL REGISTER 3 (Address=1B Hex) (MSB) TESE TCBFS TIRFS — RSRE THSE SYMBOL POSITION TESE CCR3.7 TCBFS CCR3.6 TIRFS CCR3.5 - CCR3.4 RSRE CCR3.3 THSE CCR3.2 TBCS CCR3.1 RCLA CCR3.0 TBCS (LSB) RCLA NAME AND DESCRIPTION Transmit-Side Elastic Store Enable. 0 = elastic store is bypassed 1 = elastic store is enabled Transmit Channel Blocking Registers (TCBR) Function Select.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers CCR4: COMMON CONTROL REGISTER 4 (Address = A8 Hex) (MSB) RLB LLB LIAIS TCM4 TCM3 TCM2 SYMBOL POSITION RLB CCR4.7 LLB CCR4.6 LIAIS CCR4.5 TCM4 CCR4.4 TCM3 TCM2 TCM1 TCM0 CCR4.3 CCR4.2 CCR4.1 CCR4.0 TCM1 (LSB) TCM0 NAME AND DESCRIPTION Remote Loopback. 0 = loopback disabled 1 = loopback enabled Local Loopback. 0 = loopback disabled 1 = loopback enabled Line Interface AIS Generation Enable.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers CCR5: COMMON CONTROL REGISTER 5 (Address = AA Hex) (MSB) LIRST RESA TESA RCM4 RCM3 RCM2 SYMBOL POSITION LIRST CCR5.7 RESA CCR5.6 TESA CCR5.5 RCM4 CCR5.4 RCM3 RCM2 RCM1 RCM0 CCR5.3 CCR5.2 CCR5.1 CCR5.0 RCM1 (LSB) RCM0 NAME AND DESCRIPTION Line Interface Reset. Setting this bit from a zero to a one will initiate an internal reset that affects the clock recovery state machine and jitter attenuator. Normally this bit is only toggled on power-up.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers CCR6: COMMON CONTROL REGISTER 6 (Address = 1D Hex) (MSB) LIUODO CDIG LIUSI — — TCLKSRC SYMBOL POSITION LIUODO CCR6.7 CDIG CCR6.6 LIUSI CCR6.5 — — CCR6.4 CCR6.3 TCLKSRC CCR6.2 RESR CCR6.1 TESR CCR6.0 RESR (LSB) TESR NAME AND DESCRIPTION Line Interface Open-Drain Option. This control bit determines whether the TTIP and TRING outputs will be open drain or not.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 6. STATUS AND INFORMATION REGISTERS The DS21354/DS21554 have a set of seven registers that contain information on the current real-time status of a framer—Status Register 1 (SR1), Status Register 2 (SR2), Receive Information Register (RIR), Synchronizer Status Register (SSR), and a set of three registers for the on-board HDLC controller.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers RIR: RECEIVE INFORMATION REGISTER (Address = 08 Hex) (MSB) TESF TESE JALT RESF RESE CRCRC SYMBOL POSITION TESF RIR.7 TESE RIR.6 JALT RIR.5 RESF RIR.4 RESE RIR.3 CRCRC RIR.2 FASRC RIR.1 CASRC RIR.0 POSITION SSR.7 SSR.6 SSR.5 SSR.4 CSC0 SSR.3 FASSA SSR.2 CASSA SSR.1 CRC4SA SSR.0 (LSB) CASRC NAME AND DESCRIPTION Transmit-Side Elastic Store Full. Set when the transmit-side elastic store buffer fills and a frame is deleted.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 6.1. CRC4 Sync Counter The CRC4 Sync Counter increments each time the 8ms CRC4 multiframe search times out. The counter is cleared when the framer has successfully obtained synchronization at the CRC4 level. The counter can also be cleared by disabling the CRC4 mode (CCR1.0 = 0). This counter is useful for determining the amount of time the framer has been searching for synchronization at the CRC4 level. ITU G.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Table 6-1. Alarm Criteria ALARM RSA1 (Receive Signaling All Ones) RSA0 (Receive Signaling All Zeros) RDMA (Receive Distant Multiframe Alarm) RUA1 (Receive Unframed All Ones) RRA (Receive Remote Alarm) RCL (Receive Carrier Loss) SET CRITERIA over 16 consecutive frames (one full MF) time slot 16 contains less than three zeros over 16 consecutive frames (one full MF) time slot 16 contains all zeros ITU SPEC. G.732 4.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers SR2: STATUS REGISTER 2 (Address = 07 Hex) (MSB) RMF RAF TMF SEC SYMBOL POSITION RMF SR2.7 RAF SR2.6 TMF SR2.5 SEC SR2.4 TAF SR2.3 LOTC SR2.2 RCMF SR2.1 TSLIP SR2.0 TAF LOTC RCMF (LSB) TSLIP NAME AND DESCRIPTION Receive CAS Multiframe. Set every 2ms (regardless if CAS signaling is enabled or not) on receive multiframe boundaries. Used to alert the host that signaling data is available. Receive Align Frame.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers IMR1: INTERRUPT MASK REGISTER 1 (Address = 16 Hex) (MSB) RSA1 RDMA RSA0 RSLIP RUA1 RRA SYMBOL POSITION RSA1 IMR1.7 RDMA IMR1.6 RSA0 IMR1.5 RSLIP IMR1.4 RUA1 IMR1.3 RRA IMR1.2 RCL IMR1.1 RLOS IMR1.0 NAME AND DESCRIPTION Receive Signaling All Ones/Signaling Change. 0 = interrupt masked 1 = interrupt enabled Receive Distant MF Alarm. 0 = interrupt masked 1 = interrupt enabled Receive Signaling All Zeros/Signaling Change.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers IMR2: INTERRUPT MASK REGISTER 2 (Address = 17 Hex) (MSB) RMF RAF TMF SEC TAF LOTC SYMBOL POSITION RMF IMR2.7 RAF IMR2.6 TMF IMR2.5 SEC IMR2.4 TAF IMR2.3 LOTC IMR2.2 RCMF IMR2.1 TSLIP IMR2.0 RCMF NAME AND DESCRIPTION Receive CAS Multiframe. 0 = interrupt masked 1 = interrupt enabled Receive Align Frame. 0 = interrupt masked 1 = interrupt enabled Transmit Multiframe. 0 = interrupt masked 1 = interrupt enabled One Second Timer.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 7. ERROR COUNT REGISTERS The DS21354/DS21554 have a set of four counters that record bipolar or code violations, errors in the CRC4 SMF codewords, E bits as reported by the far end, and word errors in the FAS. Each of these four counters is automatically updated on either one-second boundaries (CCR2.7 = 0) or every 62.5ms (CCR2.7 = 1) as determined by the timer in Status Register 2 (SR2.4).
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 7.2. CRC4 Error Counter CRC4 Count Register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 10-bit counter that records word errors in the Cyclic Redundancy Check 4 (CRC4). Since the maximum CRC4 count in a one second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multiframe sync occurs at the CAS level.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 7.4. FAS Error Counter FAS Count Register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 12–bit counter that records word errors in the Frame Alignment Signal in time slot 0. This counter is disabled when RLOS is high. FAS errors will not be counted when the framer is searching for FAS alignment and/or synchronization at either the CAS or CRC4 multiframe level.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 8. DS0 MONITORING FUNCTION Each framer in the DS21354/DS21554 can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR4 register. In the receive direction, the RCM0 to RCM4 bits in the CCR5 register need to be properly set.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TDS0M: TRANSMIT DS0 MONITOR REGISTER (Address = A9 Hex) (MSB) B1 B2 B3 B4 B5 B6 SYMBOL POSITION B1 TDS0M.7 B2 B3 B4 B5 B6 B7 TDS0M.6 TDS0M.5 TDS0M.4 TDS0M.3 TDS0M.2 TDS0M.1 B8 TDS0M.0 B7 (LSB) B8 NAME AND DESCRIPTION Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be transmitted). Transmit DS0 Channel Bit 2. Transmit DS0 Channel Bit 3. Transmit DS0 Channel Bit 4. Transmit DS0 Channel Bit 5. Transmit DS0 Channel Bit 6.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers RDS0M: RECEIVE DS0 MONITOR REGISTER (Address = AB Hex) (MSB) B1 B2 B3 B4 B5 B6 SYMBOL B1 B2 B3 B4 B5 B6 B7 B8 POSITION RDS0M.7 RDS0M.6 RDS0M.5 RDS0M.4 RDS0M.3 RDS0M.2 RDS0M.1 RDS0M.0 B7 (LSB) B8 NAME AND DESCRIPTION Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit received). Receive DS0 Channel Bit 2. Receive DS0 Channel Bit 3. Receive DS0 Channel Bit 4. Receive DS0 Channel Bit 5. Receive DS0 Channel Bit 6. Receive DS0 Channel Bit 7.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 9. SIGNALING OPERATION The DS21354/DS21554 contain provisions for both processor-based (i.e., software-based) signaling bit access and for hardware-based access. Both the processor-based access and the hardware-based access can be used simultaneously if necessary. The processor-based signaling is covered in Section 9.1 and the hardware based signaling is covered in Section 9.2. When referring to signaling, the voice-channel numbering scheme is used. 9.1.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Each Receive Signaling Register (RS1 to RS16) reports the incoming signaling from two time slots. The bits in the Receive Signaling Registers are updated on multiframe boundaries so the user can utilize the Receive Multiframe Interrupt in the Receive Status Register 2 (SR2.7) to know when to retrieve the signaling bits. The user has a full 2ms to retrieve the signaling bits before the data is lost. The RS registers are updated under all conditions.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers the TSRs before the old data is retransmitted. ITU specifications recommend that the ABCD signaling not be set to all zeros because they will emulate a CAS multiframe alignment word. The TS1 register is special because it contains the CAS multiframe alignment word in its upper nibble. The upper nibble must always be set to 0000 or else the terminal at the far end loses multiframe synchronization.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 9.2.2. Transmit Side Via the THSE control bit (CCR3.2), the DS21354/DS21554 can be set up to take the signaling data presented at the TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The hardware signaling insertion capabilities of each framer are available whether the transmit-side elastic store is enabled or disabled.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 10. PER-CHANNEL CODE GENERATION AND LOOPBACK The DS21354/DS21554 can replace data on a channel-by-channel basis in both the transmit and receive directions. The transmit direction is from the backplane to the E1 line and is covered in Section 10.1. The receive direction is from the E1 line to the backplane and is covered in Section 10.2. 10.1.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address = 2A Hex) (MSB) TIDR7 TIDR6 TIDR5 TIDR4 TIDR3 TIDR2 SYMBOL TIDR7 TIDR0 10.1.2. POSITION TIDR.7 TIDR.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 10.2. Receive-Side Code Generation On the receive side, the Receive Channel Control Registers (RCC1/2/3/4) are used to determine which of the 32 E1 channels off of the E1 line and going to the backplane should be overwritten with the code placed in the Receive Channel Registers (RC1 to RC32). This method allows a different 8–bit code to be placed into each of the 32 E1 channels.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 11. CLOCK BLOCKING REGISTERS The receive-channel blocking registers (RCBR1/RCBR2/RCBR3/RCBR4) and the transmit-channel blocking registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins, respectively. (The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low during individual channels). These outputs can be used to block clocks to a USART or LAPD controller in ISDN–PRI applications.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TCBR1/TCBR2/TCBR3/TCBR4: DEFINITION WHEN CCR3.6 = 1 (MSB) CH18 CH3 CH17 CH2 CH16 CH1 1* CH22 CH7 CH21 CH6 CH20 CH5 CH19 CH26 CH11 CH25 CH10 CH24 CH9 CH23 CH30 CH15 CH29 CH14 CH28 CH13 CH27 (LSB) 1* CH4 CH8 CH12 TCBR1(22) TCBR2(23) TCBR3(24) TCBR4(25) *These bits should be set to one to allow the internal TS1 register to create the CAS Multiframe Alignment Word and Spare/Remote Alarm bits.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 12. ELASTIC STORES OPERATION The DS21354/DS21554 contain dual two-frame (512 bits) elastic stores, one for the receive direction and one for the transmit direction. These elastic stores have two main purposes. First, they can be used to rate convert the E1 data stream to 1.544Mbps (or a multiple of 1.544Mbps), which is the T1 rate.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 13. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION The DS21354/DS21554 provide for access to both the Sa and the Si bits through three different methods. The first method is accomplished via a hardware scheme using the RLINK/RLCLK and TLINK/TLCLK pins (see Section 13.1). The second method involves using the internal RAF/RNAF and TAF/TNAF registers (see Section 13.2). The third method, which is covered in Section 13.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers RAF: RECEIVE ALIGN FRAME REGISTER (Address = 2F Hex) (MSB) Si 0 0 1 1 0 SYMBOL Si 0 0 1 1 0 1 1 POSITION RAF.7 RAF.6 RAF.5 RAF.4 RAF.3 RAF.2 RAF.1 RAF.0 POSITION RNAF.7 RNAF.6 RNAF.5 RNAF.4 RNAF.3 RNAF.2 RNAF.1 RNAF.0 POSITION TAF.7 TAF.6 TAF.5 TAF.4 TAF.3 TAF.2 TAF.1 TAF.0 Sa7 (LSB) Sa8 NAME AND DESCRIPTION International Bit. Frame Non-Alignment Signal Bit. Remote Alarm. Additional Bit 4. Additional Bit 5. Additional Bit 6. Additional Bit 7.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TNAF: TRANSMIT NON-ALIGN FRAME REGISTER (Address = 21 Hex) (MSB) Si 1 A Sa4 Sa5 Sa6 Sa7 SYMBOL Si 1 A Sa4 Sa5 Sa6 Sa7 Sa8 POSITION TNAF.7 TNAF.6 TNAF.5 TNAF.4 TNAF.3 TNAF.2 TNAF.1 TNAF.0 (LSB) Sa8 NAME AND DESCRIPTION International Bit. Frame Non-Alignment Signal Bit. Remote Alarm (used to transmit the alarm). Additional Bit 4. Additional Bit 5. Additional Bit 6. Additional Bit 7. Additional Bit 8.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TSaCR: TRANSMIT Sa BIT CONTROL REGISTER (Address = 1C Hex) (MSB) SiAF SiNAF RA Sa4 Sa5 Sa6 SYMBOL POSITION SiAF TSaCR.7 SiNAF TSaCR.6 RA TSaCR.5 Sa4 TSaCR.4 Sa5 TSaCR.3 Sa6 TSaCR.2 Sa7 TSaCR.1 Sa8 TSaCR.0 Sa7 (LSB) Sa8 NAME AND DESCRIPTION International Bit in Align Frame Insertion Control Bit.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 14. HDLC CONTROLLER FOR THE Sa BITS OR DS0 The DS21354/DS21554 can extract/insert data from/into the Sa bit positions (Sa4 to Sa8) or from/to any multiple of DS0 or sub-DS0 channels. The SCT contains a complete HDLC controller (see Section 14). 14.1.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 14.2. HDLC Status Registers Three of the HDLC controller registers (HSR, RHIR, and THIR) provide status information. When a particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one. Some of the bits in these three status registers are latched and some are real time bits that are not latched. Section 14.4 contains register descriptions that list which bits are latched and which are not.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 14.3. Basic Operation Details As a basic guideline for interpreting and sending HDLC messages, the following sequences can be applied: 14.3.1. Example: Receive an HDLC Message 1. 2. 3. 4. Enable RPS interrupts Wait for interrupt to occur Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt Read RHIR to obtain REMPTY status a. If REMPTY=0, then record OBYTE, CBYTE, and POK bits and then read the FIFO a1.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 14.4. HDLC Register Description HCR: HDLC CONTROL REGISTER (Address = B0 Hex) (MSB) — RHR TFS THR TABT SYMBOL — POSITION HCR.7 RHR HCR.6 TFS HCR.5 THR HCR.4 TABT HCR.3 TEOM HCR.2 TZSD HCR.1 TCRCD HCR.0 TEOM TZSD (LSB) TCRCD NAME AND DESCRIPTION Not Assigned. Should be set to zero when written. Receive HDLC Reset. A 0-to-1 transition will reset the HDLC controller. Must be cleared and set again for a subsequent reset.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers HSR: HDLC STATUS REGISTER (Address = B1 Hex) (MSB) FRCL RPE RPS RHALF RNE SYMBOL POSITION FRCL HSR.7 RPE HSR.6 RPS HSR.5 RHALF HSR.4 RNE HSR.3 THALF HSR.2 TNF HSR.1 TMEND HSR.0 THALF TNF (LSB) TMEND NAME AND DESCRIPTION Framer Receive Carrier Loss. Set when 255 (or 2048 if CCR3.0 = 1) consecutive zeros have been detected at RPOSI and RNEGI. Receive Packet End.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers HIMR: HDLC INTERRUPT MASK REGISTER (Address = B2 Hex) (MSB) FRCL RPE RPS RHALF RNE THALF SYMBOL POSITION FRCL HIMR.7 RPE HIMR.6 RPS HIMR.5 RHALF HIMR.4 RNE HIMR.3 THALF HIMR.2 TNF HIMR.1 TMEND HIMR.0 NAME AND DESCRIPTION Framer Receive Carrier Loss. 0 = interrupt masked 1 = interrupt enabled Receive Packet End. 0 = interrupt masked 1 = interrupt enabled Receive Packet Start.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers RHIR: RECEIVE HDLC INFORMATION REGISTER (Address = B3 Hex) (MSB) RABT RCRCE ROVR RVM REMPTY POK CBYTE SYMBOL POSITION RABT RHIR.7 RCRCE RHIR.6 ROVR RHIR.5 RVM RHIR.4 REMPTY RHIR.3 POK RHIR.2 CBYTE RHIR.1 OBYTE RHIR.0 (LSB) OBYTE NAME AND DESCRIPTION Abort Sequence Detected. Set whenever the HDLC controller sees 7 or more ones in a row. CRC Error. Set when the CRC checksum is in error. Overrun.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers THIR: TRANSMIT HDLC INFORMATION REGISTER (Address = B6 Hex) (MSB) — — — — — TEMPTY TFULL SYMBOL — — — — — POSITION THIR.7 THIR.6 THIR.5 THIR.4 THIR.3 TEMPTY THIR.2 TFULL THIR.1 TUDR THIR.0 (LSB) TUDR NAME AND DESCRIPTION Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read. Not Assigned. Could be any value when read.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers RDC1: RECEIVE HDLC DS0 CONTROL REGISTER 1 (Address = B8 Hex) (MSB) RHS RSaDS RDS0M RD4 RD3 RD2 RD1 SYMBOL POSITION RHS RDC1.7 RSaDS RDC1.6 RDS0M RDC1.5 RD4 RD3 RD2 RD1 RD0 RDC1.4 RDC1.3 RDC1.2 RDC1.1 RDC1.0 NAME AND DESCRIPTION Receive HDLC source 0 = Sa bits defined by RCR2.3 to RCR2.7. 1 = Sa bits or DS0 channels defined by RDC1 (see bits defined below). Receive Sa Bit/DS0 Select. 0 = route Sa bits to the HDLC controller.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TDC1: TRANSMIT HDLC DS0 CONTROL REGISTER 1 (Address = BA Hex) (MSB) THE TSaDS TDS0M TD4 TD3 TD2 TD1 SYMBOL POSITION THE TDC1.7 TSaDS TDC1.6 TDS0M TDC1.5 TD4 TD3 TD2 TD1 TD0 TDC1.4 TDC1.3 TDC1.2 TDC1.1 TDC1.0 NAME AND DESCRIPTION Transmit HDLC Enable.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 15. LINE INTERFACE FUNCTIONS The line interface function in the DS21354/DS21554 contains three sections: (1) the receiver, which handles clock and data recovery; (2) the transmitter, which waveshapes and drives the E1 line; and (3) the jitter attenuator. Each of these three sections is controlled by The Line Interface Control Register (LICR) contrlls each of these three sections.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 15.1. Receive Clock and Data Recovery The DS21354/DS21554 contain a digital clock recovery system. See Figure 2-1 and Figure 15-1 for more details. The device couples to the receive-E1-shielded twisted pair or coax via a 1:1 transformer. See Table 15-3 for transformer details. The 2.048MHz clock attached at the MCLK pin is internally multiplied by 16 via an internal PLL and fed to the clock recovery system.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Table 15-2. Line Build-Out Select in LICR for the DS21354 L2 0 0 0 0 1 1 L1 0 0 1 1 0 0 L0 0 1 0 1 0 1 APPLICATION 75W normal 120W normal 75W with protection resistors 120W with protection resistors 75W with high return loss 120W with high return loss TRANSFORMER 1:2 step-up 1:2 step-up 1:2 step-up 1:2 step-up 1:2 step-up 1:2 step-up RETURN LOSS (dB)* N.M. N.M. N.M. N.M. 21 21 RT (W)** 0 0 2.5 2.5 6.2 11.6 * N.M.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 15-1. Basic External Analog Connections 0.47 (nonpolarized) DS21354/DS21554 DVDD TTIP TRING DVSS Rt E1 Transmit Line VDD Rt N:1 (See Note 1) 0.01 0.1 RVDD RVSS 1:1 TVDD RTIP E1 Receive Line TVSS 0.1 0.1 + 10 RRING Rr Rr MCLK 0.1mF NOTE 1: ALL CAPACITORS VALUES ARE IN mF. NOTE 2: 10mF CAPACITOR ON TVDD IS OF TANTALUM CONSTRUCTION. NOTE 3: SEE TABLE 15-3 FOR TRANSFORMER SELECTION. Figure 15-2.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 15-3. Jitter Tolerance UNIT INTERVALS (UIpp) 1K 100 DS21354/ DS21554 Tolerance 40 10 1.5 1 0.1 Minimum Tolerance Level as per ITU G.823 1 10 20 0.2 100 1K FREQUENCY (Hz) 2.4K 10K 18K 100K Figure 15-4. Jitter Attenuation ITU G.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 15-5. Transmit Waveform Template 1.2 1.1 269ns (in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) SCALED AMPLITUDE 1.0 0.9 0.8 0.7 G.703 Template 194ns 0.6 0.5 219ns 0.4 0.3 0.2 0.1 0 -0.1 -0.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 15.4. Protected Interfaces In certain applications, such as connecting to the PSTN, it is required that the network interface be protected from and resistant to certain electrical conditions. These conditions are divided into two categories, surge and power line cross. A typical cause of surge is lightening strike. Power-line cross refers to accidental contact with high-voltage power wiring.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 15-6. Protected Interface Example for the DS21554 +5V D1 Fuse Transmit Line R1 N:1 Rt S R2 Fuse X1 Rt C2 DS21554 D2 C1 D3 TTIP DVDD TRING DVSS D4 Receive Line R3 1:1 RTIP 470 RRING Fuse X2 Rterm 0.1 RVDD 470 R4 0.01 + RVSS Fuse +5.0V TVDD 0.1 0.1 + 10 TVSS MCLK 2.048MHz Rterm 0.1 NOTE 1: ALL CAPACITOR VALUES ARE IN mF. NOTE 2: THE 10mF CAPACITOR ON TVDD IS OF TANTALUM CONSTRUCTION.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 15-7. Protected Interface Example for the DS21354 +3.3V D1 Fuse Transmit Line S Fuse C2 C1 X1 DS21354 D2 2:1 D3 +3.3V TTIP DVDD TRING DVSS D4 0.01 0.1 + RVDD 0.1 RVSS Fuse 1:1 470 RTIP Receive Line 470 RRING Fuse X2 TVDD TVSS MCLK 37/60 0.1 + 10 2.048MHz 37/60 0.1 NOTE 1: ALL CAPACITOR VALUES ARE IN mF. NOTE 2: THE 10mF CAPACITOR ON TVDD IS OF TANTALUM CONSTRUCTION.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 15.5. Receive Monitor Mode When connecting to a monitor port, a large resistive loss is incurred due to the voltage divider between the E1 line termination resistors (Rt) and the monitor port isolation resistors (Rm), as shown in Figure 15-8. The receiver of the DS21354/DS21554 can provide gain to overcome the resistive loss of a monitor connection.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 16. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT The DS21354/DS21554 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. See Figure 16-1. The device contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 16-1.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 16-2. Test-Logic-Reset Upon power up, the TAP Controller will be in the Test-Logic-Reset state. The Instruction register will contain the IDCODE instruction. All system logic of the device will operate normally. Run-Test-Idle The Run-Test-Idle is used between scan operations or during specific tests.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and will initiate a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the Test-Logic-Reset state.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 16-2.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 16.1. Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial output at JTDO.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output. The ID code will always have a one in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Table 16-4. Boundary Scan Control Bits BIT 2 — 1 — — 0 — — — — 72 71 70 69 68 — — — — — — — 67 — 66 — — — — — — — 65 64 63 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Note 1: Note 2: Note 3: NAME RCHBLK JTMS 8MCLK JTCLK JTRST RCL JTDI N.C. N.C. JTDO BTS LIUC 8XCLK TEST N.C. RTIP RRING RVDD RVSS RVSS MCLK XTALD N.C.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 17. INTERLEAVED PCM BUS OPERATION In many architectures, the outputs of individual framers are combined into higher speed serial buses to simplify transport across the system. The DS21354/DS21554 can be configured to allow data and signaling buses to be multiplexed into higher speed data and signaling buses eliminating external hardware saving board space and cost. The interleaved PCM bus option (IBO) supports two bus speeds. The 4.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 17-1. IBO Basic Configuration Using Four SCTs CI RSYSCLK TSYSCLK MASTER SCT RSYNC TSSYNC RSIG TSIG TSER RSER CO CI RSYSCLK TSYSCLK RSYNC TSSYNC SLAVE #2 RSIG TSIG TSER RSER CO 8.192MHz System Clock In System 8KHz Frame Sync In PCM Signaling Out PCM Signaling In PCM Data In PCM Data Out CI RSYSCLK TSYSCLK RSYNC TSSYNC SLAVE #1 CO RSIG TSIG TSER RSER CI RSYSCLK TSYSCLK RSYNC TSSYNC SALVE #3 CO RSIG TSIG TSER RSER 17.1.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 18. FUNCTIONAL TIMING DIAGRAMS 18.1. Receive Figure 18-1. Receive-Side Timing 1 FRAME# 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 RFSYNC RSYNC 1 2 RSYNC RLCLK RLINK 3 4 NOTE 1: RSYNC IN FRAME MODE (RCR1.6 = 0). NOTE 2: RSYNC IN MULTIFRAME MODE (RCR1.6 = 1). NOTE 3: RLCLK IS PROGRAMMED TO OUTPUT JUST THE SA BITS. NOTE 4: RLINK WILL ALWAYS OUTPUT ALL FIVE SA BITS AS WELL AS THE REST OF THE RECEIVE DATA STREAM.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-3. Receive-Side 1.544MHz Boundary Timing (with Elastic Store Enabled) RSYSCLK CHANNEL 23/31 1 RSER CHANNEL 24/32 CHANNEL 1/2 LSB LSB MSB F MSB RSYNC2 RMSYNC 3 RSYNC RCHCLK RCHBLK 4 NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS (MAPPED TO CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED TO ON1). NOTE 2: RSYNC IN THE OUTPUT MODE (RCR1.5 = 0).
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-5.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-6.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 18.2. Transmit Figure 18-7. Transmit-Side Timing FRAME# 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 1 TSYNC TSSYNC 2 TSYNC TLCLK 3 3 TLINK NOTE 1: TSYNC IN FRAME MODE (TCR1.1 = 0). NOTE 2: TSYNC IN MULTIFRAME MODE (TCR1.1 = 1). NOTE 3: TLINK IS PROGRAMMED TO SOURCE JUST THE SA4 BIT. NOTE 4: THIS DIAGRAM ASSUMES BOTH THE CAS MF AND THE CRC4 MF BEGIN WITH THE TAF FRAME.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-9. Transmit-Side 1.544MHz Boundary Timing (with Elastic Store Enabled) TSYSCLK CHANNEL 23 CHANNEL 24 1 CHANNEL 1 LSB MSB TSER LSB F MSB TSSYNC TCHCLK TCHBLK 2 NOTE 1: THE F-BIT POSITION IN THE TSER DATA IS IGNORED. NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. Figure 18-10. Transmit-Side 2.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-11.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-12.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-13. G.802 Timing TS # 31 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 RSYNC TSYNC RCHCLK TCHCLK RCHBLK TCHBLK NOTE: RCHBLK OR TCHBLK PROGRAMMED TO PULSE HIGH DURING TIME SLOTS 1 THROUGH 15, 17 THROUGH 25, AND BIT 1 OF TIME SLOT 26.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-14. DS21354/DS21554 Framer Synchronization Flowchart Power Up RLOS = 1 FAS Search FASSA = 1 RLOS = 1 FAS Sync Criteria Met FASSA = 0 Resync if RCR1.1 = 0 Increment CRC4 Sync Counter; CRC4SA = 0 8ms Time Out CRC4 Multiframe Search (if enabled via CCR1.0) CRC4SA = 1 CRC4 Sync Criteria Met; CRC4SA = 0; Reset CRC4 Sync Counter Set FASRC (RIR.1) CRC4 Resync Criteria Met (RIR.2) CAS Resync Criteria Met; Set CASRC (RIR.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 18-15. DS21354/DS21554 Transmit Data Flow TSER & TDATA HDLC ENGINE TNAF.0-4 0 Sa Data Source MUX (TDC1) 1 0 1 DS0 Data Source MUX (TDC1/2) TAF 0 TAF/TNAF Bit MUX RSER (note #1) TLINK TNAF.5-7 TC1 to TC32 1 0 1 Per-Channel Code Generation (TCC1/2/3/4) 0 1 Timeslot 0 Pass-Through (TCR1.6) 1 0 Si Bit Insertion Control (TCR1.3) Receive Side CRC4 Error Detector CRC4 Multiframe Alignment Word Generation (CCR.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 19. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground………………………………………………………………-1.0V to +6.0V Operating Temperature Range for DS21354L/DS21554L……………………………………………………0°C to +70°C Operating Temperature Range for DS21354LN/DS21554LN……………………………………………..-40°C to +85°C Storage Temperature Range………………………………………………………………………………...-55°C to +125°C Soldering Temperature………………………………………………………..
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 20. AC TIMING PARAMETERS AND DIAGRAMS 20.1. Multiplexed Bus AC Characteristics AC CHARACTERISTICS—MULTIPLEXED PARALLEL PORT (MUX = 1) (VDD = 3.3V ±5%, TA = 0°C to +70°C; for DS21354L; VDD = 5.0V ±5%, TA = 0°C to +70°C for DS21554L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21354LN; VDD = 5.0V ±5%, TA = -40°C to +85°C for DS21554LN.) (See Figure 20-1 to Figure 20-3.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 20-1. Intel Bus Read Ac Timing (BTS = 0/MUX = 1) t CYC ALE PWASH t ASD WR t ASD RD PWEL t ASED PWEH t CH t CS CS t ASL t DHR t DDR AD0–AD7 t AHL Figure 20-2.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 20-3.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 20.2. Nonmultiplexed Bus AC Characteristics AC CHARACTERISTICS—NONMULTIPLEXED PARALLEL PORT (MUX = 0) (VDD = 3.3V ±5%, TA = 0°C to +70°C; for DS21354L; VDD = 5.0V ±5%, TA = 0°C to +70°C for DS21554L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21354LN; VDD = 5.0V ±5%, TA = -40°C to +85°C for DS21554LN.) (See Figure 20-4 to Figure 20-7.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 20-5. Intel Bus Write AC Timing (BTS = 0/MUX = 0) A0–A7 ADDRESS VALID D0–D7 t7 10ns MIN RD t1 CS 0ns MIN t8 10ns MIN 0ns MIN t2 t6 75ns MIN WR t4 0ns MIN Figure 20-6. Motorola Bus Read AC Timing (BTS = 1/MUX = 0) ADDRESS VALID A0–A7 DATA VALID D0–D7 5ns MIN/20ns MAX t5 R/W t1 CS 0ns MIN 0ns MIN t2 t3 t4 0ns MIN 75ns MAX DS Figure 20-7.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 20.3. Receive-Side AC Characteristics AC CHARACTERISTICS—RECEIVE SIDE (VDD = 3.3V ±5%, TA = 0°C to +70°C; for DS21354L; VDD = 5.0V ±5%, TA = 0°C to +70°C for DS21554L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21354LN; VDD = 5.0V ±5%, TA = -40°C to +85°C for DS21554LN.) (See Figure 20-8 to Figure 20-10.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 20-8. Receive-Side AC Timing RCLK t D1 MSB of Channel 1 RSER / RDATA / RSIG t D2 RCHCLK t D2 RCHBLK t D2 RFSYNC / RMSYNC t D2 RSYNC1 t D2 2 RLCLK t D1 RLINK Sa4 to Sa8 Bit Position Notes: 1. RSYNC is in the output mode (RCR1.5 = 0). 2. RLCLK will only pulse high during Sa bit locations as defined in RCR2; no relationship between RLCLK and RSYNC or RFSYNC is implied.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 20-9. Receive System Side AC Timing t SL tF tR RSYSCLK t SH tSP t D3 MSB of Channel 1 RSER / RSIG tD4 RCHCLK tD4 RCHBLK t D4 RMSYNC / CO t D4 RSYNC1 t HD t SU RSYNC2 t SC t WC CI Notes: 1. RSYNC is in the output mode (RCR1.5 = 0) 2. RSYNC is in the input mode (RCR1.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 20-10.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 20.4. Transmit AC Characteristics AC CHARACTERISTICS—TRANSMIT SIDE (VDD = 3.3V ±5%, TA = 0°C to +70°C; for DS21354L; VDD = 5.0V ±5%, TA = 0°C to +70°C for DS21554L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21354LN; VDD = 5.0V ±5%, TA = -40°C to +85°C for DS21554LN.) (See Figure 20-11 to Figure 20-13.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 20-11. Transmit-Side AC Timing t CP t CL tF tR t CH TCLK t D1 TESO t SU TSER / TSIG / TDATA t HD t D2 TCHCLK t D2 TCHBLK t D2 TSYNC1 t SU t HD TSYNC2 5 TLCLK t D2 t HD TLINK t SU Notes: 1. TSYNC is in the output mode (TCR1.0 = 1). 2. TSYNC is in the input mode (TCR1.0 = 0). 3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled. 4.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers Figure 20-12. Transmit System Side AC Timing t SP t SL tF tR t SH TSYSCLK t SU TSER t D3 t HD TCHCLK / CO t D3 TCHBLK t HD t SU TSSYNC t WC t SC CI Notes: 1. TSER is only sampled on the falling edge of TSYSCLK when the transmit side elastic store is enabled. 2. TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit side elastic store is enabled. Figure 20-13.
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers 21. PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied.