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DS21455/DS21458

Quad T1/E1/J1 Transceivers

1 of 269

REV: 051507

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata

www.maxim-ic.com

GENERAL DESCRIPTION

The DS21455 and DS21458 are quad monolithic

devices featuring independent transceivers that can

be software configured for T1, E1, or J1 operation.

Each is composed of a line interface unit (LIU),

framer, HDLC controllers, and a TDM backplane

interface, and is controlled via an 8-bit parallel port

configured for Intel or Motorola bus operations. The

DS21455* is a direct replacement for the older

DS21Q55 quad MCM device. The DS21458, in a

smaller package (17mm CSBGA) and featuring an

improved controller interface, is software compatible

with the older DS21Q55.

*The JTAG function on the DS21455/DS21458 is a single

controller for all four transceivers, unlike the DS21Q55, which has

a JTAG controller-per-transceiver architecture.

APPLICATIONS

Routers

Channel Service Units (CSUs)

Data Service Units (DSUs)

Muxes

Switches

Channel Banks

T1/E1 Test Equipment

ORDERING INFORMATION

PART TEMP RANGE PIN-PACKAGE

DS21455

0°C to +70°C

256 BGA

(27mm x 27mm)

DS21455+ 0°C to +70°C

256 BGA

(27mm x 27mm)

DS21455N -40°C to +85°C

256 BGA

(27mm x 27mm)

DS21455N+

-40°C to +85°C

256 BGA

(27mm x 27mm)

DS21458

0°C to +70°C

256 CSBGA

(17mm x 17mm)

DS21458+ 0°C to +70°C

256 CSBGA

(17mm x 17mm)

DS21458N -40°C to +85°C

256 CSBGA

(17mm x 17mm)

DS21458N+ -40°C to +85°C

256 CSBGA

(17mm x 17mm)

FEATURES

Four Independent Transceivers, Each Having the

Following Features:

 Complete T1 (DS1)/ISDN-PRI/J1 Transceiver

Functionality

 Complete E1 (CEPT) PCM-30/ISDN-PRI

Transceiver Functionality

 Short- and Long-Haul Line Interface for

Clock/Data Recovery and Waveshaping

 CMI Coder/Decoder

 Crystal-Less Jitter Attenuator

 Fully Independent Transmit and Receive

Functionality

 Dual HDLC Controllers

 On-Chip Programmable BERT Generator and

Detector

 Internal Software-Selectable Receive- and

Transmit-Side Termination Resistors for

75Ω/100Ω/120Ω T1 and E1 Interfaces

 Dual Two-Frame Elastic-Store Slip Buffers that

can Connect to Asynchronous Backplanes Up to

16.384MHz

 16.384MHz, 8.192MHz, 4.096MHz, or

2.048MHz Clock Output Synthesized to

Recovered Network Clock

 Programmable Output Clocks for Fractional T1,

E1, H0, and H12 Applications

 Interleaving PCM Bus Operation

 8-Bit Parallel Control Port, Multiplexed or

Nonmultiplexed, Intel or Motorola

 IEEE 1149.1 JTAG-Boundary Scan

 3.3V Supply with 5V Tolerant Inputs and

Outputs

 DS21455 Directly Replaces DS21Q55

 Signaling System 7 (SS7) Support

 RAI-CI, AIS-CI Support

+ Denotes a lead(Pb)-free/RoHS-compliant package.

Summary of content (269 pages)

PAGE 1
DS21455/DS21458 Quad T1/E1/J1 Transceivers www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS21455 and DS21458 are quad monolithic devices featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer, HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or Motorola bus operations.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers DOCUMENT REVISION HISTORY REVISION 040804 091304 101304 042105 CHANGES New Product Release. 1. An incorrect Device ID was shown in the IDR register. A table was added to clearly show the Device IDs for the DS21455 and DS21458. 2. Corrected multiple incorrect pin names in Figure 5-2. The pin names were changed to match the correct pin names shown in Table 5-2. Pin A1 was changed from TNEG0 to TNEGO3. Pin F11 was changed from TLINK3 to TLINK2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers TABLE OF CONTENTS 1. DESCRIPTION ............................................................................................................................................... 9 STANDARDS ...................................................................................................................... 10 2. FEATURE HIGHLIGHTS.............................................................................................................................. 11 2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 13. I/O PIN CONFIGURATION OPTIONS......................................................................................................... 78 14. LOOPBACK CONFIGURATIONS ............................................................................................................... 80 14.1 PER-CHANNEL PAYLOAD LOOPBACK .................................................................................. 83 15. ERROR COUNT REGISTERS.......................................
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 24.5.1 Receive Section ............................................................................................................155 24.5.2 Transmit Section ...........................................................................................................157 24.6 D4/SLC-96 OPERATION .................................................................................................. 157 25. LINE INTERFACE UNIT (LIU) .........................................
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DS21455/DS21458 Quad T1/E1/J1 Transceivers LIST OF FIGURES Figure 3-1. DS21458 Block Diagram ......................................................................................................................... 15 Figure 3-2. DS21455 Block Diagram ......................................................................................................................... 16 Figure 4-1. DS21455 Framer/LIU Interim Signals .......................................................................................
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 38-2. Intel Bus Write Timing (BTS = 0 / MUX = 1) ....................................................................................... 254 Figure 38-3. Motorola Bus Timing (BTS = 1 / MUX = 1).......................................................................................... 255 Figure 38-4. Intel Bus Read Timing (BTS = 0 / MUX = 0) ....................................................................................... 257 Figure 38-5.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers LIST OF TABLES Table 5-1. DS21455 Pin Description ......................................................................................................................... 29 Table 5-2. DS21458 Pin Description ......................................................................................................................... 34 Table 6-1. Register Map Sorted By Address ...........................................................................................
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 1. DESCRIPTION The DS21455 and DS21458 are quad monolithic devices featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each is composed of a line interface unit (LIU), framer, HDLC controllers, and a TDM backplane interface, and is controlled via an 8-bit parallel port configured for Intel or Motorola bus operations. The DS21455* is a direct replacement for the older DS21Q55 quad MCM device.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers The parallel port provides access for control and configuration of all the DS21455/DS21458’s features. The Extended System Information Bus (ESIB) function allows up to eight transceivers, two DS21455s or two DS21458s to be accessed via a single read for interrupt status or other user-selectable alarm status information. Diagnostic capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code generation and detection.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 2. FEATURE HIGHLIGHTS 2.1 General       DS21455: 27mm, 1.27 pitch BGA, compatible replacement for the DS21Q55 DS21458: 17mm, 1.00 pitch CSBGA 3.3V supply with 5V tolerant inputs and outputs Evaluation kits IEEE 1149.1 JTAG-boundary scan Driver source code available from the factory 2.2 Line Interface                       Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be 2.048MHz, 4.096MHz, 8.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 2.4 Jitter Attenuator     32-bit or 128-bit crystal-less jitter attenuator Requires only a 2.048MHz master clock for both E1 and T1 operation with the option to use 1.544MHz for T1 operation Can be placed in either the receive or transmit path or disabled Limit trip indication 2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 2.6 System Interface         Dual two-frame, independent receive and transmit elastic stores  Independent control and clocking  Controlled-slip capability with status  Minimum-delay mode supported Supports T1 to E1 conversion Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode Programmable output clocks for fractional T1, E1, H0, and H12 applications Interleaving PCM bus operation with rates of 4.096MHz, 8.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 2.9 Extended System Information Bus  Host can read interrupt and alarm status on up to eight ports (two devices) with a single-bus read 2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 3. BLOCK DIAGRAM Figure 3-1 shows a simplified block diagram highlighting the major components of the DS21458 and DS21455. Figure 3-1.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 3-2. DS21455 Block Diagram MCLK1 MCLK2 TRANSCEIVER #4 TRANSCEIVER #3 TRANSCEIVER #2 RPOSO RPOSI RNEGO RNEGI RCLKO RCLKI 2 HDLCs MASTER CLOCK MUX CLOCK & DATA RECOVERY RRING JITTER ATTEN.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 4. DS21455/DS21458 DELTA This section describes the differences between the DS21455 and DS21458. 4.1 Package DS21455: 27mm, 256-pin, 1.27 ball pitch, BGA (This package has the same footprint and pinout as the DS21Q55.) DS21458: 17mm, 256-pin, 1.00 ball pitch, CSBGA 4.2 Controller Interface DS21455: The CPU interface has 8 address lines with independent chip selects (4) per transceiver. DS21458: The CPU interface has 10 address lines with a single chip select.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 4-1.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 4-2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 5. PIN FUNCTION DESCRIPTION 5.1 Transmit Side Pins Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 1.544 MHz or a 2.048MHz primary clock. Used to clock data through the transmit-side formatter. Signal Name: TSER Signal Description: Transmit Serial Data Signal Type: Input Transmit NRZ serial data. Sampled on the falling edge of TCLK when the transmit-side elastic store is disabled.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Signal Name: TSYNC Signal Description: Transmit Sync Signal Type: Input/Output A pulse at this pin will establish either frame or multiframe boundaries for the transmit side. Can be programmed to output either a frame or multiframe pulse. If this pin is set to output pulses at frame boundaries, it can also be set via IOCR1.3 to output double-wide pulses at signaling frames in T1 mode.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Signal Name: TNEGI (DS21455 Only) Signal Description: Transmit Negative-Data Input Signal Type: Input Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TNEGO by tying the LIUC/TPD pin high. See the LIUC/TPD pin description for a full explanation of the LIUC/TPD function. TPOSI and TNEGI can be tied together in NRZ applications.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Signal Name: RSYNC Signal Description: Receive Sync Signal Type: Input/Output An extracted pulse, one RCLK wide, is output at this pin which identifies either frame (IOCR1.5 = 0) or multiframe (IOCR1.5 = 1) boundaries. If set to output-frame boundaries then via IOCR1.6, RSYNC can also be set to output double-wide pulses on signaling frames in T1 mode. If the receive-side elastic store is enabled, then this pin can be enabled to be an input via IOCR1.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Signal Name: BPCLK Signal Description: Backplane Clock Signal Type: Output A user-selectable synthesized clock output that is referenced to the clock that is output at the RCLK pin. Signal Name: RPOSO Signal Description: Receive Positive-Data Output Signal Type: Output Updated on the rising edge of RCLKO with bipolar data out of the line interface. This pin is normally tied to RPOSI.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Signal Name: MUX Signal Description: Bus Operation Signal Type: Input Set low to select nonmultiplexed bus operation. Set high to select multiplexed bus operation. Signal Name: AD0 to AD7 Signal Description: Data Bus [D0 to D7] or Address/Data Bus Signal Type: Input/Output In nonmultiplexed bus operation (MUX = 0), it serves as the data bus. In multiplexed bus operation (MUX = 1), it serves as an 8-bit, multiplexed address/data bus.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Signal Name: CS (DS21458 Only) Signal Description: Chip Select Signal Type: Input Must be low to read or write to the device. CS is an active-low signal. Signal Name: ALE (AS)/A7 Signal Description: Address Latch Enable (Address Strobe) or A7 Signal Type: Input In nonmultiplexed bus operation (MUX = 0), it serves as the upper address bit. In multiplexed bus operation (MUX = 1), it serves to demultiplex the bus on a positive-going edge.
PAGE 27
DS21455/DS21458 Quad T1/E1/J1 Transceivers Signal Name: JTCLK Signal Description: IEEE 1149.1 Test Clock Signal Signal Type: Input This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. Signal Name: JTDI Signal Description: IEEE 1149.1 Test Data Input Signal Type: Input Test instructions and data are clocked into this pin on the rising edge of JTCLK. This pin has a 10k pullup resistor. Signal Name: JTDO Signal Description: IEEE 1149.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 5.7 Supply Pins Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 3.3V ±5%. Should be tied to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal Type: Supply 3.3V ±5%. Should be tied to the DVDD and TVDD pins. Signal Name: TVDD Signal Description: Transmit Analog Positive Supply Signal Type: Supply 3.3V ±5% Should be tied to the RVDD and DVDD pins.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 5.8 Pin Descriptions Table 5-1.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers PIN B7 B9 H20 L20 N17 J4 C13 C3 U13 W6 F18 D7 T20 V9 B17 A6 J20 U1 Y15 N1 V19 W13 V18 K2 T1 W20 U10 M2 G17 G4 Y12 J1 D14 F3 U14 N3 B13 E3 M18 M4 A15 A4 R17 M3 C14 B4 T17 N2 K4 D17 A2 V14 F1 NAME DVSS DVSS DVSS DVSS DVSS ESIBRD1 ESIBRD2 ESIBRD3 ESIBRD4 ESIBS0_1 ESIBS0_2 ESIBS0_3 ESIBS0_4 ESIBS1_1 ESIBS1_2 ESIBS1_3 ESIBS1_4 INT JTCLK JTDI JTDO JTMS JTRST LIUC/TPD MCLK1 MCLK2 MUX RCHBLK1 RCHBLK2 RCHBLK3 RCHBLK4 RCHCLK1 RCHCLK2 RCHCLK3 RCHCLK4 RCLK1 RCLK2 RCLK3 RCLK4
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DS21455/DS21458 Quad T1/E1/J1 Transceivers PIN A12 D3 K18 G2 A13 A3 U12 H2 E17 E1 V11 L1 D16 F2 W16 R3 D13 A1 P17 L3 B15 C2 U17 R4 B14 B2 V15 L4 A16 B1 U15 Y11 Y14 Y17 Y20 J2 D15 E2 W17 L2 B16 C1 Y18 K1 C15 D2 V16 G1 D12 D1 V12 H1 F17 NAME RLCLK2 RLCLK3 RLCLK4 RLINK1 RLINK2 RLINK3 RLINK4 RLOS/LOTC1 RLOS/LOTC2 RLOS/LOTC3 RLOS/LOTC4 RMSYNC1 RMSYNC2 RMSYNC3 RMSYNC4 RNEGI1 RNEGI2 RNEGI3 RNEGI4 RNEGO1 RNEGO2 RNEGO3 RNEGO4 RPOSI1 RPOSI2 RPOSI3 RPOSI4 RPOSO1 RPOSO2 RPOSO3 RPOSO4 RRING1 RRING2 RRING3 RRING4 RSER1
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DS21455/DS21458 Quad T1/E1/J1 Transceivers PIN G3 W14 Y10 Y13 Y16 Y19 P1 J17 E4 W18 R2 T2 H19 J18 D4 D5 V20 W19 W1 F20 C11 U20 V10 A18 B8 L18 Y9 B19 B10 M19 V6 D19 C8 P20 W7 E18 A7 P19 V3 E20 D6 T18 W5 E19 C6 T19 R1 F19 D8 R20 T3 B20 D9 NAME RSYSCLK3 RSYSCLK4 RTIP1 RTIP2 RTIP3 RTIP4 RVDD RVDD RVDD RVDD RVSS RVSS RVSS RVSS RVSS RVSS RVSS RVSS TCHBLK1 TCHBLK2 TCHBLK3 TCHBLK4 TCHCLK1 TCHCLK2 TCHCLK3 TCHCLK4 TCLK1 TCLK2 TCLK3 TCLK4 TCLKI1 TCLKI2 TCLKI3 TCLKI4 TCLKO1 TCLKO2 TCLKO3 TCLKO4 TLCLK1 TLCLK2 TLCLK3 TL
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DS21455/DS21458 Quad T1/E1/J1 Transceivers PIN N20 W3 C20 A8 R19 V7 C19 C9 N19 Y2 Y4 Y6 Y8 W9 C17 C10 K20 W10 C18 A10 L19 W12 B18 D10 K19 U16 V1 D20 C7 R18 W11 A19 A11 N18 Y1 Y3 Y5 Y7 W2 G19 D11 U19 W4 G18 C5 U18 K3 NAME TNEGO4 TPOSI1 TPOSI2 TPOSI3 TPOSI4 TPOSO1 TPOSO2 TPOSO3 TPOSO4 TRING1 TRING2 TRING3 TRING4 TSER1 TSER2 TSER3 TSER4 TSIG1 TSIG2 TSIG3 TSIG4 TSSYNC1 TSSYNC2 TSSYNC3 TSSYNC4 TSTRST TSYNC1 TSYNC2 TSYNC3 TSYNC4 TSYSCLK1 TSYSCLK2 TSYSCLK3 TSYSCLK4 TTIP1 TTIP2 TTIP3 TTIP4 TVDD TVDD TVDD TVDD TVSS
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Table 5-2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers PIN J9 H5 K16 C10 K13 J15 K14 D9 H4 J12 R8 E9 K9 P3 K3 G10 C7 R11 L2 G11 D7 M9 K8 F10 G5 K12 H9 R1 C14 A2 P14 A10 K4 G14 C6 P11 M2 F15 B6 R12 P2 C15 C3 T15 K5 E15 D6 P12 M3 G13 E6 M10 H10 NAME ESIBS1 INT JTCLK JTDI JTDO JTMS JTRST TPD MCLK1 MCLK2 MUX Unused N.C. N.C.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers PIN J2 H11 F8 P10 G8 J6 H12 F9 N10 L1 F16 A6 T11 J4 H14 C8 P9 K2 G15 B7 R10 L3 F14 E7 N11 K6 E14 B5 N12 J3 H15 B8 R9 K1 G16 A7 T10 H1 J16 A9 T8 N1 J1 M1 E16 H16 D16 A5 A8 A4 T12 T13 T9 NAME RNEGO1 RNEGO2 RNEGO3 RNEGO4 Unused RPOSO1 RPOSO2 RPOSO3 RPOSO4 RRING1 RRING2 RRING3 RRING4 RSER1 RSER2 RSER3 RSER4 RSIG1 RSIG2 RSIG3 RSIG4 RSIGF1 RSIGF2 RSIGF3 RSIGF4 RSYNC1 RSYNC2 RSYNC3 RSYNC4 RSYSCLK1 RSYSCLK2 RSYSCLK3 RSYSCLK4 RTIP1 RTIP2 RTIP3 RTIP4 RVDD RVDD RVDD RVDD RVS
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DS21455/DS21458 Quad T1/E1/J1 Transceivers PIN N2 E13 C5 R13 J7 D15 B4 P13 L5 G12 F6 L9 L6 F12 F7 L11 T2 A15 B2 R16 J14 J13 P1 C16 C4 T14 K7 F11 G7 L12 M5 E12 E5 M12 T1 B15 A1 T16 L4 F13 D5 L10 R2 A16 B1 R15 R4 T4 A13 B13 D1 D2 N15 NAME TCHBLK1 TCHBLK2 TCHBLK3 TCHBLK4 TCHCLK1 TCHCLK2 TCHCLK3 TCHCLK4 TCLK1 TCLK2 TCLK3 TCLK4 Unused Unused Unused Unused TCLKO1 TCLKO2 TCLKO3 TCLKO4 TEST1 TEST2 TLCLK1 TLCLK2 TLCLK3 TLCLK4 TLINK1 TLINK2 TLINK3 TLINK4 Unused Unused Unused Unused TNEGO1 TNEGO2 TNEGO3 TNEGO4 Unused
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DS21455/DS21458 Quad T1/E1/J1 Transceivers PIN N16 M6 G9 G6 K10 L7 E11 F5 K11 M4 D14 A3 M11 K15 N3 B16 B3 R14 H7 J10 D8 L8 R3 T3 A14 B14 C1 C2 P15 P16 R6 T6 A11 B11 F1 F2 L15 L16 R5 T5 A12 B12 E1 E2 M15 M16 C9 NAME TRING4 TSER1 TSER2 TSER3 TSER4 TSIG1 TSIG2 TSIG3 TSIG4 TSSYNC1 TSSYNC2 TSSYNC3 TSSYNC4 TSTRST TSYNC1 TSYNC2 TSYNC3 TSYNC4 TSYSCLK1 TSYSCLK2 TSYSCLK3 TSYSCLK4 TTIP1 TTIP1 TTIP2 TTIP2 TTIP3 TTIP3 TTIP4 TTIP4 TVDD TVDD TVDD TVDD TVDD TVDD TVDD TVDD TVSS TVSS TVSS TVSS TVSS TVSS TVSS TVSS WR (R/W)
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 5.9 Packages The package diagrams below show the lead pattern that will be placed on the target PC board. This is the same pattern that would be seen as viewed from the top. Figure 5-1.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 5-2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 6. PARALLEL PORT The transceiver is controlled via either a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus by an external microcontroller or microprocessor. The transceiver can operate with either Intel or Motorola bus timing configurations. If the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parentheses ().
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DS21455/DS21458 Quad T1/E1/J1 Transceivers ADDRESS 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E REGISTER NAME Per-Channel Data Register 2 Per-Channel Data Register 3 Per-Channel Data Register 4 Information Register 4 Information Register 5 Information Register 6 Information Register 7 HDLC #1 Receive Control HDLC #2 Receive Control E1 Receive Control Register 1 E1 Receive Control Register 2 E1
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DS21455/DS21458 Quad T1/E1/J1 Transceivers ADDRESS 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 REGISTER NAME Transmit Signaling Register 16 Receive Signaling Register 1 Receive Signaling Register 2 Receive Signaling Register 3 Receive Signaling Register 4 Receive Signaling Register 5 Receive Signaling Register 6 Receive Signaling Register 7 Receive Signaling Register 8 Receive Signaling Regist
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DS21455/DS21458 Quad T1/E1/J1 Transceivers ADDRESS 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 REGISTER NAME HDLC #1 Receive Channel Select 3 HDLC #1 Receive Channel Select 4 HDLC #1 Receive Time Slot Bits/Sa Bits Select HDLC #1 Transmit Channel Select1 HDLC #1 Transmit Channel Select 2 HDLC #1 Transmit Channel Select 3 HDLC #1 Transmit Channel Select 4 HDLC #1 Transmit Time Slot Bits/Sa Bits
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DS21455/DS21458 Quad T1/E1/J1 Transceivers ADDRESS C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3–F9, FA–FF REGISTER NAME Receive Si Nonalign Frame Receive Remote Alarm Bits Receive Sa4 Bits Receive Sa5 Bits Receive Sa6 Bits Receive Sa7 Bits Receive Sa8 Bits Transmit Align Frame Register Transmit Nonalign Frame Register Transmit Si Align Frame Transmit Si Nonalign Frame Transmit Remote Alarm Bits Transmit Sa4 Bits Transmit Sa
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 7. SPECIAL PER-CHANNEL REGISTER OPERATION Some of the features described in the data sheet that operate on a per-channel basis use a special method for channel selection. The registers involved are the per-channel pointer registers (PCPR) and per-channel data registers 1 to 4 (PCDR1–4). The user selects the function(s) that are to be applied on a per-channel basis by setting the appropriate bit(s) in the PCPR register.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: PCDR1 Per-Channel Data Register 1 29h Bit # Name Default 7 6 5 4 3 2 1 0 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 Register Name: Register Description: Register Address: PCDR2 Per-Channel Data Register 2 2Ah Bit # Name Default 7 6 5 4 3 2 1 0 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 Register Name: Register Description: Register Address: PCDR3 Per-Channel Data Register 3 2Bh Bit # Nam
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 8. PROGRAMMING MODEL The DS21455/DS21458 register map is divided into three groups: T1 specific features, E1 specific features, and common features. The typical programming sequence begins with issuing a reset to the device, selecting T1 or E1 operation in the master mode register, enabling T1 or E1 functions, and enabling the common functions. The act of resetting the device automatically clears all configuration and status registers.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 8.1 Power-Up Sequence The DS21455/DS21458 contain an on-chip power-up reset function, which automatically clears the writeable register space immediately after power is supplied to the device. The user can issue a chip reset at any time. Issuing a reset will disrupt traffic until the device is reprogrammed. The reset can be issued through hardware using the TSTRST pin or through software using the SFTRST function in the master mode register. The LIRST (LIC2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 8.2 Interrupt Handling Various alarms, conditions, and events in the DS21455/DS21458 can cause interrupts. For simplicity, these are all referred to as events in this explanation. All STATUS registers can be programmed to produce interrupts. Each status register has an associated interrupt mask register. For example, SR1 (Status Register 1) has an interrupt control register called IMR1 (Interrupt Mask Register 1).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 8.4 Information Registers Information registers operate the same as status registers except they cannot cause interrupts. They are all latched except for INFO7 and some of the bits in INFO5 and INFO6. INFO7 register is a read only register and it reports the status of the E1 synchronizer in real time. INFO7 and some of the bits in INFO6 and INFO5 are not latched and it is not necessary to precede a read of these bits with a write. 8.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 9. CLOCK MAP Figure 9-1 shows the clock map of the DS21455/DS21458. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator, which can be placed in the receive or transmit path, two are shown for simplification and clarity. Figure 9-1. Clock Map MCLK PRE-SCALER LIC4.MPS0 LIC4.MPS1 2.048 TO 1.544 SYNTHESIZER LIC2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 10. T1 FRAMER/FORMATTER CONTROL REGISTERS The T1 framer portion of the DS21455/DS21458 is configured via a set of nine control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers will only need to be accessed when there is a change in the system configuration.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 T1RCR2 T1 Receive Control Register 2 04h 6 RFM 0 5 RB8ZS 0 4 RSLC96 0 3 RZSE 0 2 RZBTSI 0 1 RJC 0 0 RD4YM 0 Bit 0/Receive Side D4 Yellow Alarm Select (RD4YM). 0 = zeros in bit 2 of all channels 1 = a one in the S-bit position of frame 12 (J1 Yellow Alarm Mode) Bit 1/Receive Japanese CRC6 Enable (RJC).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 TJC 0 T1TCR1 T1 Transmit Control Register 1 05h 6 TFPT 0 5 TCPT 0 4 TSSE 0 3 GB7S 0 2 TFDLS 0 1 TBL 0 0 TYEL 0 Bit 0/Transmit Yellow Alarm (TYEL). 0 = do not transmit yellow alarm 1 = transmit yellow alarm Bit 1/Transmit Blue Alarm (TBL). 0 = transmit data normally 1 = transmit an unframed all one’s code at TPOS and TNEG Bit 2/TFDL Register Select (TFDLS).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 TB8ZS 0 T1TCR2 T1 Transmit Control Register 2 06h 6 TSLC96 0 5 TZSE 0 4 FBCT2 0 3 FBCT1 0 2 TD4YM 0 1 TZBTSI 0 0 TB7ZS 0 Bit 0/Transmit Side Bit 7 Zero Suppression Enable (TB7ZS). 0 = no stuffing occurs 1 = Bit 7 force to a one in channels with all zeros Bit 1/Transmit Side ZBTSI Support Enable (TZBTSI). Allows ZBTSI information to be input on TLINK pin.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: T1CCR1 T1 Common Control Register 1 07h Bit # Name Default 6 — 0 7 — 0 5 — 0 4 TRAI-CI 0 3 TAIS-CI 0 2 TFM 0 1 PDE 0 0 TLOOP 0 Bit 0/Transmit Loop Code Enable (TLOOP). See Programmable In-Band Loop Codes Generation and Detection for details.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 10.2 T1 Transmit Transparency The software-signaling insertion-enable registers, SSIE1–SSIE4, can be used to select signaling insertion from the transmit-signaling registers, TS1–TS12, on a per-channel basis. Setting a bit in the SSIEx register allows signaling data to be sourced from the signaling registers for that channel. In transparent mode, bit 7 stuffing and/or robbed-bit signaling is prevented from overwriting the data in the channels.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 10.3 AIS-CI and RAI-CI Generation and Detection The DS21455/DS21458 can transmit and detect the RAI-CI and AIS-CI codes in T1 mode. These codes are compatible with and do not interfere with the standard RAI (Yellow) and AIS (Blue) alarms. These codes are defined in ANSI T1.403. The AIS-CI code (alarm indication signal-customer installation) is the same for both ESF and D4 operation.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 10.4 T1 Receive-Side Digital-Milliwatt Code Generation Receive-side digital-milliwatt code generation involves using the receive digital-milliwatt registers (T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be overwritten with a digital-milliwatt pattern. The digital-milliwatt code is an 8-byte repeating pattern that represents a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 CH8 0 T1RDMR1 T1 Receive Digital-Milliwatt Enable Register 1 0Ch 6 CH7 0 5 CH6 0 4 CH5 0 3 CH4 0 2 CH3 0 1 CH2 0 0 CH1 0 Bits 0 to 7/Receive Digital-Milliwatt Enable for Channels 1 to 8 (CH1 to CH8).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 10.5 T1 Information Register Register Name: Register Description: Register Address: Bit # Name Default 7 RPDV 0 INFO1 Information Register 1 10h 6 TPDV 0 5 COFA 0 4 8ZD 0 3 16ZD 0 2 SEFE 0 1 B8ZS 0 0 FBE 0 Bit 0/Frame Bit Error Event (FBE). Set when a Ft (D4) or FPS (ESF) framing bit is received in error. Bit 1/B8ZS Codeword Detect Event (B8ZS).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Table 10-1. T1 Alarm Criteria ALARM Blue Alarm (AIS) (Note 1) SET CRITERIA Over a 3ms window, five or fewer zeros are received CLEAR CRITERIA Over a 3ms window, six or more zeros are received D4 Bit-2 Mode (T1RCR2.0 = 0) Bit 2 of 256 consecutive channels is set to zero for at least 254 occurrences Bit 2 of 256 consecutive channels is set to zero for less than 254 occurrences D4 12th F-bit Mode (T1RCR2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 11. E1 FRAMER/FORMATTER CONTROL REGISTERS The E1 framer portion of the DS21455/DS21458 is configured via a set of four control registers. Typically, the control registers are only accessed when the system is first powered up. Once the device has been initialized, the control registers will only need to be accessed when there is a change in the system configuration.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Table 11-1. E1 Sync/Resync Criteria FRAME OR MULTIFRAME LEVEL FAS SYNC CRITERIA RESYNC CRITERIA FAS present in frame N and N + 2, and FAS not present in frame N + 1 ITU SPEC. Three consecutive incorrect FAS received G.706 4.1.1 4.1.2 Alternate: (E1RCR1.2 = 1) The above criteria is met or three consecutive incorrect bit 2 of nonFAS received.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 TFPT 0 E1TCR1 E1 Transmit Control Register 1 35h 6 T16S 0 5 TUA1 0 4 TSiS 0 3 TSA1 0 2 THDB3 0 1 TG802 0 0 TCRC4 0 Bit 0/Transmit CRC-4 Enable (TCRC4). 0 = CRC-4 disabled 1 = CRC-4 enabled Bit 1/Transmit G.802 Enable (TG802). See the Functional Timing Diagrams section for details.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 Sa8S 0 E1TCR2 E1 Transmit Control Register 2 36h 6 Sa7S 0 5 Sa6S 0 4 Sa5S 0 3 Sa4S 0 2 AEBE 0 1 AAIS 0 0 ARA 0 Bit 0/Automatic Remote Alarm Generation (ARA). 0 = disabled 1 = enabled Bit 1/Automatic AIS Generation (AAIS). 0 = disabled 1 = enabled Bit 2/Automatic E-Bit Enable (AEBE).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 11.2 Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. 11.2.1 Auto AIS When automatic AIS generation is enabled (E1TCR2.1 = 1), the device monitors the receive side framer to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all ones) reception, or loss of receive carrier (or signal).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 11.3 E1 Information Registers Register Name: Register Description: Register Address: INFO3 Information Register 3 12h Bit # Name Default 6 — 0 7 — 0 5 — 0 4 — 0 3 — 0 2 CRCRC 0 1 FASRC 0 0 CASRC 0 Bit 0/CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words are received in error. (Note: During a CRC resync the FAS synchronizer is brought online to verify the FAS alignment.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Table 11-3. E1 Alarm Criteria ALARM RLOS RCL RRA SET CRITERIA An RLOS condition exists on power-up prior to initial synchronization, when a resync criteria has been met, or when a manual resync has been initiated via E1RCR1.0 255 or 2048 consecutive zeros received as determined by E1RCR2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 12. COMMON CONTROL AND STATUS REGISTERS Register Name: Register Description: Register Address: Bit # Name Default 7 MCLKS 0 CCR1 Common Control Register 1 70h 6 CRC4R 0 5 SIE 0 4 ODM 0 3 — 0 2 TCSS1 0 1 TCSS0 0 0 RLOSF 0 Bit 0/Function of the RLOS/LOTC Output (RLOSF). 0 = Receive Loss of Sync (RLOS) 1 = Loss of Transmit Clock (LOTC) Bit 1/Transmit Clock Source Select Bit 0 (TCSS0). Bit 2/Transmit Clock Source Select Bit 1 (TCSS1).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 ID7 X IDR Device Identification Register 0Fh 6 ID6 X 5 ID5 X 4 ID4 X 3 ID3 X 2 ID2 X 1 ID1 X 0 ID0 X Bits 0 to 3/Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to display the die revision of the chip. IDO is the LSB of a decimal code that represents the chip revision. Bits 4 to 7/Device ID (ID4 to ID7).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 RYELC 0 IMR2 Interrupt Mask Register 2 19h 6 RUA1C 0 5 FRCLC 0 4 RLOSC 0 3 RYEL 0 Bit 0/Receive Loss of Sync Condition (RLOS). 0 = interrupt masked 1 = interrupt enabled–interrupts on rising edge only Bit 1/Framer Receive Carrier Loss Condition (FRCL).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 LSPARE 0 SR3 Status Register 3 1Ah 6 LDN 0 5 LUP 0 4 LOTC 0 3 LORC 0 2 V52LNK 0 1 RDMA 0 0 RRA 0 Bit 0/Receive Remote Alarm Condition (RRA) (E1 Only). Set when a remote alarm is received at RPOSI and RNEGI Bit 1/Receive Distant MF Alarm Condition (RDMA) (E1 Only). Set when bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 LSPARE 0 IMR3 Interrupt Mask Register 3 1Bh 6 LDN 0 5 LUP 0 4 LOTC 0 3 LORC 0 Bit 0/Receive Remote Alarm Condition (RRA). 0 = interrupt masked 1 = interrupt enabled—interrupts on rising and falling edges Bit 1/Receive Distant MF Alarm Condition (RDMA). 0 = interrupt masked 1 = interrupt enabled—interrupts on rising and falling edges Bit 2/V5.2 Link Detected Condition (V52LNK).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 RAIS-CI 0 SR4 Status Register 4 1Ch 6 RSA1 0 5 RSA0 0 4 TMF 0 3 TAF 0 2 RMF 0 1 RCMF 0 0 RAF 0 Bit 0/Receive Align Frame Event (RAF) (E1 Only). Set every 250s at the beginning of align frames. Used to alert the host that Si and Sa bits are available in the RAF and RNAF registers. Bit 1/Receive CRC-4 Multiframe Event (RCMF) (E1 Only).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 RAIS-CI 0 IMR4 Interrupt Mask Register 4 1Dh 6 RSA1 0 5 RSA0 0 4 TMF 0 3 TAF 0 Bit 0/Receive Align Frame Event (RAF). 0 = interrupt masked 1 = interrupt enabled Bit 1/Receive CRC-4 Multiframe Event (RCMF). 0 = interrupt masked 1 = interrupt enabled Bit 2/Receive Multiframe Event (RMF). 0 = interrupt masked 1 = interrupt enabled Bit 3/Transmit Align Frame Event (TAF).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 13. I/O PIN CONFIGURATION OPTIONS Register Name: Register Description: Register Address: Bit # Name Default 7 RSMS 0 IOCR1 I/O Configuration Register 1 01h 6 RSMS2 0 5 RSMS1 0 4 RSIO 0 3 TSDW 0 2 TSM 0 1 TSIO 0 0 ODF 0 Bit 0/Output Data Format (ODF). 0 = bipolar data at TPOSO and TNEGO 1 = NRZ data at TPOSO; TNEGO = 0 Bit 1/TSYNC I/O Select (TSIO). 0 = TSYNC is an input 1 = TSYNC is an output Bit 2/TSYNC Mode Select (TSM).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: IOCR2 I/O Configuration Register 2 02h Bit # Name Default 7 6 5 4 3 2 1 0 RCLKINV TCLKINV RSYNCINV TSYNCINV TSSYNCINV H100EN TSCLKM RSCLKM 0 0 0 0 0 0 0 0 Bit 0/RSYSCLK Mode Select (RSCLKM). 0 = if RSYSCLK is 1.544MHz 1 = if RSYSCLK is 2.048MHz or IBO enabled (See the Interleaved PCM Bus Operation section.) Bit 1/TSYSCLK Mode Select (TSCLKM). 0 = if TSYSCLK is 1.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 14. LOOPBACK CONFIGURATIONS The DS21455/DS21458 have four loopback configurations including Framer, Payload, Local, and Remote loopback. Figure 14-1 depicts a normal signal flow without any loopbacks enabled. Payload loopback may be done on a per-channel basis if both the transmit and receive paths are synchronous (RCLK = TCLK and RSYNC = TSYNC). See Section 14.1. Figure 14-1.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers This loopback is useful in testing and debugging applications. In FLB, the device will loop data from the transmit side back to the receive side. When FLB is enabled, the following will occur: 1) T1 Mode: An unframed all ones code will be transmitted at TPOSO and TNEGO. E1 Mode: Normal data will be transmitted at TPOSO and TNEGO. 2) Data at RPOSI and RNEGI will be ignored. 3) All receive-side signals will take on timing synchronous with TCLK instead of RCLKI.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Bit 3/Local Loopback (LLB). In this loopback, data will continue to be transmitted as normal through the transmit side of the transceiver. Data being received at RTIP and RRING will be replaced with the data being transmitted. Data in this loopback will pass through the jitter attenuator.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 14.1 Per-Channel Payload Loopback The per-channel loopback registers (PCLRs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off of the T1 or E1 line. If this loopback is enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this would be to tie RCLK to TCLK and RFSYNC to TSYNC.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 PCLR3 Per-Channel Loopback Enable Register 3 4Dh 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0 1 CH26 0 0 CH25 0 Bits 0 to 7/Per-Channel Loopback Enable for Channels 17 to 24 (CH17 to CH24). 0 = loopback disabled 1 = enable loopback.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 15. ERROR COUNT REGISTERS The DS21455/DS21458 contain four counters that are used to accumulate line coding errors, path errors, and synchronization errors. Counter update options include one second boundaries, 42ms (T1 mode only), 62ms (E1 mode only) or manually. See Error Counter Configuration Register (ERCNT). When updated automatically, the user can use the interrupt from the timer to determine when to read these registers.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 15.1 Line Code Violation Count Register (LCVCR) 15.1.1 T1 Operation T1 code violations are defined as bipolar violations (BPVs) or excessive zeros. If the B8ZS mode is set for the receive side, then B8ZS codewords are not counted. This counter is always enabled; it is not disabled during receive loss of synchronization (RLOS = 1) conditions. Table 15-1. T1 Line Code Violation Counting Options COUNT EXCESSIVE ZEROS? (ERCNT.0) No Yes No Yes B8ZS ENABLED? (T1RCR2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 LCVC15 0 LCVCR1 Line Code Violation Count Register 1 42h 6 LCVC14 0 5 LCVC13 0 4 LCVC12 0 3 LCVC11 0 2 LCVC10 0 1 LCVC9 0 0 LCCV8 0 Bits 0 to 7/Line Code Violation Counter Bits 8 to 15 (LCVC8 to LCVC15). LCV15 is the MSB of the 16-bit code violation count.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 15.2 Path Code Violation Count Register (PCVCR) 15.2.1 T1 Operation The path code violation count register records either Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to operate in the T1 ESF framing mode, PCVCR will record errors in the CRC6 codewords. When set to operate in the T1 D4 framing mode, PCVCR will count errors in the Ft framing bit position. Via the ERCNT.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 15.3 Frames Out Of Sync Count Register (FOSCR) 15.3.1 T1 Operation The FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is useful in ESF applications needing to measure the parameters loss of frame count (LOFC) and ESF error events as described in AT&T publication TR54016. When the FOSCR is operated in this mode, it is not disabled during receive loss of synchronization (RLOS = 1) conditions.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 FOS15 0 FOSCR1 Frames Out Of Sync Count Register 1 46h 6 FOS14 0 5 FOS13 0 4 FOS12 0 3 FOS11 0 2 FOS10 0 1 FOS9 0 0 FOS8 0 Bits 0 to 7/Frames Out of Sync Counter Bits 8 to 15 (FOS8 to FOS15). FOS15 is the MSB of the 16-bit frames out of sync count.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 16. DS0 MONITORING FUNCTION The DS21455/DS21458 can monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction the user will determine which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the TDS0SEL register. In the receive direction, the RCM0 to RCM4 bits in the RDS0SEL register need to be properly set.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 16.2 Receive DS0 Monitor Registers Register Name: Register Description: Register Address: RDS0SEL Receive Channel Monitor Select 76h Bit # Name Default 6 — 0 7 — 0 5 — 0 4 RCM4 0 3 RCM3 0 2 RCM2 0 1 RCM1 0 0 RCM0 0 Bits 0 to 4/Receive Channel Monitor Bits (RCM0 to RCM4). RCM0 is the LSB of a 5-bit channel-select that determines which receive DS0 channel data will appear in the RDS0M register. Bits 5 to 7/Unused, must be set to zero for proper operation.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 17. SIGNALING OPERATION There are two methods to access receive signaling data and provide transmit signaling data: processorbased (i.e., software-based) or hardware-based. Processor-based refers to access through the transmit and receive signaling registers, RS1–RS16 and TS1–TS16. Hardware-based refers to the TSIG and RSIG pins. Both methods can be used simultaneously. 17.1 Receive Signaling Figure 17-1.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 17.1.1 Processor-Based Receive Signaling The robbed-bit signaling (T1) or TS16 CAS signaling (E1) is sampled in the receive data stream and copied into the receive signaling registers, RS1 through RS16. In T1 mode, only RS1 through RS12 are used. The signaling information in these registers is always updated on multiframe boundaries. This function is always enabled. 17.1.1.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 17.1.2.2 Force Receive Signaling All Ones In T1 mode, the user can, on a per-channel basis, force the robbed-bit signaling-bit positions to a one. This is done by using the per-channel register, which is described in the Special Per-Channel Operation section. The user sets the BTCS bit in the PCPR register. The channels that are to be forced to one are selected by writing to the PCDR1–PCDR3 registers. 17.1.2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: SIGCR Signaling Control Register 40h Bit # Name Default 6 — 0 7 GRSRE 0 5 — 0 4 RFE 0 3 RFF 0 2 RCCS 0 1 TCCS 0 0 FRSAO 0 Bit 0/Force Receive Signaling All Ones (FRSAO). In T1 mode, this bit forces all signaling data at the RSIG and RSER pin to all ones. This bit has no effect in E1 mode.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B RS1 to RS12 Receive Sig
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: (MSB) 0 CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH26-A CH28-A CH30-A 0 CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B CH26-B CH28-B CH30-B Register Name: Register Description: Register Address: (MSB) 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121 2 10 18 26 34 42 50 58 66 74 82 90 98 106 114 122 RS1 to RS16 Receive Signaling Register
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 CH7 CH15 CH23 RSCSE1, RSCSE2, RSCSE3, RSCSE4 Receive Signaling Change Of State Interrupt Enable 3Ch, 3Dh, 3Eh, 3Fh CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 (LSB) CH1 CH9 CH17 CH25 RSCSE1 RSCSE2 RSCSE3 RSCSE4 Setting any of the CH1 through CH30 bits in the RSCSE1 through RSCSE4 registers will cause an interrupt when that channel’s
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 17.2 Transmit Signaling Figure 17-2.Simplified Diagram of Transmit Signaling Path TRANSMIT SIGNALING REGISTERS 1 0 0 T1/E1 DATA STREAM TSER 0 1 1 B7 SIGNALING BUFFERS TSIG T1TCR1.4 PER-CHANNEL CONTROL PER-CHANNEL CONTROL PCPR.3 SSIE1 - SSIE4 ONLY APPLIES TO T1 MODE 17.2.1 Processor-Based Transmit Signaling In processor-based mode, signaling data is loaded into the transmit-signaling registers (TS1–TS16) via the host interface.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 17.2.1.1 T1 Mode In T1 ESF framing mode, there are four signaling bits per channel (A, B, C, and D). TS1–TS12 contain a full multiframe of signaling data. In T1 D4 framing mode, there are only two signaling bits per channel (A and B). In T1 D4 framing mode, the framer uses the C and D bit positions as the A and B bit positions for the next multiframe. In D4 mode, two multiframes of signaling data can be loaded into TS1–TS12.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: (MSB) 0 CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH26-A CH28-A CH30-A 0 CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B CH26-B CH28-B CH30-B Register Name: Register Description: Register Address: (MSB) 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121 2 10 18 26 34 42 50 58 66 74 82 90 98 106 114 122 TS1 to TS16 Transmit Signaling Registe
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B TS1 to TS16 Transmit Si
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 17.2.2 Software Signaling Insertion Enable Registers, E1 CAS Mode In E1 CAS mode, the CAS signaling alignment/alarm byte can be sourced from the transmit signaling registers along with the signaling data. Register Name: Register Description: Register Address: Bit # Name Default 7 CH7 0 SSIE1 Software Signaling Insertion Enable 1 08h 6 CH6 0 5 CH5 0 4 CH4 0 3 CH3 0 2 CH2 0 1 CH1 0 0 UCAW 0 Bit 0/Upper CAS Align/Alarm Word (UCAW).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 CH22 0 SSIE3 Software Signaling Insertion Enable 3 0Ah 6 CH21 0 5 CH20 0 4 CH19 0 3 CH18 0 2 CH17 0 1 CH16 0 0 LCAW 0 Bit 0/Lower CAS Align/Alarm Word (LCAW). Selects the lower CAS align/alarm bits (xyxx) to be sourced from the lower 4 bits of the TS1 register.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 17.2.3 Software Signaling Insertion Enable Registers, T1 Mode In T1 mode, only registers SSIE1 through SSIE3 are used since there are only 24 channels in a T1 frame. Register Name: Register Description: Register Address: Bit # Name Default 7 CH8 0 SSIE1 Software Signaling Insertion Enable 1 08h 6 CH7 0 5 CH6 0 4 CH5 0 3 CH4 0 2 CH3 0 1 CH2 0 0 CH1 0 Bits 0 to 7/Software Signaling Insertion Enable for and Channels 1 to 8 (CH1 to CH8).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 17.2.4 Hardware-Based Transmit Signaling In hardware-based mode, signaling data is input via the TSIG pin. This signaling PCM stream is buffered and inserted to the data stream being input at the TSER pin. Signaling data can be input on a per-channel basis via the transmit-hardware signaling-channel select (THSCS) function.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 18. PER-CHANNEL IDLE CODE GENERATION Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. When operated in the T1 mode, only the first 24 channels are used; the remaining channels, CH25–CH32 are not used. The DS21455/DS21458 contain a 64-byte idle code array accessed by the idle array address register (IAAR) and the per-channel idle code register (PCICR).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 18.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 GRIC 0 IAAR Idle Array Address Register 7Eh 6 GTIC 0 5 IAA5 0 4 IAA4 0 3 IAA3 0 2 IAA2 0 1 IAA1 0 0 IAA0 0 Bits 0 to 5/Channel Pointer Address Bits (IAA0 to IAA5). IAA0 is the LSB of the 5-bit Channel Code. Bit 6/Global Transmit Idle Code (GTIC). Setting this bit will cause all transmit idle codes to be set to the value written to the PCICR register.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 TCICE3 Transmit Channel Idle Code Enable Register 3 82h 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0 Bits 0 to 7/Transmit Channels 17 to 24 Code Insertion Control Bits (CH17 to CH24).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 RCICE3 Receive Channel Idle Code Enable Register 3 86h 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0 Bits 0 to 7/Receive Channels 17 to 24 Code Insertion Control Bits (CH17 to CH24).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 19. CHANNEL BLOCKING REGISTERS The receive-channel blocking registers (RCBR1/RCBR2/RCBR3/RCBR4) and the transmit-channel blocking registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN–PRI applications.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 RCBR3 Receive Channel Blocking Register 3 8Ah 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0 Bits 0 to 7/Receive Channels 17 to 24 Channel Blocking Control Bits (CH17 to CH24).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 TCBR3 Transmit Channel Blocking Register 3 8Eh 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0 Bits 0 to 7/Transmit Channels 17 to 24 Channel Blocking Control Bits (CH17 to CH24).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 20. ELASTIC STORES OPERATION The DS21455/DS21458 contain dual two-frame, fully independent elastic stores, one for the receive direction and one for the transmit direction. The transmit- and receive-side elastic stores can be enabled/disabled independent of each other. Also, each elastic store can interface to either a 1.544MHz or 2.048MHz/4.096MHz/8.192MHz/16.384MHz backplane without regard to the backplane rate to which the other elastic store is interfacing.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: ESCR Elastic Store Control Register 4Fh Bit # Name Default 6 TESR 0 7 TESALGN 0 5 TESMDM 0 4 TESE 0 3 RESALGN 0 2 RESR 0 1 RESMDM 0 0 RESE 0 Bit 0/Receive Elastic Store Enable (RESE). 0 = elastic store is bypassed 1 = elastic store is enabled Bit 1/Receive Elastic Store Minimum Delay Mode (RESMDM). See the Minimum Delay Mode section for details.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: SR5 Status Register 5 1Eh Bit # Name Default 6 — 0 7 — 0 5 TESF 0 4 TESEM 0 3 TSLIP 0 2 RESF 0 1 RESEM 0 0 RSLIP 0 Bit 0/Receive Elastic Store Slip Occurrence Event (RSLIP). Set when the receive elastic store has either repeated or deleted a frame. Bit 1/Receive Elastic Store Empty Event (RESEM). Set when the receive elastic store buffer empties and a frame is repeated.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 20.1 Receive Side See the IOCR1 and IOCR2 registers for information on clock and I/O configurations. If the receive-side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the RSYSCLK pin. For higher rate system-clock applications, see the Interleaved PCM Bus Operation section.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 20.2 Transmit Side See the IOCR1 and IOCR2 registers for information on clock and I/O configurations. The operation of the transmit elastic store is very similar to the receive side. If the transmit-side elastic store is enabled a 1.544MHz or 2.048MHz clock can be applied to the TSYSCLK input. For higher-rate system clock applications, see the Interleaved PCM Bus Operation section. Controlled slips in the transmit elastic store are reported in the SR5.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 20.4 Minimum-Delay Mode When minimum delay mode is enabled the elastic stores will be forced to a maximum depth of 32 bits instead of the normal two-frame depth. ESCR.5 and ESCR.1 enable the transmit and receive elastic store minimum-delay modes. This feature is useful primarily in applications that interface T1 to a 2.048MHz bus without adding the latency that would be associated with using the elastic store in full buffer mode.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 21. G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY) The DS21455/DS21458 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSER will already have the FAS/NFAS, CRC multiframe alignment word, and CRC-4 checksum in time slot 0. The user can modify the Sa bit positions; this change in data content will be used to modify the CRC-4 checksum.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 22. T1 BIT ORIENTED CODE (BOC) CONTROLLER The DS21455/DS21458 contain a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. 22.1 Transmit BOC Bits 0 through 5 in the TFDL register contain the BOC message to be transmitted. Setting BOCC.0 = 1 causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: BOCC BOC Control Register 37h Bit # Name Default 6 — 0 7 — 0 5 — 0 4 RBOCE 0 3 RBR 0 2 RBF1 0 1 RBF0 0 0 SBOC 0 Bit 0/Send BOC (SBOC). Set = 1 to transmit the BOC code placed in bits 0 to 5 of the TFDL register. Bits 1 to 2/Receive BOC Filter Bits (RBF0, RBF1). The BOC filter sets the number of consecutive patterns that must be received without error prior to an indication of a valid message.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: RFDL (RFDL register bit usage when BOCC.4 = 1) Receive FDL Register C0h Bit # Name Default 6 — 0 7 — 0 5 RBOC5 0 4 RBOC4 0 3 RBOC3 0 2 RBOC2 0 1 RBOC1 0 0 RBOC0 0 3 RFDLF 0 2 TFDLE 0 1 RMTCH 0 0 RBOC 0 Bit 0/BOC Bit 0 (RBOC0). Bit 1/BOC Bit 1 (RBOC1). Bit 2/BOC Bit 2 (RBOC2). Bit 3/BOC Bit 3 (RBOC3). Bit 4/BOC Bit 4 (RBOC4). Bit 5/BOC Bit 5 (RBOC5). Bit 6/This bit position is unused when BOCC.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: IMR8 Interrupt Mask Register 8 25h Bit # Name Default 6 — 0 7 — 0 5 BOCC 0 4 RFDLAD 0 3 RFDLF 0 Bit 0/Receive BOC Detector Change of State Event (RBOC). 0 = interrupt masked 1 = interrupt enabled Bit 1/Receive FDL Match Event (RMTCH). 0 = interrupt masked 1 = interrupt enabled Bit 2/TFDL Register Empty Event (TFDLE). 0 = interrupt masked 1 = interrupt enabled Bit 3/RFDL Register Full Event (RFDLF).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 23. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION (E1 ONLY) The DS21455/DS21458, when operated in the E1 mode, provide for access to both the Sa and the Si bits via three different methods. The first method is via a hardware scheme using the RLINK/RLCLK and TLINK/TLCLK pins. The second method involves using the internal RAF/RNAF and TAF/TNAF registers. The third method involves an expanded version of the second method. 23.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: RAF Receive Align Frame Register C6h Bit # Name Default 6 0 0 7 Si 0 5 0 0 4 1 0 3 1 0 2 0 0 1 1 0 0 1 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 Bit 0/Frame Alignment Signal Bit (1). Bit 1/Frame Alignment Signal Bit (1). Bit 2/Frame Alignment Signal Bit (0). Bit 3/Frame Alignment Signal Bit (1). Bit 4/Frame Alignment Signal Bit (1). Bit 5/Frame Alignment Signal Bit (0).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: TAF Transmit Align Frame Register D0h Bit # Name Default 6 0 0 7 Si 0 5 0 0 4 1 1 3 1 1 2 0 0 1 1 1 0 1 1 2 Sa6 0 1 Sa7 0 0 Sa8 0 Bit 0/Frame Alignment Signal Bit (1). Bit 1/Frame Alignment Signal Bit (1). Bit 2/Frame Alignment Signal Bit (0). Bit 3/Frame Alignment Signal Bit (1). Bit 4/Frame Alignment Signal Bit (1). Bit 5/Frame Alignment Signal Bit (0). Bit 6/Frame Alignment Signal Bit (0).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 23.3 Internal Register Scheme Based On CRC-4 Multiframe (Method 3) On the receive side, there is a set of eight registers (RSiAF, RSiNAF, RRA, RSa4 to RSa8) that report the Si and Sa bits as they are received. These registers are updated with the setting of the receive CRC-4 multiframe bit in status register 2 (SR4.1). The host can use the SR4.1 bit to know when to read these registers. The user has 2ms to retrieve the data before it is lost.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 SiF1 0 RSiNAF Receive Si Bits of the Nonalign Frame C9h 6 SiF3 0 5 SiF5 0 4 SiF7 0 3 SiF9 0 2 SiF11 0 1 SiF13 0 0 SiF15 0 3 RRAF9 0 2 RRAF11 0 1 RRAF13 0 0 RRAF15 0 Bit 0/Si Bit of Frame 15(SiF15). Bit 1/Si Bit of Frame 13(SiF13). Bit 2/Si Bit of Frame 11(SiF11). Bit 3/Si Bit of Frame 9(SiF9). Bit 4/Si Bit of Frame 7(SiF7). Bit 5/Si Bit of Frame 5(SiF5).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 RSa4F1 0 RSa4 Receive Sa4 Bits CBh 6 RSa4F3 0 5 RSa4F5 0 4 RSa4F7 0 3 RSa4F9 0 2 RSa4F11 0 1 RSa4F13 0 0 RSa4F15 0 4 RSa5F7 0 3 RSa5F9 0 2 RSa5F11 0 1 RSa5F13 0 0 RSa5F15 0 Bit 0/Sa4 Bit of Frame 15(RSa4F15). Bit 1/Sa4 Bit of Frame 13(RSa4F13). Bit 2/Sa4 Bit of Frame 11(RSa4F11). Bit 3/Sa4 Bit of Frame 9(RSa4F9). Bit 4/Sa4 Bit of Frame 7(RSa4F7).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 RSa6F1 0 RSa6 Receive Sa6 Bits CDh 6 RSa6F3 0 5 RSa6F5 0 4 RSa6F7 0 3 RSa6F9 0 2 RSa6F11 0 1 RSa6F13 0 0 RSa6F15 0 4 RSa7F7 0 3 RSa7F9 0 2 RSa7F11 0 1 RSa7F13 0 0 RSa7F15 0 Bit 0/Sa6 Bit of Frame 15(RSa6F15). Bit 1/Sa6 Bit of Frame 13(RSa6F13). Bit 2/Sa6 Bit of Frame 11(RSa6F11). Bit 3/Sa6 Bit of Frame 9(RSa6F9). Bit 4/Sa6 Bit of Frame 7(RSa6F7).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 RSa8F1 0 RSa8 Receive Sa8 Bits CFh 6 RSa8F3 0 5 RSa8F5 0 4 RSa8F7 0 3 RSa8F9 0 Bit 0/Sa8 Bit of Frame 15(RSa8F15). Bit 1/Sa8 Bit of Frame 13(RSa8F13). Bit 2/Sa8 Bit of Frame 11(RSa8F11). Bit 3/Sa8 Bit of Frame 9(RSa8F9). Bit 4/Sa8 Bit of Frame 7(RSa8F7). Bit 5/Sa8 Bit of Frame 5(RSa8F5). Bit 6/Sa8 Bit of Frame 3(RSa8F3). Bit 7/Sa8 Bit of Frame 1(RSa8F1).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 TsiF0 0 TSiAF Transmit Si Bits of the Align Frame D2h 6 TsiF2 0 5 TsiF4 0 4 TsiF6 0 3 TsiF8 0 Bit 0/Si Bit of Frame 14(TsiF14). Bit 1/Si Bit of Frame 12(TsiF12). Bit 2/Si Bit of Frame 10(TsiF10). Bit 3/Si Bit of Frame 8(TsiF8). Bit 4/Si Bit of Frame 6(TsiF6). Bit 5/Si Bit of Frame 4(TsiF4). Bit 6/Si Bit of Frame 2(TsiF2). Bit 7/Si Bit of Frame 0(TsiF0).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 TsiF1 0 TSiNAF Transmit Si Bits of the Nonalign Frame D3h 6 TsiF3 0 5 TsiF5 0 4 TsiF7 0 3 TsiF9 0 2 TsiF11 0 1 TsiF13 0 0 TSiF15 0 3 TRAF9 0 2 TRAF11 0 1 TRAF13 0 0 TRAF15 0 Bit 0/Si Bit of Frame 15(TSiF15). Bit 1/Si Bit of Frame 13(TsiF13). Bit 2/Si Bit of Frame 11(TsiF11). Bit 3/Si Bit of Frame 9(TsiF9). Bit 4/Si Bit of Frame 7(TsiF7). Bit 5/Si Bit of Frame 5(TsiF5).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 TSa4F1 0 TSa4 Transmit Sa4 Bits D5h 6 TSa4F3 0 5 TSa4F5 0 4 TSa4F7 0 3 TSa4F9 0 2 TSa4F11 0 1 TSa4F13 0 0 TSa4F15 0 4 TSa5F7 0 3 TSa5F9 0 2 TSa5F11 0 1 TSa5F13 0 0 TSa5F15 0 Bit 0/Sa4 Bit of Frame 15(TSa4F15). Bit 1/Sa4 Bit of Frame 13(TSa4F13). Bit 2/Sa4 Bit of Frame 11(TSa4F11). Bit 3/Sa4 Bit of Frame 9(TSa4F9). Bit 4/Sa4 Bit of Frame 7(TSa4F7).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 TSa6F1 0 TSa6 Transmit Sa6 Bits D7h 6 TSa6F3 0 5 TSa6F5 0 4 TSa6F7 0 3 TSa6F9 0 2 TSa6F11 0 1 TSa6F13 0 0 TSa6F15 0 4 TSa7F7 0 3 TSa7F9 0 2 TSa7F11 0 1 TSa7F13 0 0 TSa7F15 0 Bit 0/Sa6 Bit of Frame 15(TSa6F15). Bit 1/Sa6 Bit of Frame 13(TSa6F13). Bit 2/Sa6 Bit of Frame 11(TSa6F11). Bit 3/Sa6 Bit of Frame 9(TSa6F9). Bit 4/Sa6 Bit of Frame 7(TSa6F7).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 TSa8F1 0 TSa8 Transmit Sa8 Bits D9h 6 TSa8F3 0 5 TSa8F5 0 4 TSa8F7 0 3 TSa8F9 0 Bit 0/Sa8 Bit of Frame 15(TSa8F15). Bit 1/Sa8 Bit of Frame 13(TSa8F13). Bit 2/Sa8 Bit of Frame 11(TSa8F11). Bit 3/Sa8 Bit of Frame 9(TSa8F9). Bit 4/Sa8 Bit of Frame 7(TSa8F7). Bit 5/Sa8 Bit of Frame 5(TSa8F5). Bit 6/Sa8 Bit of Frame 3(TSa8F3). Bit 7/Sa8 Bit of Frame 1(TSa8F1).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 SiAF 0 TSACR Transmit Sa Bit Control Register DAh 6 SiNAF 0 5 RA 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 Bit 0/Additional Bit 8 Insertion Control Bit (Sa8). 0 = do not insert data from the TSa8 register into the transmit data stream 1 = insert data from the TSa8 register into the transmit data stream Bit 1/Additional Bit 7 Insertion Control Bit (Sa7).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 24. HDLC CONTROLLERS This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, or Sa4 to Sa8 bits (E1 Mode) or the FDL (T1 Mode). Each HDLC controller has 128 byte buffers in both the transmit and receive paths.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Table 24-1.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 24.2 HDLC Configuration Basic configuration of the HDLC controllers is accomplished via the HxTC and HxRC registers. Operating features such as CRC generation, zero stuffer, transmit and receive HDLC mapping options, and idle flags are selected here. Also, the HDLC controllers are reset via these registers.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 RHR 0 H1RC, H2RC HDLC #1 Receive Control, HDLC #2 Receive Control 31h, 32h 6 RHMS 0 5 — 0 4 — 0 3 HDLCD 0 2 — 0 1 — 0 0 RSFD 0 Bit 0/Receive SS7 Fill In Signal Unit Delete (RSFD). 0 = normal operation. All FISUs are stored in the receive FIFO and reported to the host.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 24.2.1 FIFO Control Control of the transmit and receive FIFOs is accomplished via the FIFO control (HxFC). The FIFO control register sets the watermarks for both the transmit and receive FIFO. Bits 3–5 set the transmit low watermark and the lower 3 bits set the receive high watermark. When the transmit FIFO empties below the low watermark, the TLWM bit in the appropriate HDLC status register SR6 or SR7 will be set.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 24.3 HDLC Mapping 24.3.1 Receive The HDLC controllers need to be assigned a space in the T1/E1 bandwidth in which they will transmit and receive data. The controllers can be mapped to either the FDL (T1), Sa bits (E1), or to channels. If mapped to channels, then any channel or combination of channels, contiguous or not, can be assigned to an HDLC controller. When assigned to a channel(s) any combination of bits within the channel(s) can be avoided.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 RCB8SE 0 H1RTSBS, H2RTSBS HDLC # 1 Receive Time Slot Bits/Sa Bits Select HDLC # 2 Receive Time Slot Bits/Sa Bits Select 96h, A6h 6 RCB7SE 0 5 RCB6SE 0 4 RCB5SE 0 3 RCB4SE 0 2 RCB3SE 0 1 RCB2SE 0 0 RCB1SE 0 Bit 0/Receive Channel Bit 1 Suppress Enable/Sa8 Bit Enable (RCB1SE ). LSB of the channel. Set to one to stop this bit from being used when the HDLC is mapped to time slots.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 24.3.2 Transmit The HxTCS1–HxTCS4 registers are used to assign the transmit controllers to channels 1–24 (T1) or 1–32 (E1), according to the following table.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 TCB8SE 0 H1TTSBS, H2TTSBS HDLC # 1 Transmit Time Slot Bits/Sa Bits Select HDLC # 2 Transmit Time Slot Bits/Sa Bits Select 9Bh, Abh 6 TCB7SE 0 5 TCB6SE 0 4 TCB5SE 0 3 TCB4SE 0 2 TCB3SE 0 1 TCB2SE 0 0 TCB1SE 0 Bit 0/Transmit Channel Bit 1 Suppress Enable / Sa8 Bit Enable (TCB1SE). LSB of the channel. Set to one to stop this bit from being used.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 SR6, SR7 HDLC #1 Status Register 6 HDLC #2 Status Register 7 20h, 22h 6 TMEND 0 5 RPE 0 4 RPS 0 3 RHWM 0 2 RNE 0 1 TLWM 0 0 TNF 0 Bit 0/Transmit FIFO Not Full Condition (TNF). Set when the transmit 128-byte FIFO has at least one byte available. Bit 1/Transmit FIFO Below Low Watermark Condition (TLWM).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 IMR6, IMR7 HDLC # 1 Interrupt Mask Register 6 HDLC # 2 Interrupt Mask Register 7 21h, 23h 6 TMEND 0 5 RPE 0 4 RPS 0 3 RHWM 0 Bit 0/Transmit FIFO Not Full Condition (TNF). 0 = interrupt masked 1 = interrupt enabled–interrupts on rising edge only Bit 1/Transmit FIFO Below Low Watermark Condition (TLWM).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 INFO5, INFO6 HDLC #1 Information Register HDLC #2 Information Register 2Eh, 2Fh 6 — 0 5 TEMPTY 0 4 TFULL 0 3 REMPTY 0 2 PS2 0 1 PS1 0 0 PS0 0 Bits 0 to 2/Receive Packet Status (PS0 to PS2). These are real-time bits indicating the status as of the last read of the receive FIFO.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 24.3.3 FIFO Information The transmit FIFO buffer-available register indicates the number of bytes that can be written into the transmit FIFO. The count from this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 24.3.5 HDLC FIFOS Register Name: Register Description: Register Address: Bit # Name Default 7 THD7 0 H1TF, H2TF HDLC # 1 Transmit FIFO, HDLC # 2 Transmit FIFO 9Dh, Adh 6 THD6 0 5 THD5 0 4 THD4 0 3 THD3 0 2 THD2 0 1 THD1 0 0 THD0 0 1 RHD1 0 0 RHD0 0 Bit 0/Transmit HDLC Data Bit 0 (THD0). LSB of a HDLC packet data byte. Bit 1/Transmit HDLC Data Bit 1 (THD1). Bit 2/Transmit HDLC Data Bit 2 (THD2). Bit 3/Transmit HDLC Data Bit 3 (THD3).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 24.4 Receive HDLC Code Example Below is an example of a receive HDLC routine for controller #1. 1) Reset receive HDLC controller. 2) Set HDLC mode, mapping, and high watermark. 3) Start new message buffer. 4) Enable RPE and RHWM interrupts. 5) Wait for interrupt. 6) Disable RPE and RHWM interrupts. 7) Read HxRPBA register. N = HxRPBA (lower 7 bits are byte count, MSB is status). 8) Read (N AND 7Fh) bytes from receive FIFO and store in message buffer.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 RFDL7 0 RFDL Receive FDL Register C0h 6 RFDL6 0 5 RFDL5 0 4 RFDL4 0 3 RFDL3 0 2 RFDL2 0 1 RFDL1 0 0 RFDL0 0 Bit 0/Receive FDL Bit 0 (RFDL0). LSB of the Received FDL Code. Bit 1/Receive FDL Bit 1 (RFDL1). Bit 2/Receive FDL Bit 2 (RFDL2). Bit 3/Receive FDL Bit 3 (RFDL3). Bit 4/Receive FDL Bit 4 (RFDL4). Bit 5/Receive FDL Bit 5 (RFDL5). Bit 6/Receive FDL Bit 6 (RFDL6).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 24.5.2 Transmit Section The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the transmit FDL register (TFDL). When a new value is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing T1 data stream.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 25. LINE INTERFACE UNIT (LIU) The LIU in the DS21455/DS21458 contains three sections: the receiver, which handles clock and data recovery; the transmitter, which wave-shapes and drives the network line; and the jitter attenuator. These three sections are controlled by the line interface control registers (LIC1–LIC4), which are described below. The LIU has its own T1/E1 mode select bit and can operate independently of the framer function.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 25-2. Basic Unbalanced Network Connections TTIP 0.047F Tx TRING RTIP DS21455/ DS21458 Rx RRING 60* 60* 0.01F *USE 60 WHEN USING INTERNAL TERMINATION FEATURE. 25.1 LIU Operation The analog AMI/HDB3 waveform off of the E1 line or the AMI/B8ZS waveform off of the T1 line is transformer coupled into the RTIP and RRING pins of the DS21455/DS21458.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers There are two ranges of receive sensitivity for both T1 and E1, which is selectable by the user. The EGL bit of LIC1 (LIC1.4) selects the full or limited sensitivity. The resultant E1 or T1 clock derived from MCLK is multiplied by 16 via an internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to form a 16 times over-sampler, which is used to recover the clock and data.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 25.3 LIU Transmitter The DS21455/DS21458 use a phase-lock loop along with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the E1 or T1 line. The waveforms created by the transmitter meet the latest ETSI, ITU, ANSI, and AT&T specifications. The user will select which waveform is to be generated by setting the ETS bit (LIC2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 25.3.3 Transmit BPV Error Insertion When IBPV (LIC2.5) is transitioned from a zero to a one, the device waits for the next occurrence of three consecutive ones to insert a BPV. IBPV must be cleared and set again for another BPV error insertion. 25.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode) The DS21455/DS21458 can transmit the 2.048MHz square-wave synchronization clock. When in E1 mode, to transmit the 2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 25.6 CMI (Code Mark Inversion) Option The DS21455/DS21458 provide a CMI interface for connection to optical transports. This interface is a unipolar 1T2B type of signal. Ones are encoded as either a logical one or zero level for the full duration of the clock period. Zeros are encoded as a zero-to-one transition at the middle of the clock period. Figure 25-4. CMI Coding CLOCK DATA 1 1 0 1 0 0 1 CMI Transmit and receive CMI is enabled via LIC4.7.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 25.7 LIU Control Registers Register Name: Register Description: Register Address: LIC1 Line Interface Control 1 78h Bit # Name Default 6 L1 0 7 L2 0 5 L0 0 4 EGL 0 3 JAS 0 2 JABDS 0 1 DJA 0 0 TPD 0 Bit 0/Transmit Power-Down (TPD). This bit along with the LIUC/TPD pin and the LTS (LBCR.7) bit controls the transmit power-down function. 0 = powers down the transmitter and tri-states the TTIP and TRING pins 1 = normal transmitter operation Table 25-1.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Table 25-2. E1 Mode With Automatic Gain Control Mode Enabled (TLBC.6 = 0) APPLICATION 75 Normal 120 Normal 75 with High Return Loss* 120 with High Return Loss* LIC1.7 (L2) 0 0 1 1 LIC1.6 (L1) 0 0 0 0 LIC1.5 (L0) 0 1 0 1 PSA1 (F1h) 20h 20h 00h 20h PSA2 (F2h) 08h 00h 00h 00h RETURN LOSS N.M.** N.M. 21dB 21dB Rt (1) 0 0 6.2Ω 11.6Ω Table 25-3. E1 Mode With Automatic Gain Control Mode Disabled (TLBC.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TLBC Transmit Line Build-Out Control 7Dh 6 AGCD 0 5 GC5 0 4 GC4 0 3 GC3 0 2 GC2 0 1 GC1 0 0 GC0 0 Bit 0–5/Gain Control Bits 0–5 (GC0–GC5). The GC0 through GC5 bits control the gain setting automatic gain control is disabled. Use the tables below for setting the recommended values.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 ETS 0 LIC2 Line Interface Control 2 79h 6 LIRST 0 5 IBPV 0 4 TUA1 0 3 JAMUX 0 2 — 0 1 SCLD 0 0 CLDS 0 Bit 0/Custom Line Driver Select (CLDS). Setting this bit to a one will redefine the operation of the transmit line driver. When this bit is set to a one and LIC1.5 = LIC1.6 = LIC1.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 LIC3 Line Interface Control 3 7Ah 6 TCES 0 5 RCES 0 4 MM1 0 3 MM0 0 2 RSCLKE 0 1 TSCLKE 0 0 TAOZ 0 Bit 0/Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern (Customer Disconnect Indication Signal) at TTIP and TRING. The transmission of this data pattern is always timed off of TCLK. 0 = disabled 1 = enabled Bit 1/Transmit Synchronization G.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default LIC4 Line Interface Control 4 7Bh 7 CMIE 0 6 CMII 0 5 MPS1 0 4 MPS0 0 3 TT1 0 Bits 0 to 1/Receive Termination Select (RT0 to RT1).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: INFO2 Information Register 2 11h Bit # Name Default 6 BD 0 7 BSYNC 0 5 TCLE 0 4 TOCD 0 3 RL3 0 2 RL2 0 1 RL1 0 0 RL0 0 Bits 0 to 3/Receive Level Bits (RL0 to RL3). Real-time bits. RL3 RL2 RL1 RL0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 RECEIVE LEVEL (dB) Greater than -2.5 -2.5 to -5.0 -5.0 to -7.5 -7.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 ILUT 0 SR1 Status Register 1 16h 6 TIMER 0 5 RSCOS 0 4 JALT 0 3 LRCL 0 2 TCLE 0 1 TOCD 0 0 LOLITC 0 Bit 0/Loss of Line Interface Transmit Clock Condition (LOLITC). Set when TCLKI has not transitioned for one channel time. Bit 1/Transmit Open-Circuit Detect Condition (TOCD). Set when the device detects that the TTIP and TRING outputs are open-circuited.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 ILUT 0 IMR1 Interrupt Mask Register 1 17h 6 TIMER 0 5 RSCOS 0 4 JALT 0 3 LRCL 0 2 TCLE 0 Bit 0/Loss of Transmit Clock Condition (LOLITC). 0 = interrupt masked 1 = interrupt enabled–generates interrupts on rising and falling edges Bit 1/Transmit Open Circuit Detect Condition (TOCD).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 25.8 Recommended Circuits Figure 25-5. Software-Selected Termination, Metallic Protection VCC 1.0 F T1 DVDD 0.01 F 2 T3 1 F1 75/100/110/120  Twisted Pair/Coax TTIP 0.1 F 2 DVSS S3 S1 TRING VCC 2:1 68 F 2 Dallas Semiconductor T1/E1/J1 SCT or LIU VCC RTIP TVDD T2 F2 75/100/110/120  Twisted Pair/Coax 0.1 F 2 T4 1 TVSS S4 S2 RRING RVDD 0.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 25-6. Software-Selected Termination, Longitudinal Protection VCC F1 TTIP 1.0 F T1 0.01 F 2 T3 1 100/110/120  Twisted Pair DVDD 0.1 F 2 DVSS S3 S7 S1 TRING S4 F2 VCC 2:1 68 F 2 Dallas Semiconductor T1/E1/J1 SCT or LIU VCC RTIP F3 S5 100/110/120  Twisted Pair 0.1 F 2 T4 1 TVSS S8 F4 TVDD T2 S2 RRING S6 RVDD 0.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 25.9 Component Specifications Table 25-8. Transformer Specifications SPECIFICATION Turns Ratio (3.3V Applications) Primary Inductance Leakage Inductance Intertwining Capacitance Transmit Transformer DC Resistance Primary (Device Side) Secondary Receive Transformer DC Resistance Primary (Device Side) Secondary RECOMMENDED VALUE 1:1 (receive) and 1:2 (transmit) ±2% 600H minimum 1.0H maximum 40pF maximum 1.0Ω maximum 2.0Ω maximum 1.2Ω maximum 1.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 25-7. E1 Transmit Pulse Template 1.2 1.1 269ns SCALED AMPLITUDE (in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 1.0 0.9 0.8 0.7 G.703 Template 194ns 0.6 0.5 219ns 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 -200 -150 -100 -50 0 50 100 150 200 250 TIME (ns) Figure 25-8. T1 Transmit Pulse Template 1.2 1.0 -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 0.9 0.8 0.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 25-9. Jitter Tolerance UNIT INTERVALS (UIpp) 1K DS21458 /455 Tolerance 100 TR 62411 (Dec. 90) 10 ITU-T G.823 1 0.1 10 1 100 1K FREQUENCY (Hz) 10K 100K Figure 25-10. Jitter Attenuation (T1 Mode) -20dB C ve ur A TR 62411 (Dec.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 25-11. Jitter Attenuation (E1 Mode) JITTER ATTENUATION (dB) 0dB TBR12 Prohibited Area ITU G.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 26. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION The DS21455/DS21458 can generate and detect a repeating bit pattern from 1 bit to 8 bits or 16 bits in length. This function is available only in T1 mode. To transmit a pattern, the user will load the pattern to be sent into the transmit code definition registers (TCD1 and TCD2) and select the proper length of the pattern by setting the TC0 and TC1 bits in the in-band code-control (IBCC) register.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 TC1 0 IBCC In-Band Code Control Register B6h 6 TC0 0 5 RUP2 0 4 RUP1 0 3 RUP0 0 2 RDN2 0 Bits 0 to 2/Receive-Down Code Length Definition Bits (RDN0 to RDN2). RDN2 0 0 0 0 1 1 1 1 RDN1 0 0 1 1 0 0 1 1 RDN0 0 1 0 1 0 1 0 1 LENGTH SELECTED (Bits) 1 2 3 4 5 6 7 8/16 Bits 3 to 5/Receive-Up Code Length Definition Bits (RUP0 to RUP2).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: TCD1 Transmit Code Definition Register 1 B7h Bit # Name Default 6 C6 0 7 C7 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit 0/Transmit Code Definition Bit 0 (C0). A “don’t care” if a 5-, 6-, or 7-bit length is selected. Bit 1/Transmit Code Definition Bit 1 (C1). A “don’t care” if a 5-bit or 6-bit length is selected. Bit 2/Transmit Code Definition Bit 2 (C2).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: RUPCD1 Receive-Up Code Definition Register 1 B9h Bit # Name Default 6 C6 0 7 C7 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive-Up Code Definition Bit 0 (C0). A “don’t care” if a 1-bit to 7-bit length is selected. Bit 1/Receive-Up Code Definition Bit 1 (C1). A “don’t care” if a 1-bit to 6-bit length is selected.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: RDNCD1 Receive-Down Code Definition Register 1 BBh Bit # Name Default 6 C6 0 7 C7 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive-Down Code Definition Bit 0 (C0). A “don’t care” if a 1-bit to 7-bit length is selected. Bit 1/Receive-Down Code Definition Bit 1 (C1). A “don’t care” if a 1-bit to 6-bit length is selected.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: RDNCD2 Receive-Down Code Definition Register 2 BCh Bit # Name Default 6 C6 0 7 C7 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit 0/Receive-Down Code Definition Bit 0 (C0). A “don’t care” if a 1-bit to 7-bit length is selected. Bit 1/Receive-Down Code Definition Bit 1 (C1). A “don’t care” if a 1-bit to 7-bit length is selected. Bit 2/Receive-Down Code Definition Bit 2 (C2).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: RSCD1 Receive-Spare Code Definition Register 1 BEh Bit # Name Default 6 C6 0 7 C7 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive-Spare Code Definition Bit 0 (C0). A “don’t care” if a 1-bit to 7-bit length is selected. Bit 1/Receive-Spare Code Definition Bit 1 (C1). A “don’t care” if a 1-bit to 6-bit length is selected.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 27. BERT FUNCTION The BERT (Bit Error-Rate Tester) block can generate and detect both pseudorandom and repeating-bit patterns. It is used to test and stress data-communication links.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 27.1 BERT Register Description Register Name: Register Description: Register Address: Bit # Name Default 7 TC 0 BC1 BERT Control Register 1 E0h 6 TINV 0 5 RINV 0 4 PS2 0 3 PS1 0 2 PS0 0 1 LC 0 0 RESYNC 0 Bit 0/Force Resynchronization (RESYNC). A low-to-high transition will force the receive BERT synchronizer to resynchronize to the incoming data stream.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 EIB2 0 BC2 BERT Control Register 2 E1h 6 EIB1 0 5 EIB0 0 4 SBE 0 3 RPL3 0 2 RPL2 0 1 RPL1 0 0 RPL0 0 Bits 0 to 3/Repetitive Pattern Length Bit 3 (RPL0 to RPL3). RPL0 is the LSB and RPL3 is the MSB of a nibble that describes the how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 BIC BERT Interface Control Register EAh 6 RFUS 0 5 — 0 4 TBAT 0 3 TFUS 0 2 — 0 1 BERTDIR 0 0 BERTEN 0 Bit 0/BERT Enable (BERTEN). 0 = BERT disabled 1 = BERT enabled Bit 1/BERT Direction (BERTDIR). 0 = network: BERT transmits toward the network (TTIP and TRING) and receives from the network (RTIP and RRING).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 SR9 Status Register 9 26h 6 BBED 0 5 BBCO 0 4 BEC0 0 3 BRA1 0 2 BRA0 0 1 BRLOS 0 0 BSYNC 0 Bit 0/BERT in Synchronization Condition (BSYNC). Will be set when the incoming pattern matches for 32 consecutive bit positions. Refer to BSYNC in INFO2 register for a real-time version of this bit. Bit 1/BERT Receive Loss Of Synchronization Condition (BRLOS).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 IMR9 Interrupt Mask Register 9 27h 6 BBED 0 5 BBCO 0 4 BEC0 0 3 BRA1 0 2 BRA0 0 1 BRLOS 0 0 BSYNC 0 Bit 0/BERT in Synchronization Condition (BSYNC). 0 = interrupt masked 1 = interrupt enabled–interrupts on rising and falling edges Bit 1/Receive Loss Of Synchronization Condition (BRLOS).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 27.2 BERT Repetitive Pattern Set These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern, or a Daly pattern. For a repetitive pattern that is less than 32 bits, the pattern should be repeated so that all 32 bits are used to describe the pattern.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 27.3 BERT Bit Counter Once the BERT has achieved synchronization, this 32-bit counter will increment for each data bit (i.e., clock) received. Toggling the LC control bit in BC1 can clear this counter, which saturates when full and will set the BBCO status bit.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 27.4 BERT Error Counter Once the BERT has achieved synchronization, this 24-bit counter will increment for each data bit received in error. Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and will set the BECO status bit.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 28. PAYLOAD ERROR INSERTION FUNCTION An error-insertion function is available in the DS21455/DS21458 and is used to create errors in the payload portion of the T1 frame in the transmit path. Errors can be inserted over the entire frame or on a per-channel basis. The user can select all DS0s or any combination of DS0s. See the Special Per-Channel Registration Operation section for information on using the per-channel function.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: ERC Error Rate Control Register EBh Bit # Name Default 6 — 0 7 WNOE 0 5 — 0 4 CE 0 3 ER3 0 2 ER2 0 1 ER1 0 0 ER0 0 Bits 0 to 3/Error Insertion Rate Select Bits (ER0 to ER3).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 28.1 Number of Error Registers The number of error registers determines how many errors will be generated. Up to 1023 errors can be generated. The host will load the number of errors to be generated into the NOE1 and NOE2 registers. The host can also update the number of errors to be created by first loading the prescribed value into the NOE registers and then toggling the WNOE bit in the error rate control registers. Table 28-2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 28.1.1 Number of Errors Left Register The host can read the NOELx registers at any time to determine how many errors are left to be inserted. Register Name: Register Description: Register Address: NOEL1 Number of Errors Left 1 EEh Bit # Name Default 6 C6 0 7 C7 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bits 0 to 7/Number of Errors Left Counter Bits 0 to 7 (C0 to C7). Bit C0 is the LSB of the 10-bit counter.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 29. INTERLEAVED PCM BUS OPERATION In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The DS21455/DS21458 can be configured to allow PCM data to be multiplexed into higher speed buses eliminating external hardware, saving board space and cost. The DS21455/DS21458 can be configured for channel or frame interleave.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default IBOC Interleave Bus Operation Control Register C5h 7 — 0 6 IBS1 0 5 IBS0 0 4 IBOSEL 0 3 IBOEN 0 2 DA2 0 1 DA1 0 0 DA0 0 Bits 0 to 2/Device Assignment bits (DA0 to DA2).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 29-1. IBO Example DS21455 or DS21458 RSYSCLK1 TSYSCLK1 RSYNC1 TSSYNC1 RSIG1 TSIG1 TSER1 SCT #1 RSER1 8.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 30. EXTENDED SYSTEM INFORMATION BUS (ESIB) The ESIB function is carried forward from the previous generation of single port transceiver devices such as the DS2155 and DS2156. This function allows the host to read interrupt and alarm status of multiple ports, up to 8, with a single read of any one of the devices in the ESIB group.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 30-1. DS21455 ESIB Group DS21455 #2 DS21455 #1 PORT # 1 PORT #5 ESIBS0_1 ESIBS0_1 ESIBS1_1 ESIBS1_1 ESIBRD_1 ESIBRD_1 PORT # 2 PORT # 6 ESIBS0_2 ESIBS0_2 ESIBS1_2 ESIBS1_2 ESIBRD_2 ESIBRD_2 PORT # 3 PORT # 7 ESIBS0_3 ESIBS0_3 ESIBS1_3 ESIBS1_3 ESIBRD_3 ESIBRD_3 PORT # 4 PORT # 8 ESIBS0_4 ESIBS0_4 ESIBS1_4 ESIBS1_4 ESIBRD_4 ESIBRD_4 CPU I/F CPU I/F NOTE: UP TO 8 PORTS (TWO DS21455s) CAN BE ARRANGED INTO AN ESIB GROUP.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 30-2. DS21458 ESIB Group DS21458 #2 DS21458 #1 PORT # 1 PORT # 5 ESIBS0 ESIBS1 ESIBRD PORT # 2 PORT #6 PORT # 3 PORT # 7 PORT # 4 PORT # 8 CPU I/F CPU I/F NOTE: UP TO 8 PORTS (TWO DS21458s) CAN BE ARRANGED INTO AN ESIB GROUP. ON THE DS21458, THE ESIB IS INTERNALLY CONNECTED FOR EACH OF THE FOUR TRANSCEIVERS.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: ESIBCR1 Extended System Information Bus Control Register 1 B0h Bit # Name Default 6 — 0 7 — 0 5 — 0 4 — 0 3 ESIBSEL2 0 2 ESIBSEL1 0 1 ESIBSEL0 0 0 ESIEN 0 Bit 0/Extended System Information Bus Enable (ESIEN). 0 = disabled 1 = enabled Bits 1 to 3/Output Data Bus Line Select (ESIBSEL0 to ESIBSEL2).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: Bit # Name Default ESIBCR2 Extended System Information Bus Control Register 2 B1h 7 — 0 6 ESI4SEL2 0 5 ESI4SEL1 0 4 ESI4SEL0 0 3 — 0 2 ESI3SEL2 0 1 ESI3SEL1 0 0 ESI3SEL0 0 Bits 0 to 2/Address ESI3 Data Output Select (ESI3SEL0 to ESI3SEL2). These bits select what status is to be output when the device decodes an ESI3 address during a bus read operation.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Register Name: Register Description: Register Address: ESIB1 Extended System Information Bus Register 1 B2h Bit # Name Default 6 DISn 0 7 DISn 0 5 DISn 0 4 DISn 0 3 DISn 0 2 DISn 0 1 DISn 0 0 DISn 0 Bits 0 to 7/Device Interrupt Status (DISn). Causes all devices participating in the ESIB group to output their interrupt status on the appropriate data bus line selected by the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR1 register.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 31. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER The DS21455/DS21458 contain an on-chip clock synthesizer that generates a user-selectable clock referenced to the recovered receive clock (RCLK). The synthesizer uses a phase-locked loop to generate low-jitter clocks. Common applications include generation of port and backplane system clocks.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 32. FRACTIONAL T1/E1 SUPPORT The DS21455/DS21458 can be programmed to output gapped clocks for selected channels in the receive and transmit paths to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN-PRI applications. This is accomplished by assigning an alternate function to the RCHCLK and TCHCLK pins. When the gapped clock feature is enabled, a gated clock is output on the RCHCLK and/or TCHCLK pins.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 33. USER-PROGRAMMABLE OUTPUT PINS The DS21455/DS21458 provide four user-programmable output pins. The pins are automatically cleared to zero at power-up or as a reset of a hardware- or software-issued reset. Register Name: Register Description: Register Address: Bit # Name Default CCR4 Common Control Register 4 73h 7 RLT3 0 6 RLT2 0 5 RLT1 0 4 RLT0 0 3 — 0 Bit 0/Unused, must be set to zero for proper operation.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 34. TRANSMIT FLOW DIAGRAMS Figure 34-1. T1 Transmit Data Flow TSIG TSER T1 TRANSMIT FLOW DIAGRAM Hardware Signaling HSIE1-3 through PCPR TX ESTORE KEY - PIN Estore Mux ESCR.4 TESE - SELECTOR RDATA From T1_rcv_logic LBCR1.1 PLB Payload Loopback HDLC Engine #1 TLINK H1TC.4 THMS1 - REGISTER HDLC FDL #1 THMS1 H1TC.4 H1TCS1-3 H1TTSBS HDLC Mux #1 HDLC Engine #2 H2TC.4 THMS2 TFDL T1TCR2.5 TZSE THMS2 H2TC.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 34-2. T1 Transmit Data Flow (continued) From ESF Yellow Alarm From BOC Mux From F-bit Mux TFPT T1TCR1.5 FDL Mux TFM T1CCR1.2 ESF Yellow TYEL T1TCR1.0 CRC Mux TCPT T1TCR1.5 D4 bit 2 Yellow Alm BERT Engine TFM T1CCR1.2 TD4YM T1TCR2.2 TYEL T1TCR1.0 TFUS BIC.3 F-bit BERT Mux BERTEN BIC.0 T1TCR2.3 FBCT1 T1TCR2.4 FBCT2 BTCS1-3 F-bit Corruption from PCPR Payload error insertion NOEL != 0 ERC.4 CE SSIE1-3 PEICS1-3 Bit 7 stuffing T1CCR1.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 34-3. E1 Transmit Data Flow TSER HSIE1-4 through PCPR E1 TRANSMIT FLOW DIAGRAM TSIG Hardware Signaling tx_hsig_buf KEY TX ESTORE - PIN ESCR.4 TESE Estore Mux - SELECTOR RDATA From E1_rcv_logic LBCR1.1 PLB Payload Loopback Mux - REGISTER HDLC Engine #1 THMS1 H1TC.4 HDLC DS0 Mux #1 H1TCS1-4 H1TTSBS THMS1 H1TC.4 HDLC Sa-bit Mux #1 T1SaBE4T1SaBE8 H1TTSBS.4 - H1TTSBS.0 HDLC Engine #2 THMS2 H2TC.4 H2TCS1-4 H2TTSBS HDLC DS0 Mux #2 THMS2 H2TC.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 34-4. E1 Transmit Data Flow (continued) From Idle Code Mux RDATA From E1_rcv_logic Per-Channel Loopback E1 TRANSMIT FLOW DIAGRAM PCLR1-4 TNAF THMS1 Sa-bit Mux H1TC.4 THMS2 H2TC.4 TAF/TNAF(non Sa) TS0 Mux E1TCR1.4 TSIS TFPT E1TCR1.7 Si-bit Mux Si = CRC4 MF Align Word (Does not overwrite E-bits) E1TCR1.0 TCRC4 E1TCR2.2 AEBE Sa4S - Sa8S E1TCR2.5 - E1TCR2.7 E1TCR2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 34-5. E1 Transmit Data Flow (continued) From HDB3 Encoding Mux IOCR1.0 ODF Bipolar/ NRZ coding E1 TRANSMIT FLOW DIAGRAM FLB LBCR1.0 FLB Select RPOS TO RECEIVER RNEG RLB Mux RLB Mux RLB LBCR1.2 1/2 CLK/ FULL CLK CCR1.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 35. JTAG-BOUNDARY-SCAN ARCHITECTURE AND TEST-ACCESS PORT The DS21455/DS21458 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGH-Z, CLAMP, and IDCODE. The DS21455/DS21458 contain the following as required by IEEE 1149.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK (Figure 35-2). Test-Logic-Reset Upon power-up, the TAP controller will be in the test-logic-reset state. The instruction register will contain the IDCODE instruction. All system logic of the device will operate normally. Run-Test-Idle The run-test-idle is used between scan operations or during specific tests.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the capture-IR state and will initiate a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the test-logic-reset state.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 35-2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 35.1 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the shift-IR state, the instruction shift register will be connected between JTDI and JTDO. While in the shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial output at JTDO.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers SAMPLE/PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the device can be sampled at the boundary scan register without interfering with the normal operation of the device by using the capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the boundary scan register via JTDI using the shift-DR state.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 35.2 Test Registers IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. An optional test register has been included with the DS21455/DS21458 design. This test register is the identification register and is used with the IDCODE instruction and the test-logic-reset state of the TAP controller. 35.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Table 35-4.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers CELL # NAME TYPE 46 TCLK2 observe_only 47 TNEGI2 observe_only 48 TPOSI2 observe_only 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 TCLKO2 TPOSO2 TNEGO2 RCLKO2 RLINK2 TSYNC2 TSYNC2_CTL TSSYNC2 TLCLK2 TCHCLK2 TCHBLK2 RSYNC2 RSYNC2_CTL RSIGF2 RMSYNC2 RLOS/LOTC2 RLCLK2 RFSYNC2 RCHCLK2 RCHBLK2 observe_only observe_only observe_only observe_only observe_only output3 controlr observe_only observe_only observe_only observe_only output3 controlr
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DS21455/DS21458 Quad T1/E1/J1 Transceivers CONTROL CELL CELL # NAME TYPE 92 TCLK4 observe_only 93 TNEGI4 observe_only 94 TPOSI4 observe_only 95 TCLKO4 observe_only 96 TPOSO4 observe_only 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 TNEGO4 RCLKO4 RLINK4 TSYNC4 TSYNC4_CTL TSSYNC4 TLCLK4 TCHCLK4 TCHBLK4 RSYNC4 RSYNC4_CTL RSIGF4 RMSYNC4 RLOS/LOTC4 RLCLK4 RFSYNC4 RCHCLK4 RCHBLK4 observe_only observe_only observe_only output3 controlr observe_only observe_only observe_
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DS21455/DS21458 Quad T1/E1/J1 Transceivers CONTROL CELL CELL # NAME TYPE 137 A6 observe_only 138 D3/AD3 output3 133 139 D5/AD5 output3 133 140 RCLKI1 observe_only 141 RCLK1 observe_only 142 TSIG1 observe_only 143 TSER1 observe_only 144 TLINK1 observe_only 145 TCLKI1 observe_only 146 TCLK1 observe_only 147 TNEGI1 observe_only 148 TPOSI1 observe_only 149 TCLKO1 observe_only 150 TPOSO1 observe_only 151 TNEGO1 observe_only 152 RCLKO1 observe_only 153 RLINK1
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DS21455/DS21458 Quad T1/E1/J1 Transceivers CONTROL CELL CELL # NAME TYPE 181 RSER1 observe_only 182 RSYSCLK1 observe_only 183 184 TSYSCLK1 CS1/A8 observe_only 185 INT observe_only 186 A2 observe_only 187 A0 observe_only 188 A3 observe_only 189 D7/AD7 output3 133 133 observe_only 190 D6/AD6 output3 191 A7/ALE observe_only 192 RCLKI3 observe_only 193 194 195 196 197 198 199 200 201 202 203 RCLK3 TSIG3 TSER3 TLINK3 TCLKI3 TCLK3 TNEGI3 TPOSI3 TCLKO3 TPOSO3 TNEGO3 observe
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 36. FUNCTIONAL TIMING DIAGRAMS 36.1 T1 Mode Figure 36-1. Receive Side D4 Timing FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 RFSYNC RSYNC 1 RSYNC 2 3 RSYNC RLCLK RLINK 4 NOTES: 1) 2) 3) 4) RSYNC in the frame mode (IOCR1.5 = 0) and double-wide frame sync is not enabled (IOCR1.6 = 0). RSYNC in the frame mode (IOCR1.5 = 0) and double-wide frame sync is enabled (IOCR1.6 = 1). RSYNC in the multiframe mode (IOCR1.5 = 1).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-2. Receive Side ESF Timing FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 1 RSYNC RFSYNC RSYNC RSYNC RLCLK 2 3 4 5 RLINK TLCLK 6 TLINK 7 NOTES: 1) 2) 3) 4) 5) 6) 7) RSYNC in frame mode (IOCR1.4 = 0) and double-wide frame sync is not enabled (IOCR1.6 = 0). RSYNC in frame mode (IOCR1.4 = 0) and double-wide frame sync is enabled (IOCR1.6 = 1). RSYNC in multiframe mode (IOCR1.4 = 1).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-3. Receive Side Boundary Timing (With Elastic Store Disabled) RCLK CHANNEL 23 RSER CHANNEL 24 CHANNEL 1 LSB LSB MSB F MSB RSYNC RFSYNC RSIG CHANNEL 23 A B C/A D/B CHANNEL 24 A B C/A D/B RCHCLK RCHBLK1 RLCLK RLINK 2 NOTES: 1) RCHBLK is programmed to block channel 24. 2) Shown is RLINK/RLCLK in the ESF framing mode.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-4. Receive Side 1.544MHz Boundary Timing (With Elastic Store Enabled) RSYSCLK CHANNEL 23 RSER CHANNEL 24 CHANNEL 1 LSB LSB MSB F MSB RSYNC1 RMSYNC 2 RSYNC RSIG CHANNEL 23 A B C/A D/B CHANNEL 24 A B C/A D/B RCHCLK RCHBLK 3 NOTES: 1) RSYNC is in the output mode (IOCR1.4 = 0). 2) RSYNC is in the input mode (IOCR1.4 = 1). 3) RCHBLK is programmed to block channel 24.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-5. Receive Side 2.048MHz Boundary Timing (With Elastic Store Enabled) RSYSCLK RSER RSYNC 1 CHANNEL 31 CHANNEL 32 CHANNEL 1 LSB LSB MSB 2 RMSYNC 3 RSYNC RSIG A CHANNEL 31 B C/A D/B A CHANNEL 32 B C/A D/B RCHCLK RCHBLK 4 NOTES: 1) 2) 3) 4) 5) RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to one. RSYNC is in the output mode (IOCR1.4 = 0). RSYNC is in the input mode (IOCR1.4 = 1).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-6. Transmit Side D4 Timing FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 1 TSYNC TSSYNC 2 TSYNC 3 TSYNC TLCLK TLINK 4 NOTES: 1) 2) 3) 4) TSYNC in the frame mode (IOCR1.2 = 0) and double-wide frame sync is not enabled (IOCR1.1 = 0). TSYNC in the frame mode (IOCR1.2 = 0) and double-wide frame sync is enabled (IOCR1.1 = 1). TSYNC in the multiframe mode (IOCR1.2 = 1).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-7. Transmit Side ESF Timing FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 TSYNC1 TSSYNC TSYNC 2 3 TSYNC TLCLK 4 TLINK TLCLK TLINK 5 6 NOTES: 1) 2) 3) 4) TSYNC in frame mode (IOCR1.2 = 0) and double-wide frame sync is not enabled (IOCR1.3 = 0). TSYNC in frame mode (IOCR1.2 = 0) and double-wide frame sync is enabled (IOCR1.3 = 1). TSYNC in multiframe mode (IOCR1.2 = 1).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-8. Transmit Side Boundary Timing (With Elastic Store Disabled) TCLK CHANNEL 1 LSB TSER F CHANNEL 2 MSB LSB MSB LSB MSB TSYNC1 TSYNC2 CHANNEL 1 TSIG D/B A B CHANNEL 2 C/A D/B TCHCLK TCHBLK 3 TLCLK TLINK 4 DON'T CARE NOTES: 1) 2) 3) 4) TSYNC is in the output mode (IOCR1.1 = 1). TSYNC is in the input mode (IOCR1.1 = 0). TCHBLK is programmed to block channel 2. Shown is TLINK/TLCLK in the ESF framing mode.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-9. Transmit Side 1.544MHz Boundary Timing (With Elastic Store Enabled) TSYSCLK CHANNEL 23 CHANNEL 24 LSB MSB TSER CHANNEL 1 LSB F MSB TSSYNC CHANNEL 23 TSIG A B CHANNEL 24 C/A D/B A B CHANNEL 1 C/A D/B A TCHCLK TCHBLK 1 NOTE: 1) TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG will be ignored during channel 24).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-10. Transmit Side 2.048MHz Boundary Timing (With Elastic Store Enabled) TSYSCLK CHANNEL 31 TSER 1 CHANNEL 32 LSB MSB CHANNEL 1 LSB F 4 TSSYNC CHANNEL 31 TSIG A B CHANNEL 32 C/A D/B A B CHANNEL 1 C/A D/B A TCHCLK TCHBLK 2,3 NOTES: 1) TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored. 2) TCHBLK is programmed to block channel 31 (if the TPCSI bit is set, then the signaling data at TSIG will be ignored).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 36.2 E1 Mode Figure 36-11. Receive Side Timing FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RFSYNC RSYNC 1 RSYNC 2 RLCLK RLINK 3 4 NOTES: 1) 2) 3) 4) 5) RSYNC in frame mode (IOCR1.5 = 0). RSYNC in multiframe mode (IOCR1.5 = 1). RLCLK is programmed to output just the Sa bits. RLINK will always output all five Sa bits as well as the rest of the receive data stream. This diagram assumes the CAS MF begins in the RAF frame.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-12. Receive Side Boundary Timing (With Elastic Store Disabled) RCLK CHANNEL 32 CHANNEL 1 LSB RSER Si 1 A CHANNEL 2 Sa4 Sa5 Sa6 Sa7 Sa8 MSB RSYNC RFSYNC CHANNEL 32 RSIG A B CHANNEL 1 C D CHANNEL 2 A B Note 4 RCHCLK 1 RCHBLK RLCLK RLINK 2 Sa4 Sa5 Sa6 Sa7 Sa8 NOTES: 1) 2) 3) 4) RCHBLK is programmed to block channel 1. RLCLK is programmed to mark the Sa4 bit in RLINK. Shown is a RNAF frame boundary.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-13. Receive Side Boundary Timing, RSYSCLK = 1.544MHz (With Elastic Store Enabled) RSYSCLK CHANNEL 23/31 1 RSER CHANNEL 24/32 CHANNEL 1/2 LSB LSB MSB F MSB RSYNC2 RMSYNC 3 RSYNC RCHCLK RCHBLK 4 NOTES: 1) Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is mapped to channel 1 of the T1 link, etc.) and the F-bit position is added (forced to one). 2) RSYNC in the output mode (IOCR1.4 = 0).
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-14. Receive Side Boundary Timing, RSYSCLK = 2.048MHz (With Elastic Store Enabled) RSYSCLK CHANNEL 31 CHANNEL 32 LSB MSB RSER CHANNEL 1 LSB MSB 1 RSYNC RMSYNC RSYNC 2 RSIG A CHANNEL 31 C B D A CHANNEL 32 C B D CHANNEL 1 Note 4 RCHCLK RCHBLK 3 NOTES: 1) 2) 3) 4) RSYNC is in the output mode (IOCR1.4 = 0). RSYNC is in the input mode (IOCR1.4 = 1). RCHBLK is programmed to block channel 1.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-15.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-16.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-17. G.802 Timing, E1 Mode Only TS # 31 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 RSYNC TSYNC RCHCLK TCHCLK RCHBLK TCHBLK RCLK / RSYSCLK TCLK / TSYSCLK CHANNEL 25 RSER / TSER CHANNEL 26 LSB MSB RCHCLK / TCHCLK RCHBLK / TCHBLK NOTE: 1) RCHBLK or TCHBLK programmed to pulse high during time slots 1 through 15, 17 through 25, and bit 1 of time slot 26.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-18. Transmit Side Timing FRAME# 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 1 TSYNC TSSYNC TSYNC TLCLK TLINK 2 3 3 NOTES: 1) 2) 3) 4) 5) TSYNC in frame mode (IOCR1.2 = 0). TSYNC in multiframe mode (IOCR1.2 = 1). TLINK is programmed to source just the Sa4 bit. This diagram assumes both the CAS MF and the CRC-4 MF begin with the TAF frame. TLINK and TLCLK are not synchronous with TSSYNC.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-19. Transmit Side Boundary Timing (With Elastic Store Disabled) TCLK CHANNEL 1 LSB TSER Si 1 A CHANNEL 2 Sa4 Sa5 Sa6 Sa7 Sa8 MSB LSB MSB TSYNC1 TSYNC2 CHANNEL 1 TSIG CHANNEL 2 D A B C D TCHCLK TCHBLK 3 TLCLK TLINK 4 4 DON'T CARE DON'T CARE NOTES: 1) 2) 3) 4) 5) TSYNC is in the output mode (IOCR1.1 = 1.) TSYNC is in the input mode (IOCR1.1 = 0). TCHBLK is programmed to block channel 2. TLINK is programmed to source the Sa4 bit.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-20. Transmit Side Boundary Timing, TSYSCLK = 1.544MHz (With Elastic Store Enabled) TSYSCLK CHANNEL 23 1 TSER CHANNEL 24 LSB MSB TSSYNC TCHCLK TCHBLK CHANNEL 1 LSB 2 NOTES: 1) The F-bit position in the TSER data is ignored. 2) TCHBLK is programmed to block channel 24.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-21. Transmit Side Boundary Timing, TSYSCLK = 2.048MHz (With Elastic Store Enabled) TSYSCLK CHANNEL 31 TSER CHANNEL 32 1 CHANNEL 1 LSB MSB LSB F 4 TSSYNC CHANNEL 31 TSIG A B CHANNEL 32 C D A TCHCLK TCHBLK 2,3 NOTE: 1) TCHBLK is programmed to block channel 31.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-22.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 36-23.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 37. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………..-1.0V to +6.0V Operating Temperature Range for DS21455/DS21458………………………………………0C to +70C Operating Temperature Range for DS21455N/DS21458N………………………………...-40C to +85C Storage Temperature Range……………………………………………………………….-55C to +125C Soldering Temperature ………………………………………………………..
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DS21455/DS21458 Quad T1/E1/J1 Transceivers RECOMMENDED DC OPERATING CONDITIONS (TA = 0C to +70C for DS21455/DS21458; TA = -40C to +85C for DS21455N/DS21458N.) PARAMETER Logic 1 Logic 0 Supply SYMBOL VIH VIL VDD MIN 2.0 -0.3 3.135 TYP SYMBOL CIN COUT MIN TYP 5 7 3.3 MAX 5.5 +0.8 3.465 UNITS V V V NOTES MAX UNITS pF pF NOTES MAX UNITS mA A A mA mA mW NOTES 2 3 4 1 CAPACITANCE (TA = +25C) PARAMETER Input Capacitance Output Capacitance DC CHARACTERISTICS (VDD = 3.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 38. AC TIMING PARAMETERS AND DIAGRAMS Capacitive test loads are 40pF for bus signals, 20pF for all others. 38.1 Multiplexed Bus AC Characteristics AC CHARACTERISTICS–MULTIPLEXED PARALLEL PORT (MUX = 1) (VDD = 3.3V 5%, TA = 0°C to +70°C for DS21455/DS21458; VDD = 3.3V 5%, TA = -40C to +85C for DS21455N/DS21458N.) (See Figure 38-1 to Figure 38-3.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 38-1. Intel Bus Read Timing (BTS = 0 / MUX = 1) t CYC ALE WR PWASH t ASD t ASD t ASED PWEH RD t CH t CS PWEL CS t ASL t DHR t DDR AD0-AD7 t AHL A8 & A9 Figure 38-2.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 38-3.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 38.2 Nonmultiplexed Bus AC Characteristics AC CHARACTERISTICS–NONMULTIPLEXED PARALLEL PORT (MUX = 0) (VDD = 3.3V 5%, TA = 0°C to +70°C for DS21455/DS21458; VDD = 3.3V 5%, TA = -40°C to +85°C for DS21455N/DS21458N.) (See Figure 38-4 to Figure 38-7.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 38-4. Intel Bus Read Timing (BTS = 0 / MUX = 0) A0 to A9 Address Valid D0 to D7 Data Valid t5 WR t1 CS t2 t3 t4 RD* Figure 38-5.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 38-6. Motorola Bus Read Timing (BTS = 1 / MUX = 0) A0 to A9 Address Valid D0 to D7 Data Valid t5 R/W t1 CS t2 t3 t4 DS Figure 38-7.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 38.3 Receive Side AC Characteristics AC CHARACTERISTICS–RECEIVE SIDE (VDD = 3.3V 5%, TA = 0C to +70C for DS21455/DS21458; VDD = 3.3V 5%, TA = -40C to +85C for DS21455N/DS21458N.) (See Figure 38-8 to Figure 38-12.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers AC CHARACTERISTICS–RECEIVE SIDE (continued) (VDD = 3.3V 5%, TA = 0C to +70C for DS21455/DS21458; VDD = 3.3V 5%, TA = -40C to +85C for DS21455N/DS21458N.) (See Figure 38-8 to Figure 38-12.) NOTES: 1) 2) 3) 4) 5) 6) 7) Jitter attenuator enabled in the receive path. Jitter attenuator disabled or enabled in the transmit path. RSYSCLK = 1.544MHz. RSYSCLK = 2.048MHz. RSYSCLK = 4.096MHz. RSYSCLK = 8.192MHz. RSYSCLK = 16.384MHz. Figure 38-8.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 38-9. Receive Side Timing, Elastic Store Disabled (E1 Mode) RCLK t D1 MSB of Channel 1 RSER / RDATA / RSIG t D2 RCHCLK t D2 RCHBLK t D2 RFSYNC / RMSYNC t D2 RSYNC1 t D2 2 RLCLK t D1 RLINK Sa4 to Sa8 Bit Position Notes: 1. RSYNC is in the output mode (RCR1.5 = 0). 2. RLCLK will only pulse high during Sa bit locations as defined in RCR2; no relationship between RLCLK and RSYNC or RFSYNC is implied.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 38-10. Receive Side Timing, Elastic Store Enabled (T1 Mode) t SL tF tR t SH RSYSCLK t SP t D3 F-BIT RSER / RSIG t D4 RCHCLK t D4 RCHBLK t D4 RMSYNC RSYNC RSYNC 1 t D4 t HD 2 t SU NOTES: 1) RSYNC is in the output mode. 2) RSYNC is in the input mode.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 38-11. Receive Side Timing, Elastic Store Enabled (E1 Mode) t SL tF tR t SH RSYSCLK t SP t D3 MSB of Channel 1 RSER / RSIG t D4 RCHCLK t D4 RCHBLK t D4 RMSYNC / CO t D4 RSYNC1 t HD t SU 2 RSYNC t SC t WC CI NOTES: 1) RSYNC is in the output mode. 2) RSYNC is in the input mode.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 38-12.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 38.4 Transmit AC Characteristics AC CHARACTERISTICS–TRANSMIT SIDE (VDD = 3.3V 5%, TA = 0°C to +70°C for DS21455/DS21458; VDD = 3.3V 5%, TA = -40°C to +85°C; for DS21455N/DS21458N.) (See Figure 38-13 to Figure 38-15.) PARAMETER SYMBOL TCLK Period tCP TCLK Pulse Width tCH tCL TCLKI Period tLP TCLKI Pulse Width tLH tLL MIN 20 20 20 20 TYP (E1) 488 (E1) 648 (T1) 0.5 tCP 0.5 tCP 488 (E1) 648 (T1) 0.5 tLP 0.5 tLP 648 448 244 122 61 0.5 tSP 0.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 38-13. Transmit Side Timing t CP t CL tF tR t CH TCLK t D1 TESO t SU TSER / TSIG / TDATA t HD t D2 TCHCLK t D2 TCHBLK t D2 TSYNC1 t SU t HD TSYNC2 5 TLCLK t D2 t HD TLINK t SU NOTES: 1) TSYNC is in the output mode (TCR2.2 = 1). 2) TSYNC is in the input mode (TCR2.2 = 0). 3) TSER is sampled on the falling edge of TCLK when the transmit-side elastic store is disabled.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 38-14. Transmit Side Timing, Elastic Store Enabled t SP t SL tF tR t SH TSYSCLK t SU TSER t D3 t HD TCHCLK t D3 TCHBLK t SU t HD TSSYNC NOTES: 1) TSER is only sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled. 2) TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit-side elastic store is enabled.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers Figure 38-15. Transmit Line Interface Timing TCLKO TPOSO, TNEGO t DD tR t LP t LL tF t LH TCLKI t SU TPOSI, TNEGI t HD NOTES: 1) TSER is only sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled. 2) TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit-side elastic store is enabled.
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DS21455/DS21458 Quad T1/E1/J1 Transceivers 39. PACKAGE INFORMATION For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO.