Datasheet

ManualsBrandsMAXIM INTEGRATED ManualsInterface ICsInterface IC - telecommunication LIU TQFP 44

1 of 73 REV: 011206

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device

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FEATURES

 Complete E1, T1, or J1 Line Interface Unit

(LIU)

 Supports Both Long- and Short-Haul Trunks

 Internal Software-Selectable Receive-Side

Termination for 75Ω/100Ω/120Ω

 5V Power Supply

 32-Bit or 128-Bit Crystal-Less Jitter

Attenuator Requires Only a 2.048MHz

Master Clock for Both E1 and T1 with

Option to Use 1.544MHz for T1

 Generates the Appropriate Line Build-Outs,

With and Without Return Loss, for E1 and

DSX-1 and CSU Line Build-Outs for T1

 AMI, HDB3, and B8ZS, Encoding/Decoding

 16.384MHz, 8.192MHz, 4.096MHz, or

2.048MHz Clock Output Synthesized to

Recovered Clock

 Programmable Monitor Mode for Receiver

 Loopbacks and PRBS Pattern Generation/

Detection with Output for Received Errors

 Generates/Detects In-Band Loop Codes, 1 to

16 Bits including CSU Loop Codes

 8-Bit Parallel or Serial Interface with

Optional Hardware Mode

 Multiplexed and Nonmultiplexed Parallel

Bus Supports Intel or Motorola

 Detects/Generates Blue (AIS) Alarms

 NRZ/Bipolar Interface for Tx/Rx Data I/O

 Transmit Open-Circuit Detection

 Receive Carrier Loss (RCL) Indication

(G.775)

 High-Z State for TTIP and TRING

 50mA (RMS) Current Limiter

PIN CONFIGURATION

ORDERING INFORMATION

PART CHANNEL

TEMP

RANGE

PIN-

PACKAGE

DS2148TN Single

-40°C to +85°C

44 TQFP

DS2148TN+ S i ngle

-40°C to +85°C

44 TQFP

DS2148T Single

0°C to +70°C

44 TQFP

DS2148T+ Single

0°C to +70°C

44 TQFP

DS2148GN Single

-40°C to +85°C

49 CSBGA

DS2148GN Single

-40°C to +85°C

49 CSBGA

DS2148G Single

0°C to +70°C

49 CSBGA

DS2148G+ Single

0°C to +70°C

49 CSBGA

DS21Q48N Four

-40°C to +85°C

144 CSBGA

DS21Q48 Four

0°C to +70°C

144 CSBGA

+ Denotes lead-free/RoHS-compliant package.

DS2148/DS21Q48

5V E1/T1/J1 Line Interface Unit

www.maxim-ic.com

DS2148

49 CSBGA

(7mm x 7mm)

44 TQFP

DS2148

TOP VIEW

See Section

for 14

in CSBGA

inout.

Summary of content (73 pages)

PAGE 1
DS2148/DS21Q48 5V E1/T1/J1 Line Interface Unit www.maxim-ic.com PIN CONFIGURATION FEATURES Complete E1, T1, or J1 Line Interface Unit (LIU) Supports Both Long- and Short-Haul Trunks Internal Software-Selectable Receive-Side Termination for 75Ω/100Ω/120Ω 5V Power Supply 32-Bit or 128-Bit Crystal-Less Jitter Attenuator Requires Only a 2.048MHz Master Clock for Both E1 and T1 with Option to Use 1.
PAGE 2
DS2148/DS21Q48 TABLE OF CONTENTS 1 DETAILED DESCRIPTION .................................................................................................. 5 1.1 1.2 FUNCTION DESCRIPTION..................................................................................................................5 DOCUMENT REVISION HISTORY .......................................................................................................6 2 PIN DESCRIPTION..........................................................
PAGE 3
DS2148/DS21Q48 LIST OF FIGURES Figure 1-1. DS2148 Block Diagram ............................................................................................................7 Figure 1-2. Receive Logic...........................................................................................................................8 Figure 1-3. Transmit Logic..........................................................................................................................9 Figure 2-1.
PAGE 4
DS2148/DS21Q48 LIST OF TABLES Table 2-1. Bus Interface Selection ...........................................................................................................10 Table 2-2. Pin Assignment in Parallel Port Mode .....................................................................................10 Table 2-3. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name, DS2148T) ...............................12 Table 2-4. Pin Assignment in Serial Port Mode ........................................
PAGE 5
DS2148/DS21Q48 1 DETAILED DESCRIPTION The DS2148 is a complete selectable E1 or T1 Line Interface Unit (LIU) for short- and long-haul applications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0dB to 12dB or 0dB to 43dB for E1 applications and 0dB to 30dB or 0dB to 36dB for T1 applications. The device can generate the necessary G.
PAGE 6
DS2148/DS21Q48 1.2 Document Revision History 1) 2) 3) 4) 100Ω/60Ω termination reversed in Internal Rx Termination Select tables, 091799. Add DS21Q48 pinout, 092899. Correct VSM pin number in Q48 (12 x 12 BGA) from G5 to G4, 120699. Add timing diagram for Status Register (write access mode); Add mechanical dimensions for the quad version, 032900. 5) Timing diagram for Status Register (write access mode) added; elaboration on burst mode bit; add mechanical dimensions for the quad version, 050300.
PAGE 7
DS2148/DS21Q48 MCLK VSM VSS VDD Figure 1-1. DS2148 Block Diagram 2 2 JACLK Jitter Attenuator MUX Power Connections 2.048MHz to 1.544MHz PLL 16.384MHz or 8.192MHz or 4.096MHz or 2.
PAGE 8
DS2148/DS21Q48 Figure 1-2. Receive Logic Clock Invert From Remote Loopback Routed to All Blocks RCLK CCR2.0 RPOS mux B8ZS/HDB3 Decoder NRZ Data RNEG BPV/CV/EXZ CCR1.6 4 or 8 Zero Detect 16 Zero Detect CCR2.3 CCR6.2/ RIR1.5 CCR6.0/ CCR6.1 All Ones Detector SR.4 RIR1.3 RIR1.7 Loop Code Detector SR.6 SR.7 PBEO PRBS Detector SR.0 mux CCR6.0 RIR1.6 CCR1.
PAGE 9
DS2148/DS21Q48 Figure 1-3. Transmit Logic CCR3.3 CCR1.6 CCR3.4 CCR2.2 CCR3.1 PRBS Generator CCR3.0 OR Gate mux 1 To Remote Loopback BPV Insert B8ZS/ HDB3 Coder Loop Code Generator Logic Error Insert TPOS OR Gate TNEG mux 0 0 0 Clock Invert mux Routed to All Blocks JACLK (derived from MCLK) 1 mux 1 RCLK OR Gate CCR2.1 AND Gate CCR1.1 Loss Of Transmit Clock Detect CCR1.2 CCR1.0 tx bd To LOTC Output Pin 9 of 73 SR.
PAGE 10
DS2148/DS21Q48 2 PIN DESCRIPTION The DS2148 can be controlled in a parallel port mode, a serial port mode, or a hardware mode (Table 2-1, Table 2-2, and Table 2-3). The parallel and serial port modes are described in Section 3.2 and 3.3, and the hardware mode is described below. Table 2-1. Bus Interface Selection BIS1 0 0 0 0 1 1 BIS0 0 0 1 1 0 1 PBTS 0 1 0 1 - BUS INTERFACE TYPE Muxed Intel Muxed Motorola Nonmuxed Intel Nonmuxed Motorola Serial Port Hardware Table 2-2.
PAGE 11
DS2148/DS21Q48 DS2148T PIN # 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 DS2148G PIN# C6 C7 B6 B7 A7 C5 B5 A6 B4 C4 A4 B3 A3 B2 A2 A1 I/O I I O I I O O O O O I I I I PARALLEL PORT MODE HRST MCLK BPCLK BIS0 BIS1 TTIP VSS VDD TRING RPOS RNEG RCLK TPOS TNEG TCLK PBTS 11 of 73
PAGE 12
DS2148/DS21Q48 Table 2-3. Pin Descriptions in Parallel Port Mode (Sorted by Pin Name, DS2148T) NAME A0 to A4 PIN 11 to 7 I/O ALE(AS) 4 I BIS0/BIS1 32/33 I BPCLK 31 O CS D0/AD0 to D7/AD7 1 19 to 12 I HRST 29 I INT 23 O MCLK 30 I NA - I PBEO 24 O PBTS 44 I RCLK 40 O RD(DS) 2 I RCL/LOTC 25 O I I/O FUNCTION Address Bus. In nonmultiplexed bus operation (BIS1 = 0, BIS0 = 1), serves as the address bus.
PAGE 13
DS2148/DS21Q48 NAME PIN I/O RNEG 39 O RPOS 38 O RTIP/RRING 27/28 I TCLK 43 I TEST 26 I TNEG 42 I TPOS 41 I TTIP/TRING 34/37 O VDD VSM VSS WR (R/W) 21/36 20 22/35 I - 3 I FUNCTION Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the falling edge (CCR2.0 = 1) of RCLK with the bipolar data out of the line interface. Set NRZE (CCR1.6) to a one for NRZ applications.
PAGE 14
DS2148/DS21Q48 Table 2-4.
PAGE 15
DS2148/DS21Q48 Table 2-5. Pin Descriptions in Serial Port Mode (Sorted by Pin Name, DS2148T) NAME PIN I/O BIS0/BIS1 32/33 I BPCLK 31 O CS 1 I HRST 29 I ICES 8 I INT 23 O MCLK 30 I NA - I OCES 9 I PBEO 24 O RCLK 40 O RCL/LOTC 25 O RNEG 39 O RPOS 38 O RTIP/RRING 27/28 I SCLK 5 I FUNCTION Bus Interface Select Bits 0 & 1. Used to select bus interface option. See Table 2-1 for details. Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or 2.
PAGE 16
DS2148/DS21Q48 NAME PIN I/O SDI 6 I SDO 7 O TCLK 43 I TEST 26 I TNEG 42 I TPOS 41 I TTIP/TRING 34/37 O VDD VSM VSS 21/36 20 22/35 I - FUNCTION Serial Data Input. Sampled on rising edge (ICES = 0) or the falling edge (ICES = 1) of SCLK. Serial Data Output. Valid on the falling edge (OCES = 0) or the rising edge (OCES = 1) of SCLK. Transmit Clock. A 2.048 MHz or 1.544 MHz primary clock. Used to clock data through the transmit side formatter.
PAGE 17
DS2148/DS21Q48 Table 2-6.
PAGE 18
DS2148/DS21Q48 Table 2-7. Pin Description in Hardware Mode (Sorted by Pin Name, DS2148T) NAME PIN I/O BIS0/BIS1 32/33 I BPCLK 31 O CES 12 I DJA 8 I EGL 1 I ETS 2 I HBE 11 I HRST 29 I JAMUX 9 I JAS 10 I L0/L1/L2 7/6/5 I LOOP0/ LOOP1 16/17 I MCLK 30 I MM0/MM1 18/19 I NA - I FUNCTION Bus Interface Select Bits 0 & 1. Used to select bus interface option. BIS0 = 1 and BIS1 = 1 selects hardware mode. Backplane Clock. 16.384MHz output.
PAGE 19
DS2148/DS21Q48 NAME PIN I/O NRZE 3 I PBEO 24 O RCLK 40 O RCL 25 O RNEG 39 O RPOS 38 O RT0/RT1 44/23 I RTIP/ RRING 27/28 I SCLKE 4 I TCLK 43 I TEST 26 I TNEG 42 I TPD 13 I TPOS 41 I TTIP/ TRING 34/37 O TX0/TX1 14/15 I VDD VSM VSS 21/36 20 22/35 I - FUNCTION NRZ Enable [H/W Mode] 0 = Bipolar data at RPOS/RNEG and TPOS/TNEG 1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a positive going pulse when device receives a BPV, CV, or EXZ.
PAGE 20
DS2148/DS21Q48 Table 2-8. Loopback Control in Hardware Mode LOOPBACK Remote Loopback Local Loopback Analog Loopback No Loopback SYMBOL RLB LLB ALB – CONTROL BIT CCR6.6 CCR6.7 CCR6.4 – LOOP1 1 1 0 0 LOOP0 1 0 1 0 Table 2-9. Transmit Data Control in Hardware Mode TRANSMIT DATA SYMBOL Transmit Unframed All Ones Transmit Alternating Ones and Zeros Transmit PRBS TPOS and TNEG TUA1 TAOZ TPRBSE – CONTROL BIT CCR3.7 CCR3.5 CCR3.4 – TX1 TX0 1 1 0 0 1 0 1 0 Table 2-10.
PAGE 21
DS2148/DS21Q48 Figure 2-1.
PAGE 22
DS2148/DS21Q48 Figure 2-3.
PAGE 23
DS2148/DS21Q48 3 HARDWARE MODE In hardware mode (BIS1 = 1, BIS0 = 1), pins 1-19, 23, 25, 31, and 44 are redefined to be used for initializing the DS2148. BPCLK (pin 31) defaults to a 16.384MHz output when in hardware mode. The RCL/LOTC (pin 25) is designated to RCL when in hardware mode. JABDS (CCR4.2) defaults to logic 0. The RHBE (CCR2.3) and THBE (CCR2.2) control bits are combined and controlled by HBE at pin 11 while the RSCLKE (CCR5.3) and TSCLKE (CCR5.
PAGE 24
DS2148/DS21Q48 3.2 Parallel Port Operation When using the parallel interface on the DS2148 (BIS1 = 0) the user has the option for either multiplexed bus operation (BIS1 = 0, BIS0 = 0) or nonmultiplexed bus operation (BIS1 = 0, BIS0 = 1). The DS2148 can operate with either Intel or Motorola bus timing configurations. If the PBTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All Motorola bus signals are listed in parentheses.
PAGE 25
DS2148/DS21Q48 Figure 3-1. Serial Port Operation for Read Access (R = 1) Mode 1 ICES = 1 (sample SDI on the falling edge of SCLK) OCES = 1 (update SDO on rising edge of SCLK) SCLK 1 2 3 4 5 6 A0 A1 A2 A3 A4 7 8 9 10 11 12 13 14 15 D0 D1 D2 D3 D4 D5 D6 16 CS SDI 1 0 B (lsb) (msb) READ ACCESS ENABLED SDO D7 (lsb) (msb) Figure 3-2.
PAGE 26
DS2148/DS21Q48 Figure 3-3. Serial Port Operation for Read Access Mode 3 ICES = 0 (sample SDI on the rising edge of SCLK) OCES = 0 (update SDO on falling edge of SCLK) SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CS SDI A0 1 A1 A2 A3 A4 0 B (lsb) (msb) SDO D0 D1 D2 D3 D4 D5 D6 (lsb) D7 (msb) Figure 3-4.
PAGE 27
DS2148/DS21Q48 Figure 3-5. Serial Port Operation for Write Access (R = 0) Modes 1 and 2 ICES = 1 (sample SDI on the falling edge of SCLK) SCLK 1 2 3 4 5 6 A0 A1 A2 A3 A4 7 8 9 10 11 12 13 14 15 16 B DO D1 D2 D3 D4 D5 D6 (msb) (lsb) CS SDI 0 0 (lsb) D7 (msb) WRITE ACCESS ENABLED SDO Figure 3-6.
PAGE 28
DS2148/DS21Q48 4 CONTROL REGISTERS CCR1 (00H): COMMON CONTROL REGISTER 1 (MSB) ETS NRZE RCLA SYMBOL POSITION ETS CCR1.7 NRZE CCR1.6 RCLA CCR1.5 ECUE CCR1.4 JAMUX CCR1.3 TTOJ CCR1.2 TTOR CCR1.1 LOTCMC CCR1.0 ECUE JAMUX TTOJ TTOR (LSB) LOTCMC DESCRIPTION E1/T1 Select. 0 = E1 1 = T1 NRZ Enable. 0 = Bipolar data at RPOS/RNEG and TPOS/TNEG 1 = NRZ data at RPOS and TPOS or TNEG; RNEG outputs a positive going pulse when device receives a BPV, CV, or EXZ. See Figure 1-2 and Figure 1-3.
PAGE 29
DS2148/DS21Q48 Table 4-1. MCLK Selection JAMUX (CCR1.3) 0 1 0 MCLK 2.048MHz 2.048MHz 1.544MHz ETS (CCR1.7) 0 1 1 CCR2 (01H): COMMON CONTROL REGISTER 2 (MSB) P25S N/A SCLD SYMBOL POSITION P25S CCR2.7 SCLD CCR2.6 CCR2.5 CLDS CCR2.4 RHBE CCR2.3 THBE CCR2.2 TCES CCR2.1 RCES CCR2.0 CLDS RHBE THBE TCES (LSB) RCES DESCRIPTION Pin 25 Select. Forced to logic 0 in hardware mode.
PAGE 30
DS2148/DS21Q48 CCR3 (02H): COMMON CONTROL REGISTER 3 (MSB) TUA1 ATUA1 TAOZ SYMBOL POSITION TUA1 CCR3.7 ATUA1 CCR3.6 TAOZ CCR3.5 TPRBSE CCR3.4 TLCE CCR3.3 LIRST CCR3.2 IBPV CCR3.1 IBE CCR3.0 TPRBSE TLCE LIRST IBPV (LSB) IBE DESCRIPTION Transmit Unframed All Ones. The polarity of this bit is set such that the device will transmit an all ones pattern on power-up or device reset. This bit must be set to a one to allow the device to transmit data.
PAGE 31
DS2148/DS21Q48 4.1 Device Power-Up and Reset The DS2148 will reset itself upon power-up, setting all writeable registers to 00h and clearing the status and information registers. CCR3.7 (TUA1) = 0 results in the LIU transmitting unframed all ones. After the power supplies have settled following power-up, initialize all control registers to the desired settings, then toggle the LIRST bit (CCR3.2).
PAGE 32
DS2148/DS21Q48 CCR5 (04H): COMMON CONTROL REGISTER 5 (MSB) BPCS1 BPCS0 MM1 SYMBOL POSITION BPCS1 BPCS0 MM1 MM0 RSCLKE CCR5.7 CCR5.6 CCR5.5 CCR5.4 CCR5.3 TSCLKE CCR5.2 RT1 RT0 CCR5.1 CCR5.0 MM0 RSCLKE BPCS0 (CCR5.6) 0 1 0 1 Backplane Clock Select 1. See Table 4-3 for details. Backplane Clock Select 0. See Table 4-3 for details. Monitor Mode 1. See Table 4-4. Monitor Mode 0. See Table 4-4. Receive Synchronization Clock Enable.
PAGE 33
DS2148/DS21Q48 Table 4-5. Internal Rx Termination Select RT1 (CCR5.1) 0 0 1 1 RT0 (CCR5.0) 0 1 0 1 INTERNAL RECEIVE TERMINATION CONFIGURATION Internal receive-side termination disabled Internal receive-side 120Ω enabled Internal receive-side 100Ω enabled Internal receive-side 75Ω enabled CCR6 (05H): COMMON CONTROL REGISTER 6 (MSB) LLB RLB ARLBE SYMBOL POSITION LLB CCR6.7 RLB CCR6.6 ARLBE CCR6.5 ALB CCR6.4 ALB RJAB ECRS2 ECRS1 (LSB) ECRS0 DESCRIPTION Local Loopback.
PAGE 34
DS2148/DS21Q48 SYMBOL POSITION RJAB CCR6.3 ECRS2 ECRS1 ECRS0 CCR6.2 CCR6.1 CCR6.0 DESCRIPTION RCLK Jitter Attenuator Bypass. This control bit allows the recovered received clock and data to bypass the jitter attenuation while still allowing the BPCLK output to use the jitter attenuator. See Figure 1-1 and Section 7.1 for details. 0 = disabled 1 = enabled Error Count Register Select 2. See Section 6.4 for details. Error Count Register Select 1. See Section 6.4 for details.
PAGE 35
DS2148/DS21Q48 Table 5-1. Received Alarm Criteria ALARM E1/T1 RUA1 E1 RUA1 T1 RCL1 E1 1 RCL T1 SET CRITERIA Less than two zeros in two frames (512 bits) Over a 3ms window, five or less zeros are received 255 (or 2048)2 consecutive zeros received (G.
PAGE 36
DS2148/DS21Q48 IMR (07H): INTERRUPT MASK REGISTER (MSB) LUP LDN LOTC SYMBOL POSITION LUP IMR.7 LDN IMR.6 LOTC IMR.5 RUA1 IMR.4 RCL IMR.3 TCLE IMR.2 TOCD IMR.1 PRBSD IMR.0 RUA1 RCL TCLE DESCRIPTION Loop Up Code Detected. 0 = interrupt masked 1 = interrupt enabled Loop Down Code Detected. 0 = interrupt masked 1 = interrupt enabled Loss of Transmit Clock. 0 = interrupt masked 1 = interrupt enabled Receive Unframed All Ones.
PAGE 37
DS2148/DS21Q48 RIR1 (08H): RECEIVE INFORMATION REGISTER 1 (MSB) ZD 16ZD HBD RCLC RUA1C JALT N/A (LSB) N/A SYMBOL POSITION DESCRIPTION ZD (latched) RIR1.7 16ZD (latched) RIR1.6 HBD (latched) RIR1.5 RCLC (latched) RIR1.4 RUA1C (latched) RIR1.3 JALT (latched) RIR1.2 N/A RIR1.1 Zero Detect. Set when a string of at least four (ETS = 0) or eight (ETS = 1) consecutive zeros (regardless of the length of the string) have been received. Will be cleared when read. Sixteen Zero Detect.
PAGE 38
DS2148/DS21Q48 RIR2 (09H): RECEIVE INFORMATION REGISTER 2 (MSB) RL3 RL2 RL1 RL0 N/A N/A ARLB (LSB) SEC SYMBOL POSITION RL3 (real time) RL2 (real time) RL1 (real time) RL0 (real time) N/A N/A ARLB (real time) RIR2.7 Receive Level Bit 3. See Table 5-2. RIR2.6 Receive Level Bit 2. See Table 5-2. RIR2.5 Receive Level Bit 1. See Table 5-2. RIR2.4 Receive Level Bit 0. See Table 5-2. RIR2.3 RIR2.2 RIR2.1 Not Assigned. Could be any value when read. Not Assigned. Could be any value when read.
PAGE 39
DS2148/DS21Q48 6 DIAGNOSTICS 6.1 In-Band Loop Code Generation and Detection The DS2148 can generate and detect a repeating bit pattern that is from one to eight or sixteen bits in length. To transmit a pattern, the user will load the pattern to be sent into the Transmit Code Definition (TCD1 and TCD2) registers and select the proper length of the pattern by setting the TC0 and TC1 bits in the In-Band Code Control (IBCC) register.
PAGE 40
DS2148/DS21Q48 Table 6-1. Transmit Code Length TC1 TC0 0 0 1 1 0 1 0 1 LENGTH SELECTED (BITS) 5 6/3 7 16/8/4/2/1 Table 6-2. Receive Code Length RUP2/RDN2 RUP1/RDN1 RUP0/RDN0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 LENGTH SELECTED (BITS) 1 2 3 4 5 6 7 16/8 TCD1 (0BH): TRANSMIT CODE DEFINITION REGISTER 1 (MSB) C7 C6 C5 C4 C3 C2 C1 (LSB) C0 SYMBOL POSITION DESCRIPTION C7 TCD1.7 C6 TCD1.6 Transmit Code Definition Bit 7. First bit of the repeating pattern.
PAGE 41
DS2148/DS21Q48 TCD2 (0CH): TRANSMIT CODE DEFINITION REGISTER 2 (MSB) C15 C14 C13 C12 C11 C10 SYMBOL POSITION C15 TCD2.7 Transmit Code Definition Bit 15 C14 TCD2.6 Transmit Code Definition Bit 14 C13 TCD2.5 Transmit Code Definition Bit 13 C12 TCD2.4 Transmit Code Definition Bit 12 C11 TCD2.3 Transmit Code Definition Bit 11 C10 TCD2.2 Transmit Code Definition Bit 10 C9 TCD2.1 Transmit Code Definition Bit 9 C8 TCD2.
PAGE 42
DS2148/DS21Q48 RUPCD2 (0EH): RECEIVE UP CODE DEFINITION REGISTER 2 (MSB) C15 C14 C13 C12 C11 C10 SYMBOL POSITION DESCRIPTION C15 RUPCD2.7 Receive Up Code Definition Bit 15 C14 RUPCD2.6 Receive Up Code Definition Bit 14 C13 RUPCD2.5 Receive Up Code Definition Bit 13 C12 RUPCD2.4 Receive Up Code Definition Bit 12 C11 RUPCD2.3 Receive Up Code Definition Bit 11 C10 RUPCD2.2 Receive Up Code Definition Bit 10 C9 RUPCD2.1 Receive Up Code Definition Bit 9 C8 RUPCD2.
PAGE 43
DS2148/DS21Q48 RDNCD2 (10H): RECEIVE DOWN CODE DEFINITION REGISTER 2 (MSB) C15 C14 C13 C12 C11 C10 SYMBOL POSITION DESCRIPTION C15 RDNCD2.7 Receive Down Code Definition Bit 15 C14 RDNCD2.6 Receive Down Code Definition Bit 14 C13 RDNCD2.5 Receive Down Code Definition Bit 13 C12 RDNCD2.4 Receive Down Code Definition Bit 12 C11 RDNCD2.3 Receive Down Code Definition Bit 11 C10 RDNCD2.2 Receive Down Code Definition Bit 10 C9 RDNCD2.1 Receive Down Code Definition Bit 9 C8 RDNCD2.
PAGE 44
DS2148/DS21Q48 6.2.3 Analog Loopback (ALB) Setting ALB (CCR6.4) to a one puts the DS2148 in Analog Loopback. Signals at TTIP and TRING will be internally connected to RTIP and RRING. The incoming signals at RTIP and RRING will be ignored. The signals at TTIP and TRING will be transmitted as normal. (See Figure 1-1.) 6.2.4 Dual Loopback (DLB) Setting both CCR6.7 and CCR6.6 to a one, LLB and RLB respectively, puts the DS2148 into dual loopback operation.
PAGE 45
DS2148/DS21Q48 Table 6-4. Function of ECRS Bits and RNEG Pin E1 or T1 (CCR1.7) 0 0 0 0 1 1 1 1 X ECRS2 (CCR6.2) 0 0 0 0 0 0 0 0 1 ECRS1 (CCR6.1) 0 0 1 1 X X X X X ECRS0 (CCR6.0) 0 1 0 1 0 1 0 1 X RHBE (CCR2.3) X X X X 0 0 1 1 X FUNCTION OF ECR COUNTERS/RNEG1 CVs BPVs (HDB3 codewords not counted) CVs + EXZs BPVs + EXZs BPVs (B8ZS codewords not counted) BPVs + 8 EXZs BPVs BPVs + 16 EXZs PRBS Errors2 NOTES: 1) RNEG outputs error data only when in NRZ mode (CCR1.6 = 1).
PAGE 46
DS2148/DS21Q48 7 ANALOG INTERFACE 7.1 Receiver The DS2148 contains a digital clock recovery system. The DS2148 couples to the receive E1 or T1 twisted pair (or coaxial cable in 75Ω E1 applications) via a 1:1 transformer. See Table 7-3 or transformer details. Figure 7-1, Figure 7-2, and Figure 7-3 along with Table 7-1 and Table 7-2 show the receive termination requirements. The DS2148 has the option of using internal termination resistors.
PAGE 47
DS2148/DS21Q48 7.2 Transmitter The DS2148 uses a set of laser-trimmed delay lines along with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the E1 or T1 line. The waveforms created by the DS2148 meet the latest ETSI, ITU, ANSI, and AT&T specifications. The user will select which waveform is to be generated by setting the ETS bit (CCR1.7) for E1 or T1 operation, then programming the L2/L1/L0 bits in Common Control Register 4 for the appropriate application.
PAGE 48
DS2148/DS21Q48 7.4 G.703 Synchronization Signal The DS2148 is capable of receiving a 2.048MHz square-wave synchronization clock as specified in Section 13 of ITU G.703 (10/98). To use the DS2148 in this mode, set the receive synchronization clock enable (CCR5.3) = 1. The DS2148 can also transmit the 2.048MHz square-wave synchronization clock as specified in Section 10 of G.703. To transmit the 2.048MHz clock, set the transmit synchronization clock enable (CCR5.2) = 1. Table 7-1.
PAGE 49
DS2148/DS21Q48 Figure 7-1. Basic Interface DS2148 Rt Transmit Line TTIP 0.47µF (non polarized) VDD (21) VSS (22) TRING Rt N:1 (larger winding toward the network) VDD (36) VSS (35) RTIP Receive Line RRING MCLK +VDD 0.1µF 0.01µF 10µF 0.1µF 10µF 2.048MHz (this clock can also be 1.544MHz for T1 only applications) 1:1 Rr Rr 0.1µF NOTES: 1) All resistor values are ±1%. 2) In E1 applications, the Rt resistors are used to increase the transmitter return loss (Table 7-1).
PAGE 50
DS2148/DS21Q48 Figure 7-2. Protected Interface Using Internal Receive Termination +VDD D1 (optional) Rp Fuse Rt Transmit Line Fuse TTIP 0.47uF (nonpolarized) S C1 TRING Rt Rp D3 N:1 (larger winding toward the network) DS2148 D2 D4 VDD (21) VSS (22) VDD (36) VSS (35) +VDD 0.1uF 0.01uF 10uF 68uF 0.1uF 10uF +VDD D6 D5 Fuse Rp RTIP Receive Line S Fuse Rp (optional) C2 RRING MCLK 2.048MHz (this clock can also be 1.544MHz for T1 only applications) 1:1 60 60 D7 D8 0.
PAGE 51
DS2148/DS21Q48 Figure 7-3. Protected Interface Using External Receive Termination +VDD D1 (optional) Rp Fuse Rt Transmit Line Fuse TTIP 0.47µF (nonpolarized) S D3 N:1 (larger winding toward the network) Fuse Rp Fuse Rp C1 TRING Rt Rp D4 470 RTIP Receive Line (optional) RRING 470 1:1 Rr DS2148 D2 VDD (21) VSS (22) VDD (36) VSS (35) MCLK +VDD 0.1µF 0.01µF 10µF 68µF 0.1µF 10µF 2.048MHz (this clock can also be 1.544MHz for T1 only applications) Rr 0.
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DS2148/DS21Q48 Figure 7-4. E1 Transmit Pulse Template 1.2 1.1 269ns SCALED AMPLITUDE (in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 1.0 0.9 0.8 0.7 G.703 Template 194ns 0.6 0.5 219ns 0.4 0.3 0.2 0.1 0 -0.1 -0.
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DS2148/DS21Q48 Figure 7-5. T1 Transmit Pulse Template 1.2 MAXIMUM CURVE UI Time Amp. 1.1 1.0 -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 0.9 0.8 NORMALIZED AMPLITUDE 0.7 0.6 -500 -255 -175 -175 -75 0 175 225 600 750 0.05 0.05 0.80 1.15 1.15 1.05 1.05 -0.07 0.05 0.05 0.5 MINIMUM CURVE UI Time Amp. -0.77 -0.23 -0.23 -0.15 0.00 0.15 0.23 0.23 0.46 0.66 0.93 1.16 -500 -150 -150 -100 0 100 150 150 300 430 600 750 -0.05 -0.05 0.50 0.95 0.95 0.90 0.50 -0.45 -0.45 -0.20 -0.05 -0.05 0.4 0.
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DS2148/DS21Q48 Figure 7-6. Jitter Tolerance UNIT INTERVALS (UIpp) 1K 100 DS2148 Tolerance TR 62411 (Dec. 90) 10 ITU-T G.823 1 0.1 1 10 100 1K FREQUENCY (Hz) 10K 100K Figure 7-7. Jitter Attenuation ITU G.7XX Prohibited Area TBR12 Prohibited Area -20dB C ve ur A E1 T1 TR 62411 (Dec.
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DS2148/DS21Q48 8 DS21Q48 QUAD LIU The DS21Q48 is a quad version of the DS2148G utilizing CSBGA on carrier packaging technology. The four LIUs are controlled via the parallel port mode. Serial and hardware modes are unavailable in this package. Table 8-1.
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DS2148/DS21Q48 DS21Q48 PIN# J7 A1 A4 A7 A10 B2 B5 B8 B11 H4 D6 F10 L8 A2 A5 A8 A11 B3 B6 B9 B12 K4 E1 D11 K11 G2 E2 F11 M10 H3 F1 E11 L11 G1 F2 E12 M11 H2 M1 D12 K12 M2 L2 F12 I/O O I I I I I I I I O O O O O O O O O O O O O O O O O O O O O O O O I I I I I I I I I I I PARALLEL PORT MODE RCL/LOTC4 RTIP1 RTIP2 RTIP3 RTIP4 RRING1 RRING2 RRING3 RRING4 BPCLK1 BPCLK2 BPCLK3 BPCLK4 TTIP1 TTIP2 TTIP3 TTIP4 TRING1 TRING2 TRING3 TRING4 RPOS1 RPOS2 RPOS3 RPOS4 RNEG1 RNEG2 RNEG3 RNEG4 RCLK1 RCLK2 RCLK3 RCLK4 TPOS1 TP
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DS2148/DS21Q48 DS21Q48 PIN# L12 J5 D2 G9 M9 L5 E4 D8 J8 J4 D1 E9 L10 M4 F4 D9 H9 I/O I - PARALLEL PORT MODE TCLK4 VDD1 VDD2 VDD3 VDD4 VDD1 VDD2 VDD3 VDD4 VSS1 VSS2 VSS3 VSS4 VSS1 VSS2 VSS3 VSS4 57 of 73
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DS2148/DS21Q48 Figure 8-1.
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DS2148/DS21Q48 9 DC CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS* Voltage Range on Any Pin Relative to Ground……………………………………………..-1.0V to +6.0V Operating Temperature Range for DS2148TN……………………………………………..-40°C to +85°C Storage Temperature Range……………………………………………………………….-55°C to +125°C Soldering Temperature………………………………………….
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DS2148/DS21Q48 9.1 THERMAL CHARACTERISTICS Table 9-4. Thermal Characteristics—DS21Q48 CSBGA Package PARAMETER Ambient Temperature Junction Temperature Theta-JA (θJA) in Still Air Theta-JC (θJC) in Still Air MIN -40ºC - TYP +24ºC/W +4.1ºC/W MAX +85ºC +125ºC - NOTES 1 2 3 NOTES: 1) The package is mounted on a four-layer JEDEC-standard test board. 2) Theta-JA (θJA) is the junction to ambient thermal resistance, when the package is mounted on a fourlayer JEDEC-standard test board.
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DS2148/DS21Q48 10 AC CHARACTERISTICS Table 10-1. AC Characteristics—Multiplexed Parallel Port (BIS1 = 0, BIS0 = 0) (VDD = 5.0V ±5%, TA = -40°C to +85°C.) (See Figure 10-1, Figure 10-2, and Figure 10-3.
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DS2148/DS21Q48 Figure 10-1. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 0) t CYC ALE WR* PWASH t ASD t ASD t ASED PWEH RD* t CH t CS PWEL CS* t ASL t DHR t DDR AD0-AD7 t AHL Figure 10-2.
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DS2148/DS21Q48 Figure 10-3.
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DS2148/DS21Q48 Table 10-2. AC Characteristics—Nonmultiplexed Parallel Port (BIS1 = 0, BIS0 = 1) (VDD = 5.0V ±5%, TA = -40°C to +85°C.) (See Figure 10-4, Figure 10-5, Figure 10-6, and Figure 10-7.
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DS2148/DS21Q48 Figure 10-4. Intel Bus Read Timing (PBTS = 0, BIS1 = 0, BIS0 = 1) A0 to A4 Address Valid D0 to D7 Data Valid t5 5ns min. / 20ns max. WR* t1 0ns min. CS* 0ns min. t2 t3 75ns max. RD* t4 0ns min. Figure 10-5. Intel Bus Write Timing (PBTS = 0, BIS1 = 0, BIS0 = 1) A0 to A4 Address Valid D0 to D7 t7 10ns min. RD* t1 t8 10ns min. 0ns min. CS* 0ns min. WR* t2 t6 75ns min. 65 of 73 t4 0ns min.
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DS2148/DS21Q48 Figure 10-6. Motorola Bus Read Timing (PBTS = 1, BIS1 = 0, BIS0 = 1) A0 to A4 Address Valid D0 to D7 Data Valid 5ns min. / 20ns max. t5 R/W* t1 0ns min. CS* 0ns min. t2 t3 t4 0ns min. 75ns max. DS* Figure 10-7. Motorola Bus Write Timing (PBTS = 1, BIS1 = 0, BIS0 = 1) A0 to A4 Address Valid D0 to D7 10ns min. R/W* t1 t7 t8 10ns min. 0ns min. CS* 0ns min. DS* t2 t6 75ns min. 66 of 73 t4 0ns min.
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DS2148/DS21Q48 Table 10-3. AC Characteristics—Serial Port (BIS1 = 1, BIS0 = 0) (VDD = 5.0V ±5%, TA = -40°C to +85°C.
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DS2148/DS21Q48 Table 10-4. AC Characteristics—Receive Side (VDD = 5.0V ±5%, TA = -40°C to +85°C.) (See Figure 10-9) PARAMETER SYMBOL MIN TYP 488 RCLK Period tCP 648 tCH 200 RCLK Pulse Width 200 tCL tCH 150 RCLK Pulse Width tCL 150 Delay RCLK to RPOS, RNEG, tDD PBEO, RBPV Valid MAX UNITS ns ns ns ns ns ns 50 ns NOTES: 1) 2) 3) 4) E1 Mode. T1 or J1 Mode. Jitter attenuator enabled in the receive path. Jitter attenuator disabled or enabled in the transmit path. Figure 10-9.
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DS2148/DS21Q48 Table 10-5. AC Characteristics—Transmit Side (VDD = 5.0V ±5%, TA = -40°C to +85°C.) (See Figure 10-10.) PARAMETER SYMBOL MIN TYP 488 TCLK Period tCP 648 tCH 75 TCLK Pulse Width tCL 75 TPOS/TNEG Setup to TCLK tSU 20 Falling or Rising TPOS/TNEG Hold From TCLK tHD 20 Falling or Rising TCLK Rise and Fall Times tR, tF MAX ns ns 25 NOTES: 1) E1 Mode. 2) T1 or J1 Mode. Figure 10-10. Transmit Side Timing t CP tR t CL tF TCLK1 TCLK2 t SU TPOS, TNEG t HD NOTE 1: TCES = 0 (CCR2.1) OR CES = 0.
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DS2148/DS21Q48 11 PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 11.1 44-Pin TQFP (56-G4012-001) SUGGESTED PAD LAYOUT 44 PIN TQFP, 10*10*1.
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DS2148/DS21Q48 11.
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DS2148/DS21Q48 11.3 144-Ball CSBGA (17mm x 17mm) (56-G6011-001) A1 CORNER 3 A1 CORNER 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H I J K L 1.27 17.00 13.97 0.20 1.52 Y 4 17.00 1.27 X 13.97 1.52 DETAIL A TOP VIEW (DIE SIDE) BOTTOM VIEW (BALL SIDE) 0.05 2.60 REF 1.99 0.76 Z DETAIL B SIDE VIEW 72 of 73 0.61 0.
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DS2148/DS21Q48 SOLDER BALL φ 0.76 REF φ 0.76 L X φ 0.76 L Z Y Z DETAIL A 0.05 LABEL THICKNESS // 0.24 Z 2.60 REF // 0.17 Z 0.10 SEATING PLANE 2 0.76 REF Z DETAIL B 73 of 73 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied.