DS2155 T1/E1/J1 Single-Chip Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS2155 is a software-selectable T1, E1, or J1 single-chip transceiver (SCT) for short-haul and long-haul applications. The DS2155 is composed of a line interface unit (LIU), framer, HDLC controllers, and a TDM backplane interface, and is controlled by an 8-bit parallel port configured for Intel or Motorola bus operations. The DS2155 is pin and software compatible with the DS2156.
DS2155 1. TABLE OF CONTENTS 1. TABLE OF CONTENTS ............................................................................................................................2 1.1 1.2 TABLE OF FIGURES ........................................................................................................................................6 TABLE OF TABLES..........................................................................................................................................7 2.
DS2155 12. I/O PIN CONFIGURATION OPTIONS.................................................................................................69 13. LOOPBACK CONFIGURATION ..........................................................................................................71 13.1 14. PER-CHANNEL LOOPBACK ......................................................................................................................73 ERROR COUNT REGISTERS ..........................................................
DS2155 22.1 22.2 22.3 23. METHOD 1: HARDWARE SCHEME .........................................................................................................113 METHOD 2: INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME ..............................................113 METHOD 3: INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME ........................................116 HDLC CONTROLLERS ........................................................................................................................
DS2155 28.1 28.2 CHANNEL INTERLEAVE .........................................................................................................................184 FRAME INTERLEAVE ..............................................................................................................................184 29. EXTENDED SYSTEM INFORMATION BUS (ESIB) .......................................................................187 30. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER ....................................
DS2155 1.1 Table of Figures Figure 3-1. Block Diagram ........................................................................................................................................ 15 Figure 3-2. Receive and Transmit LIU...................................................................................................................... 16 Figure 3-3. Receive and Transmit Framer/HDLC .....................................................................................................
DS2155 Figure 35-23. Transmit IBO Frame Interleave Mode Timing ................................................................................. 221 Figure 37-1. Intel Multiplexed Bus Read Timing (BTS = 0/MUX = 1).................................................................. 225 Figure 37-2. Intel Multiplexed Bus Write Timing (BTS = 0/MUX = 1)................................................................. 225 Figure 37-3. Motorola Multiplexed Bus Timing (BTS = 1/MUX = 1) ..............................
DS2155 2. DATA SHEET REVISION HISTORY REVISION 080607 040907 041806 011606 100903 DESCRIPTION In Section 3: Line Interface and Section 3.1: Functional Description, corrected dB values for E1 and T1 (page 10 and page 13): E1: 0 to -43dB and 0 to -12dB T1: 0 to -15dB and 0 to -36dB Added Note 1 (GBD for cold temp) to Absolute Maximum Ratings (Section 36). Replaced Figure 24-3 and Figure 24-4, added Table 24-A and Table 24-B. Added lead-free packages to Ordering Information table on page 1.
DS2155 REVISION DESCRIPTION The definition of the EGL bit in the LIC1 register has been corrected for both T1 and E1 mode.
DS2155 3. MAIN FEATURES The DS2155 contains all of the features of the previous generation of Dallas Semiconductor’s T1 and E1 SCTs plus many new features.
DS2155 Flexible signaling support – Software or hardware based – Interrupt generated on change of signaling data – Receive signaling freeze on loss-of-sync, carrier loss, or frame slip Addition of hardware pins to indicate carrier loss and signaling freeze Automatic RAI generation to ETS 300 011 specifications Access to Sa and Si bits Option to extend carrier loss criteria to a 1ms period as per ETS 300 233 Japanese J1 support – Ability to calculate and check CRC6 according to the Japanese standard – Abilit
DS2155 The DS2155 is compliant with the following standards: ANSI: T1.403-1995, T1.231–1993, T1.408 AT&T: TR54016, TR62411 ITU: G.703, G.704, G.706, G.736, G.775, G.823, G.932, I.431, O.151, Q.161 ITU-T: Recommendation I.432–03/93 B-ISDN User-Network Interface—Physical Layer Specification ETSI: ETS 300 011, ETS 300 166, ETS 300 233, CTR12, CTR4 Japanese: JTG.703, JTI.431, JJ-20.
DS2155 3.1 Functional Description The DS2155 is a software-selectable T1, E1, or J1 single-chip transceiver (SCT) for short-haul and longhaul applications. The DS2155 is composed of an LIU, framer, HDLC controllers, and a TDM backplane interface, and is controlled by an 8-bit parallel port configured for Intel or Motorola bus operations. The DS2155 is pin and software compatible with the DS2156. The LIU is composed of transmit and receive interfaces and a jitter attenuator.
DS2155 Reader’s Note: This data sheet assumes a particular nomenclature of the T1 operating environment. In each 125µs frame there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1. Each channel is made up of eight bits that are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last.
DS2155 3.2 Block Diagram Figure 3-1 shows a simplified block diagram featuring the major components of the DS2155. Details are shown in subsequent figures. The block diagram is divided into three functional blocks: LIU, FRAMER, and BACKPLANE INTERFACE. Figure 3-1.
DS2155 Figure 3-2. Receive and Transmit LIU RPOSI RCLKI RNEGI REMOTE LOOPBACK JITTER ATTENUATOR TRANSMIT OR RECEIVE PATH TPOSO TCLKO TNEGO TNEGI TCLKI TPOSI LIUC 16 of 238 RNEGO RCLKO RPOSO 8XCLK LOCAL LOOPBACK TRANSMIT LINE I/F TTIP JACLK 32.
DS2155 Figure 3-3.
DS2155 Figure 3-4.
DS2155 4. PIN FUNCTION DESCRIPTION 4.1 Transmit Side Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 1.544MHz (T1) or a 2.048MHz (E1) primary clock. Used to clock data through the transmit-side formatter. TCLK can be internally sourced from MCLK. This is the most flexible method and requires only a single clock signal for both T1 or E1. If internal sourcing is used, then the TCLK pin should be connected low.
DS2155 Signal Name: TLINK Signal Description: Transmit Link Data Signal Type: Input If enabled, this pin is sampled on the falling edge of TCLK for data insertion into either the FDL stream (ESF) or the Fs-bit position (D4), or the Z-bit position (ZBTSI) or any combination of the Sa-bit positions (E1). Signal Name: TSYNC Signal Description: Transmit Sync Signal Type: Input/Output A pulse at this pin establishes either frame or multiframe boundaries for the transmit side.
DS2155 Signal Description: Transmit Clock Output Signal Type: Output Buffered clock that is used to clock data through the transmit-side formatter (i.e., either TCLK or RCLKI). This pin is normally connected to TCLKI. Signal Name: TPOSI Signal Description: Transmit Positive-Data Input Signal Type: Input Sampled on the falling edge of TCLKI for data to be transmitted out onto the T1 line. Can be internally connected to TPOSO by connecting the LIUC pin high.
DS2155 Signal Name: RCHBLK Signal Description: Receive Channel Block Signal Type: Output A user-programmable output that can be forced high or low during any of the 24 T1 or 32 E1 channels. Synchronous with RCLK when the receive-side elastic store is disabled. Synchronous with RSYSCLK when the receive-side elastic store is enabled. Useful for blocking clocks to a serial UART or LAPD controller in applications where not all channels are used such as fractional service, 384kbps service, 768kbps, or ISDN–PRI.
DS2155 Signal Name: RLOS/LOTC Signal Description: Receive Loss-of-Sync/Loss-of-Transmit Clock Signal Type: Output A dual function output that is controlled by the CCR1.0 control bit. This pin can be programmed to either toggle high when the synchronizer is searching for the frame and multiframe or to toggle high if the TCLK pin has not been toggled for 5µs. Signal Name: RCL Signal Description: Receive Carrier Loss Signal Type: Output Set high when the line interface detects a carrier loss.
DS2155 Signal Name: RCLKI Signal Description: Receive Clock Input Signal Type: Input Clock used to clock data through the receive-side framer. This pin is normally connected to RCLKO. Can be internally connected to RCLKO by connecting the LIUC pin high. 4.3 Parallel Control Port Pins INT Signal Name: Signal Description: Interrupt Signal Type: Output Flags host controller during conditions and events defined in the status registers. Active-low, open-drain output.
DS2155 Signal Name: CS Signal Description: Chip Select Signal Type: Input Must be low to read or write to the device. CS is an active-low signal. Signal Name: ALE(AS)/A7 Signal Description: Address Latch Enable (Address Strobe) or A7 Signal Type: Input In nonmultiplexed bus operation (MUX = 0), serves as the upper address bit. In multiplexed bus operation (MUX = 1), serves to demultiplex the bus on a positive-going edge.
DS2155 4.5 User Output Port Pins Signal Name: UOP0 Signal Description: User Output Port 0 Signal Type: Output This output port pin can be set low or high by the CCR4.0 control bit. This pin is forced low on power-up and after any device reset. Signal Name: UOP1 Signal Description: User Output Port 1 Signal Type: Output This output port pin can be set low or high by the CCR4.1 control bit. This pin is forced low on power-up and after any device reset.
DS2155 4.6 JTAG Test Access Port Pins Signal Name: Signal Description: Signal Type: JTRST IEEE 1149.1 Test Reset Input JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to high. This action sets the device into the JTAG DEVICE ID mode. Normal device operation is restored by pulling JTRST low. JTRST is pulled high internally by a 10kΩ resistor operation. Signal Name: JTMS Signal Description: IEEE 1149.
DS2155 4.7 Line Interface Pins Signal Name: MCLK Signal Description: Signal Type: Master Clock Input Input A (50ppm) clock source is applied at this pin. This clock is used internally for both clock/data recovery and for the jitter attenuator for T1 and E1 modes. A quartz crystal of 2.048MHz can be applied across MCLK and XTALD instead of the clock source. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS2155 in T1-only operation, a 1.
DS2155 4.8 Supply Pins Signal Name: DVDD Signal Description: Digital Positive Supply Signal Type: Supply 3.3V ±5%. Should be connected to the RVDD and TVDD pins. Signal Name: RVDD Signal Description: Receive Analog Positive Supply Signal Type: Supply 3.3V ±5%. Should be connected to the DVDD and TVDD pins. Signal Name: TVDD Signal Description: Transmit Analog Positive Supply Signal Type: Supply 3.3V ±5%. Should be connected to the RVDD and DVDD pins.
DS2155 4.9 L and G Package Pinout The DS2155 is available in either a 100-pin LQFP (L) or 10mm CSBGA, 0.8mm pitch (G) package. Table 4-A.
DS2155 PIN LQFP CSBGA 51 52 53 54 55 56 57 58 59 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 82 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 K10 J9 H8 J10 G7 H9 H10 G8 G9 F9 F10 F7 F6 E10 E9 E8 D10 E7 D9 C10 D8 B10 C9 A10 B9 C8 A9 A8 A7 C6 B6 A6 D6 E6 A5 B5 C5 A4 D5 B4 A3 C4 A2 B3 SYMBOL TYPE TSYSCLK TSSYNC TCHCLK ESIBS1 MUX D0/AD0 D1/AD1 D2/AD2 D3/AD3 D4/AD4 D5/AD5 D6/AD6 D7/AD7 A0 A1 A2 A3 A4 A5 A6 ALE (AS)/A7 RD (DS) CS ESIBRD WR (R/W) RLINK RLCLK RCLK RDATA RPOSI RNEGI RCLKI RCLKO RN
DS2155 4.10 10mm CSBGA Pin Configuration Figure 4-1.
DS2155 5. PARALLEL PORT The SCT is controlled by either a nonmultiplexed (MUX = 0) or a multiplexed (MUX = 1) bus through an external microcontroller or microprocessor. The SCT can operate with either Intel or Motorola bus timing configurations. If the BTS pin is connected low, Intel timing is selected; if connected high, Motorola timing is selected. All Motorola bus signals are listed in parentheses (). See the timing diagrams in AC Electrical Characteristics in Section 37 for more details. 5.
DS2155 ADDRESS xxh R/W REGISTER NAME SYMBOL PAGE 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 R/W R/W R/W R/W W W W W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt Mask Register 8 Status Register 9 Interrupt Mask Register 9 Per-Channel Pointer Register Per-Channel Data Register 1 Per-Channel Data Register 2 P
DS2155 ADDRESS xxh R/W REGISTER NAME SYMBOL PAGE 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R R R R/W R/W R/W R/W R/W R R/W R R/W R/W R/W R/W — R/W W R/W R/W R/W R/W Transmit Signaling Register 5 Transmit Signaling Register 6 Transmit Signaling Register 7 Transmit Signaling Register 8 Transmit Signaling Register 9 Transmit Signali
DS2155 ADDRESS xxh R/W 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W R R R/W R/W REGISTER NAME Transmit Idle Code Enable Register 4 Receive Idle Code Enable Register 1 Receive Idle Code Enable Register 2 Receive Idle Code Enable Register 3 Receive Idle
DS2155 ADDRESS xxh R/W B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W — R/W R R R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W REGISTER NAME Extend System Information Bus Register 1 Extend System Information Bus Register 2 Extend System Information Bus Register 3 Extend System Information Bus Register 4 In-Band C
DS2155 ADDRESS xxh R/W E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0* F1–F9* FA–FF* R/W — R R R R R R R R/W R/W R/W R/W R R — — — REGISTER NAME BERT Control Register 2 Unused BERT Bit Count Register 1 BERT Bit Count Register 2 BERT Bit Count Register 3 BERT Bit Count Register 4 BERT Error Count Register 1 BERT Error Count Register 2 BERT Error Count Register 3 BERT Interface Control Register Error Rate Control Register Number-of-Errors 1 Number-of-Errors 2 Number-of-Errors Left 1 Number-of-Errors Lef
DS2155 6. PROGRAMMING MODEL The DS2155 register map is divided into three groups: T1 specific features, E1 specific features, and common features. The typical programming sequence begins with issuing a reset to the DS2155, selecting T1 or E1 operation in the master mode register, enabling T1 or E1 functions and enabling the common functions. The act of resetting the DS2155 automatically clears all configuration and status registers. Therefore, it is not necessary to load unused registers with 0s.
DS2155 6.1 Power-Up Sequence The DS2155 contains an on-chip power-up reset function that automatically clears the writeable register space immediately after power is supplied to the DS2155. The user can issue a chip reset at any time. Issuing a reset disrupts traffic flowing through the DS2155 until the device is reprogrammed. The reset can be issued through hardware using the TSTRST pin or through software using the SFTRST function in the master mode register. The LIRST (LIC2.
DS2155 6.2 Interrupt Handling Various alarms, conditions, and events in the DS2155 can cause interrupts. For simplicity, these are all referred to as events in this explanation. All status registers can be programmed to produce interrupts. Each status register has an associated interrupt mask register. For example, SR1 (status register 1) has an interrupt control register called IMR1 (interrupt mask register 1). Status registers are the only sources of interrupts in the DS2155.
DS2155 6.4 Information Registers Information registers operate the same as status registers except they cannot cause interrupts. They are all latched except for INFO7 and some of the bits in INFO5 and INFO6. INFO7 register is a read-only register. It reports the status of the E1 synchronizer in real time. INFO7 and some of the bits in INFO6 and INFO5 are not latched and it is not necessary to precede a read of these bits with a write. 6.
DS2155 7. SPECIAL PER-CHANNEL REGISTER OPERATION Some of the features described in the data sheet that operate on a per-channel basis use a special method for channel selection. There are five registers involved: per-channel pointer register (PCPR) and perchannel data registers 1–4 (PCDR1–4). The user selects which function or functions are to be applied on a per-channel basis by setting the appropriate bit(s) in the PCPR register.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 — CH8 Register Name: Register Description: Register Address: Bit # Name Default 7 — CH16 Register Name: Register Description: Register Address: Bit # Name Default 7 — CH24 Register Name: Register Description: Register Address: Bit # Name Default 7 — CH32 PCDR1 Per-Channel Data Register 1 29h 6 — CH7 5 — CH6 4 — CH5 3 — CH4 2 — CH3 1 — CH2 0 — CH1 3 — CH12 2 — CH11 1 — CH10 0 — CH9 3 — CH20 2 — CH19 1 — CH
DS2155 8. CLOCK MAP Figure 8-1 shows the clock map of the DS2155. The routing for the transmit and receive clocks are shown for the various loopback modes and jitter attenuator positions. Although there is only one jitter attenuator, which can be placed in the receive or transmit path, two are shown for simplification and clarity. Figure 8-1. Clock Map MCLK TSYSCLK MCLKS = 0 MCLKS = 1 PRE-SCALER LIC4.MPS0 LIC4.MPS1 2.048 TO 1.544 SYNTHESIZER LIC2.
DS2155 9. T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS The T1 framer portion of the DS2155 is configured through a set of nine control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2155 has been initialized, the control registers only need to be accessed when there is a change in the system configuration.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 T1RCR2 T1 Receive Control Register 2 04h 6 RFM 0 5 RB8ZS 0 4 RSLC96 0 3 RZSE 0 2 RZBTSI 0 1 RJC 0 0 RD4YM 0 Bit 0/Receive-Side D4 Yellow Alarm Select (RD4YM) 0 = 0s in bit 2 of all channels 1 = a 1 in the S-bit position of frame 12 (J1 Yellow Alarm Mode) Bit 1/Receive Japanese CRC6 Enable (RJC) 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation) 1 = use Japanese standard JT–G704 CRC6 calculation Bit 2/Recei
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 TJC 0 T1TCR1 T1 Transmit Control Register 1 05h 6 TFPT 0 5 TCPT 0 4 TSSE 0 3 GB7S 0 2 TFDLS 0 1 TBL 0 0 TYEL 0 Bit 0/Transmit Yellow Alarm (TYEL) 0 = do not transmit yellow alarm 1 = transmit yellow alarm Bit 1/Transmit Blue Alarm (TBL) 0 = transmit data normally 1 = transmit an unframed all-ones code at TPOS and TNEG Bit 2/TFDL Register Select (TFDLS) 0 = source FDL or Fs-bits from the internal TFDL register (legac
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 TB8ZS 0 T1TCR2 T1 Transmit Control Register 2 06h 6 TSLC96 0 5 TZSE 0 4 FBCT2 0 3 FBCT1 0 2 TD4YM 0 1 TZBTSI 0 0 TB7ZS 0 Bit 0/Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS) 0 = no stuffing occurs 1 = bit 7 forced to a 1 in channels with all 0s Bit 1/Transmit-Side ZBTSI Support Enable (TZBTSI). Allows ZBTSI information to be input on TLINK pin.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 T1CCR1 T1 Common Control Register 1 07h 6 — 0 5 — 0 4 TRAI-CI 0 3 TAIS-CI 0 2 TFM 0 1 PDE 0 0 TLOOP 0 Bit 0/Transmit Loop-Code Enable (TLOOP). See Section 25 for details. 0 = transmit data normally 1 = replace normal transmitted data with repeating code as defined in registers TCD1 and TCD2 Bit 1/Pulse Density Enforcer Enable (PDE).
DS2155 9.2 T1 Transmit Transparency The software signaling insertion-enable registers, SSIE1–SSIE4, can be used to select signaling insertion from the transmit signaling registers, TS1–TS12, on a per-channel basis. Setting a bit in the SSIEx register allows signaling data to be sourced from the signaling registers for that channel. In transparent mode, bit 7 stuffing and/or robbed-bit signaling is prevented from overwriting the data in the channels.
DS2155 9.4 T1 Receive-Side Digital-Milliwatt Code Generation Receive-side digital-milliwatt code generation involves using the receive digital-milliwatt registers (T1RDMR1/2/3) to determine which of the 24 T1 channels of the T1 line going to the backplane should be overwritten with a digital-milliwatt pattern. The digital-milliwatt code is an 8-byte repeating pattern that represents a 1kHz sine wave (1E/0B/0B/1E/9E/8B/8B/9E). Each bit in the T1RDMRx registers represents a particular channel.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 RPDV 0 INFO1 Information Register 1 10h 6 TPDV 0 5 COFA 0 4 8ZD 0 3 16ZD 0 2 SEFE 0 1 B8ZS 0 0 FBE 0 Bit 0/Frame Bit-Error Event (FBE). Set when an Ft (D4) or FPS (ESF) framing bit is received in error. Bit 1/B8ZS Codeword Detect Event (B8ZS). Set when a B8ZS codeword is detected at RPOS and RNEG independent of whether the B8ZS mode is selected or not by T1TCR2.7. Useful for automatically setting the line coding.
DS2155 Table 9-A. T1 Alarm Criteria ALARM Blue Alarm (AIS) (Note 1) Yellow Alarm (RAI) D4 Bit 2 Mode (T1RCR2.0 = 0) SET CRITERIA When over a 3ms window, five or fewer 0s are received When bit 2 of 256 consecutive channels is set to 0 for at least 254 occurrences CLEAR CRITERIA When over a 3ms window, six or more 0s are received When bit 2 of 256 consecutive channels is set to 0 for fewer than 254 occurrences D4 12th F-Bit Mode (T1RCR2.
DS2155 10. E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS The E1 framer portion of the DS2155 is configured by a set of four control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2155 has been initialized, the control registers need only to be accessed when there is a change in the system configuration. There are two receive control registers (E1RCR1 and E1RCR2) and two transmit control registers (E1TCR1 and E1TCR2).
DS2155 Table 10-A. E1 Sync/Resync Criteria FRAME OR MULTIFRAME LEVEL SYNC CRITERIA RESYNC CRITERIA ITU SPEC. Three consecutive incorrect FAS received FAS present in frame N and N + 2; FAS not present in frame N + 1 FAS Two valid MF alignment words found within 8ms Valid MF alignment word found and previous time slot 16 contains code other than all 0s CRC4 CAS Register Name: Register Description: Register Address: Bit # Name Default 7 Sa8S 0 Alternate: (E1RCR1.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 TFPT 0 E1TCR1 E1 Transmit Control Register 1 35h 6 T16S 0 5 TUA1 0 4 TSiS 0 3 TSA1 0 2 THDB3 0 1 TG802 0 0 TCRC4 0 Bit 0/Transmit CRC4 Enable (TCRC4) 0 = CRC4 disabled 1 = CRC4 enabled Bit 1/Transmit G.802 Enable (TG802). See Section 35 for details.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 Sa8S 0 E1TCR2 E1 Transmit Control Register 2 36h 6 Sa7S 0 5 Sa6S 0 4 Sa5S 0 3 Sa4S 0 2 AEBE 0 1 AAIS 0 0 ARA 0 Bit 0/Automatic Remote Alarm Generation (ARA) 0 = disabled 1 = enabled Bit 1/Automatic AIS Generation (AAIS) 0 = disabled 1 = enabled Bit 2/Automatic E-Bit Enable (AEBE) 0 = E-bits not automatically set in the transmit direction 1 = E-bits automatically set in the transmit direction Bit 3/Sa4 Bit Select (Sa
DS2155 10.2 Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is enabled (E1TCR2.1 = 1), the device monitors the receive-side framer to determine if any of the following conditions are present: loss-of-receive frame synchronization, AIS alarm (all ones) reception, or loss-of-receive carrier (or signal). The framer forces either an AIS or remote alarm if any one or more of these conditions is present.
DS2155 10.3 E1 Information Registers Register Name: Register Description: Register Address: INFO3 Information Register 3 12h Bit # Name Default 6 — 0 7 — 0 5 — 0 4 — 0 3 — 0 2 CRCRC 0 1 FASRC 0 0 CASRC 0 Bit 0/CAS Resync Criteria Met Event (CASRC). Set when two consecutive CAS MF alignment words are received in error. Bit 1/FAS Resync Criteria Met Event (FASRC). Set when three consecutive FAS words are received in error.
DS2155 Table 10-B. E1 Alarm Criteria ALARM RLOS RCL RRA RUA1 RDMA V52LNK SET CRITERIA CLEAR CRITERIA An RLOS condition exists on power-up prior to initial synchronization, when a resync criteria has been met, or when a manual resync has been initiated by E1RCR1.0 255 or 2048 consecutive 0s received as determined by E1RCR2.
DS2155 11.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 ID7 1 IDR Device Identification Register 0Fh 6 ID6 0 5 ID5 1 4 ID4 1 3 ID3 X 2 ID2 X 1 ID1 X 0 ID0 X Bits 0 to 3/Chip Revision Bits (ID0 to ID3). The lower four bits of the IDR are used to display the die revision of the chip. IDO is the LSB of a decimal code that represents the chip revision. Bits 4 to 7/Device ID (ID4 to ID7). The upper four bits of the IDR are used to display the DS2155 ID. 11.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 RYELC 0 IMR2 Interrupt Mask Register 2 19h 6 RUA1C 0 5 FRCLC 0 4 RLOSC 0 3 RYEL 0 2 RUA1 0 Bit 0/Receive Loss-of-Sync Condition (RLOS) 0 = interrupt masked 1 = interrupt enabled—interrupts on rising edge only Bit 1/Framer Receive Carrier Loss Condition (FRCL) 0 = interrupt masked 1 = interrupt enabled—interrupts on rising edge only Bit 2/Receive Unframed All-Ones (Blue Alarm) Condition (RUA1) 0 = interrupt masked 1 = i
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 LSPARE 0 SR3 Status Register 3 1Ah 6 LDN 0 5 LUP 0 4 LOTC 0 3 LORC 0 2 V52LNK 0 1 RDMA 0 0 RRA 0 Bit 0/Receive Remote Alarm Condition (RRA) (E1 Only). Set when a remote alarm is received at RPOSI and RNEGI. This is a double interrupt bit. See Section 6.3. Bit 1/Receive Distant MF Alarm Condition (RDMA) (E1 Only). Set when bit 6 of time slot 16 in frame 0 has been set for two consecutive multiframes.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 LSPARE 0 IMR3 Interrupt Mask Register 3 1Bh 6 LDN 0 5 LUP 0 4 LOTC 0 3 LORC 0 2 V52LNK 0 Bit 0/Receive Remote Alarm Condition (RRA) 0 = interrupt masked 1 = interrupt enabled—interrupts on rising and falling edges Bit 1/Receive Distant MF Alarm Condition (RDMA) 0 = interrupt masked 1 = interrupt enabled—interrupts on rising and falling edges Bit 2/V5.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 RAIS-CI 0 SR4 Status Register 4 1Ch 6 RSAO 0 5 RSAZ 0 4 TMF 0 3 TAF 0 2 RMF 0 1 RCMF 0 0 RAF 0 Bit 0/Receive Align Frame Event (RAF) (E1 Only). Set every 250µs at the beginning of align frames. Used to alert the host that Si and Sa bits are available in the RAF and RNAF registers. Bit 1/Receive CRC4 Multiframe Event (RCMF) (E1 Only).
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 RAIS-CI 0 IMR4 Interrupt Mask Register 4 1Dh 6 RSAO 0 5 RSAZ 0 4 TMF 0 3 TAF 0 Bit 0/Receive Align Frame Event (RAF) 0 = interrupt masked 1 = interrupt enabled Bit 1/Receive CRC4 Multiframe Event (RCMF) 0 = interrupt masked 1 = interrupt enabled Bit 2/Receive Multiframe Event (RMF) 0 = interrupt masked 1 = interrupt enabled Bit 3/Transmit Align Frame Event (TAF) 0 = interrupt masked 1 = interrupt enabled Bit 4/Transmit
DS2155 12. I/O PIN CONFIGURATION OPTIONS Register Name: Register Description: Register Address: Bit # Name Default 7 RSMS 0 IOCR1 I/O Configuration Register 1 01h 6 RSMS2 0 5 RSMS1 0 4 RSIO 0 3 TSDW 0 2 TSM 0 1 TSIO 0 0 ODF 0 Bit 0/Output Data Format (ODF) 0 = bipolar data at TPOSO and TNEGO 1 = NRZ data at TPOSO; TNEGO = 0 Bit 1/TSYNC I/O Select (TSIO) 0 = TSYNC is an input 1 = TSYNC is an output Bit 2/TSYNC Mode Select (TSM). Selects frame or multiframe mode for the TSYNC pin.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 RCLKINV 0 IOCR2 I/O Configuration Register 2 02h 6 TCLKINV 0 5 RSYNCINV 0 4 TSYNCINV 0 3 TSSYNCINV 0 2 H100EN 0 1 TSCLKM 0 Bit 0/RSYSCLK Mode Select (RSCLKM) 0 = if RSYSCLK is 1.544MHz 1 = if RSYSCLK is 2.048MHz or IBO enabled (See Section 28 for details on IBO function.) Bit 1/TSYSCLK Mode Select (TSCLKM) 0 = if TSYSCLK is 1.544MHz 1 = if TSYSCLK is 2.
DS2155 13. LOOPBACK CONFIGURATION Register Name: Register Description: Register Address: LBCR Loopback Control Register 4Ah Bit # Name Default 6 — 0 7 — 0 5 — 0 4 LIUC 0 3 LLB 0 2 RLB 0 1 PLB 0 0 FLB 0 Bit 0/Framer Loopback (FLB). This loopback is useful in testing and debugging applications. In FLB, the DS2155 loops data from the transmit side back to the receive side. When FLB is enabled, the following occurs: 1) T1 Mode: An unframed all-ones code is transmitted at TPOSO and TNEGO.
DS2155 Bit 3/Local Loopback (LLB). In this loopback, data continues to be transmitted as normal through the transmit side of the SCT. Data being received at RTIP and RRING are replaced with the data being transmitted. Data in this loopback passes through the jitter attenuator. See Figure 3-2 for more details. 0 = loopback disabled 1 = loopback enabled Bit 4/Line Interface Unit Mux Control (LIUC). This is a software version of the LIUC pin. When the LIUC pin is connected high, the LIUC bit has control.
DS2155 13.1 Per-Channel Loopback The per-channel loopback registers (PCLRs) determine which channels (if any) from the backplane should be replaced with the data from the receive side or, i.e., off of the T1 or E1 line. If this loopback is enabled, then transmit and receive clocks and frame syncs must be synchronized. One method to accomplish this is to connect RCLK to TCLK and RFSYNC to TSYNC. There are no restrictions on which channels can be looped back or on how many channels can be looped back.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 PCLR3 Per-Channel Loopback Enable Register 3 4Dh 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0 Bits 0 to 7/Per-Channel Loopback Enable for Channels 17 to 24 (CH17 to CH24) 0 = loopback disabled 1 = enable loopback; source data from the corresponding receive channel Register Name: Register Description: Register Address: Bit # Name Default 7 CH32 0 PCLR4 Per-Channel Loopback Enable Register 4
DS2155 14. ERROR COUNT REGISTERS The DS2155 contains four counters that are used to accumulate line-coding errors, path errors, and synchronization errors. Counter update options include one-second boundaries, 42ms (T1 mode only), 62ms (E1 mode only), or manual. See Error-Counter Configuration Register (ERCNT). When updated automatically, the user can use the interrupt from the timer to determine when to read these registers.
DS2155 14.1 Line-Code Violation Count Register (LCVCR) 14.1.1 T1 Operation T1 code violations are defined as bipolar violations (BPVs) or excessive 0s. If the B8ZS mode is set for the receive side, then B8ZS codewords are not counted. This counter is always enabled; it is not disabled during receive loss-of-synchronization (RLOS = 1) conditions. Table 14-A shows what the LCVCRs count. Table 14-A. T1 Line Code Violation Counting Options COUNT EXCESSIVE ZEROS? (ERCNT.0) No Yes No Yes B8ZS ENABLED? (T1RCR2.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 LCVC15 0 LCVCR1 Line-Code Violation Count Register 1 42h 6 LCVC14 0 5 LCVC13 0 4 LCVC12 0 3 LCVC11 0 2 LCVC10 0 1 LCVC9 0 0 LCCV8 0 Bits 0 to 7/Line-Code Violation Counter Bits 8 to 15 (LCVC8 to LCVC15). LCV15 is the MSB of the 16-bit code violation count.
DS2155 14.2 Path Code Violation Count Register (PCVCR) 14.2.1 T1 Operation The path code violation count register records Ft, Fs, or CRC6 errors in T1 frames. When the receive side of a framer is set to operate in the T1 ESF framing mode, PCVCR records errors in the CRC6 codewords. When set to operate in the T1 D4 framing mode, PCVCR counts errors in the Ft framing bit position. Through the ERCNT.2 bit, a framer can be programmed to also report errors in the Fs framing bit position.
DS2155 14.3 Frames Out-of-Sync Count Register (FOSCR) 14.3.1 T1 Operation The FOSCR is used to count the number of multiframes that the receive synchronizer is out of sync. This number is useful in ESF applications needing to measure the parameters loss-of-frame count (LOFC) and ESF error events as described in AT&T publication TR54016. When the FOSCR is operated in this mode, it is not disabled during receive loss-of-synchronization (RLOS = 1) conditions.
DS2155 14.4 E-Bit Counter (EBCR) This counter is only available in E1 mode. E-bit count register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 16-bit counter that records far-end block errors (FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running with CRC4 multiframe. These count registers increment once each time the received E-bit is set to 0. Since the maximum E-bit count in a onesecond period is 1000, this counter cannot saturate.
DS2155 15. DS0 MONITORING FUNCTION The DS2155 has the ability to monitor one DS0 64kbps channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the TDS0SEL register. In the receive direction, the RCM0 to RCM4 bits in the RDS0SEL register need to be properly set.
DS2155 Register Name: Register Description: Register Address: RDS0SEL Receive Channel Monitor Select 76h Bit # Name Default 6 — 0 7 — 0 5 — 0 4 RCM4 0 3 RCM3 0 2 RCM2 0 1 RCM1 0 0 RCM0 0 Bits 0 to 4/Receive Channel Monitor Bits (RCM0 to RCM4). RCM0 is the LSB of a 5-bit channel select that determines which receive DS0 channel data appear in the RDS0M register.
DS2155 16. SIGNALING OPERATION There are two methods to access receive signaling data and provide transmit signaling data, processorbased (software-based) or hardware-based. Processor-based refers to access through the transmit and receive signaling registers RS1–RS16 and TS1–TS16. Hardware-based refers to the TSIG and RSIG pins. Both methods can be used simultaneously. 16.1 Receive Signaling Figure 16-1.
DS2155 16.1.2 Hardware-Based Receive Signaling In hardware-based signaling the signaling data can be obtained from the RSER pin or the RSIG pin. RSIG is a signaling PCM stream output on a channel-by-channel basis from the signaling buffer. The signaling data, T1 robbed bit or E1 TS16, is still present in the original data stream at RSER.
DS2155 Register Name: Register Description: Register Address: SIGCR Signaling Control Register 40h Bit # Name Default 6 — 0 7 GRSRE 0 5 — 0 4 RFE 0 3 RFF 0 2 RCCS 0 1 TCCS 0 0 FRSAO 0 Bit 0/Force Receive Signaling All Ones (FRSAO). In T1 mode, this bit forces all signaling data at the RSIG and RSER pin to all ones. This bit has no effect in E1 mode.
DS2155 Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B RS1 to RS12 Receive Signaling Registers (T1 Mode, ESF Forma
DS2155 Register Name: Register Description: Register Address: (MSB) 0 CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH26-A CH28-A CH30-A 0 CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B CH26-B CH28-B CH30-B Register Name: Register Description: Register Address: (MSB) 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121 2 10 18 26 34 42 50 58 66 74 82 90 98 106 114 122 RS1 to RS16 Receive Signaling Registers (E1 Mode, CAS Format) 60h to 6Fh
DS2155 Register Name: Register Description: Register Address: (MSB) CH8 CH16 CH24 CH7 CH15 CH23 RSCSE1, RSCSE2, RSCSE3, RSCSE4 Receive Signaling Change-of-State Interrupt Enable 3Ch, 3Dh, 3Eh, 3Fh CH6 CH14 CH22 CH30 CH5 CH13 CH21 CH29 CH4 CH12 CH20 CH28 CH3 CH11 CH19 CH27 CH2 CH10 CH18 CH26 (LSB) CH1 CH9 CH17 CH25 RSCSE1 RSCSE2 RSCSE3 RSCSE4 Setting any of the CH1–CH30 bits in the RSCSE1–RSCSE4 registers causes an interrupt when that channel’s signaling data changes state.
DS2155 16.2 Transmit Signaling Figure 16-2. Simplified Diagram of Transmit Signaling Path TRANSMIT SIGNALING REGISTERS 1 0 0 T1/E1 DATA STREAM TSER 0 1 1 B7 SIGNALING BUFFERS TSIG T1TCR1.4 PER-CHANNEL CONTROL PER-CHANNEL CONTROL PCPR.3 SSIE1 - SSIE4 ONLY APPLIES TO T1 MODE 16.2.1 Processor-Based Mode In processor-based mode, signaling data is loaded into the transmit signaling registers (TS1–TS16) by the host interface.
DS2155 16.2.1.2 E1 Mode In E1 mode, TS16 carries the signaling information. This information can be in either CCS (common channel signaling) or CAS (channel associated signaling) format. The 32 time slots are referenced by two different channel number schemes in E1. In “Channel” numbering, TS0–TS31 are labeled channels 1 through 32. In “Phone Channel” numbering, TS1–TS15 are labeled channel 1 through channel 15 and TS17–TS31 are labeled channel 15 through channel 30. Table 16-A.
DS2155 Register Name: Register Description: Register Address: (MSB) 0 CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH26-A CH28-A CH30-A 0 CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B CH26-B CH28-B CH30-B Register Name: Register Description: Register Address: (MSB) 1 9 17 25 33 41 49 57 65 73 81 89 97 105 113 121 2 10 18 26 34 42 50 58 66 74 82 90 98 106 114 122 TS1 to TS16 Transmit Signaling Registers (E1 Mode, CAS Format) 50h to 5Fh
DS2155 Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B Register Name: Register Description: Register Address: (MSB) CH2-A CH4-A CH6-A CH8-A CH10-A CH12-A CH14-A CH16-A CH18-A CH20-A CH22-A CH24-A CH2-B CH4-B CH6-B CH8-B CH10-B CH12-B CH14-B CH16-B CH18-B CH20-B CH22-B CH24-B TS1 to TS12 Transmit Signaling Registers (T1 Mode, ESF For
DS2155 16.2.2 Software Signaling Insertion-Enable Registers, E1 CAS Mode In E1 CAS mode, the CAS signaling alignment/alarm byte can be sourced from the transmit signaling registers along with the signaling data. Register Name: Register Description: Register Address: Bit # Name Default 7 CH7 0 SSIE1 Software Signaling Insertion Enable 1 08h 6 CH6 0 5 CH5 0 4 CH4 0 3 CH3 0 2 CH2 0 1 CH1 0 0 UCAW 0 Bit 0/Upper CAS Align/Alarm Word (UCAW).
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 CH22 0 SSIE3 Software Signaling Insertion Enable 3 0Ah 6 CH21 0 5 CH20 0 4 CH19 0 3 CH18 0 2 CH17 0 1 CH16 0 0 LCAW 0 Bit 0/Lower CAS Align/Alarm Word (LCAW). Selects the lower CAS align/alarm bits (xyxx) to be sourced from the lower 4 bits of the TS1 register.
DS2155 16.2.3 Software Signaling Insertion-Enable Registers, T1 Mode In T1 mode, only registers SSIE1–SSIE3 are used since there are only 24 channels in a T1 frame. Register Name: Register Description: Register Address: Bit # Name Default 7 CH8 0 SSIE1 Software Signaling Insertion Enable 1 08h 6 CH7 0 5 CH6 0 4 CH5 0 3 CH4 0 2 CH3 0 1 CH2 0 0 CH1 0 Bits 0 to 7/Software Signaling Insertion Enable for Channels 1 to 8 (CH1 to CH8).
DS2155 17. PER-CHANNEL IDLE CODE GENERATION Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. When operated in the T1 mode, only the first 24 channels are used by the DS2155, the remaining channels, CH25–CH32, are not used. The DS2155 contains a 64-byte idle code array accessed by the idle array address register (IAAR) and the per-channel idle code register (PCICR).
DS2155 17.1 Idle-Code Programming Examples Example 1 Sets transmit channel 3 idle code to 7Eh. Write IAAR = 02h ;select channel 3 in the array Write PCICR = 7Eh ;set idle code to 7Eh Example 2 Sets transmit channels 3, 4, 5, and 6 idle code to 7Eh and enables transmission of idle codes for those channels.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 GRIC 0 IAAR Idle Array Address Register 7Eh 6 GTIC 0 5 IAA5 0 4 IAA4 0 3 IAA3 0 2 IAA2 0 1 IAA1 0 0 IAA0 0 Bits 0 to 5/Channel Pointer Address Bits (IAA0 to IAA5). These bits select the channel to be programmed with the idle code defined in the PCICR register. IAA0 is the LSB of the 5-bit channel code. Channel 1 is 01h. Bit 6/Global Transmit-Idle Code (GTIC).
DS2155 The transmit-channel idle-code enable registers (TCICE1/2/3/4) are used to determine which of the 24 T1 or 32 E1 channels from the backplane to the T1 or E1 line should be overwritten with the code placed in the per-channel code array.
DS2155 The receive-channel idle-code enable registers (RCICE1/2/3/4) are used to determine which of the 24 T1 or 32 E1 channels from the backplane to the T1 or E1 line should be overwritten with the code placed in the per-channel code array.
DS2155 18. CHANNEL BLOCKING REGISTERS The receive channel blocking registers (RCBR1/RCBR2/RCBR3/RCBR4) and the transmit channel blocking registers (TCBR1/TCBR2/TCBR3/TCBR4) control RCHBLK and TCHBLK pins, respectively. The RCHBLK and TCHBLK pins are user-programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI applications.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 CH24 0 RCBR3 Receive Channel Blocking Register 3 8Ah 6 CH23 0 5 CH22 0 4 CH21 0 3 CH20 0 2 CH19 0 1 CH18 0 0 CH17 0 Bits 0 to 7/Receive Channels 17 to 24 Channel Blocking Control Bits (CH17 to CH24) 0 = force the RCHBLK pin to remain low during this channel time 1 = force the RCHBLK pin high during this channel time Register Name: Register Description: Register Address: Bit # Name Default 7 CH32 0 RCBR4 Receive Cha
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 CH8 0 TCBR1 Transmit Channel Blocking Register 1 8Ch 6 CH7 0 5 CH6 0 4 CH5 0 3 CH4 0 2 CH3 0 1 CH2 0 0 CH1 0 Bits 0 to 7/Transmit Channels 1 to 8 Channel Blocking Control Bits (CH1 to CH8) 0 = force the TCHBLK pin to remain low during this channel time 1 = force the TCHBLK pin high during this channel time Register Name: Register Description: Register Address: Bit # Name Default 7 CH16 0 TCBR2 Transmit Channel Bloc
DS2155 19. ELASTIC STORES OPERATION The DS2155 contains dual two-frame elastic stores, one for the receive direction and one for the transmit direction. Both elastic stores are fully independent. The transmit and receive-side elastic stores can be enabled/disabled independently of each other. Also, each elastic store can interface to either a 1.544MHz or 2.048MHz/4.096MHz/8.192MHz/16.384MHz backplane without regard to the backplane rate the other elastic store is interfacing to.
DS2155 Register Name: Register Description: Register Address: ESCR Elastic Store Control Register 4Fh Bit # Name Default 6 TESR 0 7 TESALGN 0 5 TESMDM 0 4 TESE 0 3 RESALGN 0 2 RESR 0 1 RESMDM 0 0 RESE 0 Bit 0/Receive Elastic Store Enable (RESE) 0 = elastic store is bypassed 1 = elastic store is enabled Bit 1/Receive Elastic Store Minimum-Delay Mode (RESMDM). See Section 19.4 for details.
DS2155 Register Name: Register Description: Register Address: SR5 Status Register 5 1Eh Bit # Name Default 6 — 0 7 — 0 5 TESF 0 4 TESEM 0 3 TSLIP 0 2 RESF 0 1 RESEM 0 0 RSLIP 0 Bit 0/Receive Elastic Store Slip-Occurrence Event (RSLIP). Set when the receive elastic store has either repeated or deleted a frame. Bit 1/Receive Elastic Store Empty Event (RESEM). Set when the receive elastic store buffer empties and a frame is repeated. Bit 2/Receive Elastic Store Full Event (RESF).
DS2155 19.1 Receive Side See the IOCR1 and IOCR2 registers for information about clock and I/O configurations. If the receive-side elastic store is enabled, then the user must provide either a 1.544MHz or 2.048MHz clock at the RSYSCLK pin. For higher rate system clock applications, see the Interleaved PCM Bus Operation in Section 28. The user has the option of either providing a frame/multiframe sync at the RSYNC pin or having the RSYNC pin provide a pulse on frame/multiframe boundaries.
DS2155 19.2.1 T1 Mode If the user selects to apply a 2.048MHz clock to the TSYSCLK pin, then the data input at TSER is ignored every fourth channel. Therefore channels 1, 5, 9, 13, 17, 21, 25, and 29 (time slots 0, 4, 8, 12, 16, 20, 24, and 28) are ignored. The user can supply frame or multiframe sync pulse to the TSSYNC input. Also, in 2.048MHz applications, the TCHBLK output is forced high during the channels ignored by the framer. 19.2.2 E1 Mode A 1.544MHz or 2.
DS2155 20. G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY) The DS2155 can implement the G.706 CRC-4 recalculation at intermediate path points. When this mode is enabled, the data stream presented at TSER already has the FAS/NFAS, CRC multiframe alignment word, and CRC-4 checksum in time slot 0. The user can modify the Sa bit positions. This change in data content is used to modify the CRC-4 checksum.
DS2155 21. T1 BIT-ORIENTED CODE (BOC) CONTROLLER The DS2155 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. 21.1 Transmit BOC Bits 0 to 5 in the TFDL register contain the BOC message to be transmitted. Setting BOCC.0 = 1 causes the transmit BOC controller to immediately begin inserting the BOC sequence into the FDL bit position. The transmit BOC controller automatically provides the abort sequence.
DS2155 Register Name: Register Description: Register Address: BOCC BOC Control Register 37h Bit # Name Default 6 — 0 7 — 0 5 — 0 4 RBOCE 0 3 RBR 0 2 RBF1 0 1 RBF0 0 0 SBOC 0 Bit 0/Send BOC (SBOC). Set = 1 to transmit the BOC code placed in bits 0 to 5 of the TFDL register. Bits 1 and 2/Receive BOC Filter Bits (RBF0, RBF1). The BOC filter sets the number of consecutive patterns that must be received without error prior to an indication of a valid message.
DS2155 Register Name: Register Description: Register Address: SR8 Status Register 8 24h Bit # Name Default 6 — 0 7 — 0 5 BOCC 0 4 RFDLAD 0 3 RFDLF 0 2 TFDLE 0 1 RMTCH 0 0 RBOC 0 Bit 0/Receive BOC Detector Change-of-State Event (RBOC). Set whenever the BOC detector sees a change of state to a valid BOC. The setting of this bit prompts the user to read the RFDL register. Bit 1/Receive FDL Match Event (RMTCH). Set whenever the contents of the RFDL register matches RFDLM1 or RFDLM2.
DS2155 22. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY) When operated in the E1 mode, the DS2155 provides three methods for accessing the Sa and the Si bits. The first method involves a hardware scheme that uses the RLINK/RLCLK and TLINK/TLCLK pins (Section 22.1). The second method involves using the internal RAF/RNAF and TAF/TNAF registers (Section 22.2). The third method, which is covered in Section 22.3, involves an expanded version of the second method. 22.
DS2155 Register Name: Register Description: Register Address: RAF Receive Align Frame Register C6h Bit # Name Default 6 0 0 7 Si 0 5 0 0 4 1 0 3 1 0 2 0 0 1 1 0 0 1 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 Bit 0/Frame Alignment Signal Bit (1) Bit 1/Frame Alignment Signal Bit (1) Bit 2/Frame Alignment Signal Bit (0) Bit 3/Frame Alignment Signal Bit (1) Bit 4/Frame Alignment Signal Bit (1) Bit 5/Frame Alignment Signal Bit (0) Bit 6/Frame Alignment Signal Bit (0) Bit 7/International Bit (Si) Register Name: Reg
DS2155 Register Name: Register Description: Register Address: TAF Transmit Align Frame Register D0h Bit # Name Default 6 0 0 7 Si 0 5 0 0 4 1 1 3 1 1 2 0 0 1 1 1 0 1 1 2 Sa6 0 1 Sa7 0 0 Sa8 0 Bit 0/Frame Alignment Signal Bit (1) Bit 1/Frame Alignment Signal Bit (1) Bit 2/Frame Alignment Signal Bit (0) Bit 3/Frame Alignment Signal Bit (1) Bit 4/Frame Alignment Signal Bit (1) Bit 5/Frame Alignment Signal Bit (0) Bit 6/Frame Alignment Signal Bit (0) Bit 7/International Bit (Si) Register Name: Re
DS2155 22.3 Method 3: Internal Register Scheme Based on CRC4 Multiframe The receive side contains a set of eight registers (RSiAF, RSiNAF, RRA, and RSa4–RSa8) that report the Si and Sa bits as they are received. These registers are updated with the setting of the receive CRC4 multiframe bit in Status Register 2 (SR4.1). The host can use the SR4.1 bit to know when to read these registers. The user has 2ms to retrieve the data before it is lost. The MSB of each register is the first received.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 SiF1 0 RSiNAF Received Si Bits of the Nonalign Frame C9h 6 SiF3 0 5 SiF5 0 4 SiF7 0 3 SiF9 0 2 SiF11 0 3 RRAF9 0 2 RRAF11 0 1 SiF13 0 0 SiF15 0 Bit 0/Si Bit of Frame 15 (SiF15) Bit 1/Si Bit of Frame 13 (SiF13) Bit 2/Si Bit of Frame 11 (SiF11) Bit 3/Si Bit of Frame 9 (SiF9) Bit 4/Si Bit of Frame 7 (SiF7) Bit 5/Si Bit of Frame 5 (SiF5) Bit 6/Si Bit of Frame 3 (SiF3) Bit 7/Si Bit of Frame 1 (SiF1) Register Name: Regis
DS2155 Register Name: Register Description: Register Address: RSa4 Received Sa4 Bits CBh Bit # Name Default 6 RSa4F3 0 7 RSa4F1 0 5 RSa4F5 0 4 RSa4F7 0 3 RSa4F9 0 2 RSa4F11 0 4 RSa5F7 0 3 RSa5F9 0 2 RSa5F11 0 1 RSa4F13 0 0 RSa4F15 0 Bit 0/Sa4 Bit of Frame 15 (RSa4F15) Bit 1/Sa4 Bit of Frame 13 (RSa4F13) Bit 2/Sa4 Bit of Frame 11 (RSa4F11) Bit 3/Sa4 Bit of Frame 9 (RSa4F9) Bit 4/Sa4 Bit of Frame 7 (RSa4F7) Bit 5/Sa4 Bit of Frame 5(RSa4F5) Bit 6/Sa4 Bit of Frame 3 (RSa4F3) Bit 7/Sa4 Bit of Frame
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 RSa6F1 0 RSa6 Received Sa6 Bits CDh 6 RSa6F3 0 5 RSa6F5 0 4 RSa6F7 0 3 RSa6F9 0 2 RSa6F11 0 1 RSa6F13 0 0 RSa6F15 0 Bit 0/Sa6 Bit of Frame 15 (RSa6F15) Bit 1/Sa6 Bit of Frame 13 (RSa6F13) Bit 2/Sa6 Bit of Frame 11 (RSa6F11) Bit 3/Sa6 Bit of Frame 9 (RSa6F9) Bit 4/Sa6 Bit of Frame 7 (RSa6F7) Bit 5/Sa6 Bit of Frame 5 (RSa6F5) Bit 6/Sa6 Bit of Frame 4 (RSa6F4) Bit 7/Sa6 Bit of Frame 3(RSa6F3) Register Name: Register De
DS2155 Register Name: Register Description: Register Address: RSa8 Received Sa8 Bits CFh Bit # Name Default 6 RSa8F3 0 7 RSa8F1 0 5 RSa8F5 0 4 RSa8F7 0 3 RSa8F9 0 2 RSa8F11 0 1 RSa8F13 0 1 TSiF12 0 0 TSiF14 0 Bit 0/Sa8 Bit of Frame 15 (RSa8F15) Bit 1/Sa8 Bit of Frame 13 (RSa8F13) Bit 2/Sa8 Bit of Frame 11 (RSa8F11) Bit 3/Sa8 Bit of Frame 9 (RSa8F9) Bit 4/Sa8 Bit of Frame 7 (RSa8F7) Bit 5/Sa8 Bit of Frame 5 (RSa8F5) Bit 6/Sa8 Bit of Frame 3 (RSa8F3) Bit 7/Sa8 Bit of Frame 1 (RSa8F1) Register Nam
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 TSiF1 0 TSiNAF Transmit Si Bits of the Nonalign Frame D3h 6 TSiF3 0 5 TSiF5 0 4 TSiF7 0 3 TSiF9 0 2 TSiF11 0 1 TSiF13 0 0 TSiF15 0 Bit 0/Si Bit of Frame 15 (TSiF15) Bit 1/Si Bit of Frame 13 (TSiF13) Bit 2/Si Bit of Frame 11 (TSiF11) Bit 3/Si Bit of Frame 9 (TSiF9) Bit 4/Si Bit of Frame 7 (TSiF7) Bit 5/Si Bit of Frame 5 (TSiF5) Bit 6/Si Bit of Frame 3 (TSiF3) Bit 7/Si Bit of Frame 1 (TSiF1) Register Name: Register De
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 TSa4F1 0 TSa4 Transmit Sa4 Bits D5h 6 TSa4F3 0 5 TSa4F5 0 4 TSa4F7 0 3 TSa4F9 0 2 TSa4F11 0 1 TSa4F13 0 0 TSa4F15 0 Bit 0/Sa4 Bit of Frame 15 (TSa4F15) Bit 1/Sa4 Bit of Frame 13 (TSa4F13) Bit 2/Sa4 Bit of Frame 11 (TSa4F11) Bit 3/Sa4 Bit of Frame 9 (TSa4F9) Bit 4/Sa4 Bit of Frame 7 (TSa4F7) Bit 5/Sa4 Bit of Frame 5 (TSa4F5) Bit 6/Sa4 Bit of Frame 3 (TSa4F3) Bit 7/Sa4 Bit of Frame 1 (TSa4F1) Register Name: Register D
DS2155 Register Name: Register Description: Register Address: TSa6 Transmit Sa6 Bits D7h Bit # Name Default 6 TSa6F3 0 7 TSa6F1 0 5 TSa6F5 0 4 TSa6F7 0 3 TSa6F9 0 2 1 0 TSa6F11 TSa6F13 TSa6F15 0 0 0 Bit 0/Sa6 Bit of Frame 15 (TSa6F15) Bit 1/Sa6 Bit of Frame 13 (TSa6F13) Bit 2/Sa6 Bit of Frame 11 (TSa6F11) Bit 3/Sa6 Bit of Frame 9 (TSa6F9) Bit 4/Sa6 Bit of Frame 7 (TSa6F7) Bit 5/Sa6 Bit of Frame 5 (TSa6F5) Bit 6/Sa6 Bit of Frame 3 (TSa6F3) Bit 7/Sa6 Bit of Frame 1 (TSa6F1) Register Name: Register
DS2155 Register Name: Register Description: Register Address: TSa8 Transmit Sa8 Bits D9h Bit # Name Default 6 TSa8F3 0 7 TSa8F1 0 5 TSa8F5 0 4 TSa8F7 0 3 TSa8F9 0 Bit 0/Sa8 Bit of Frame 15 (TSa8F15) Bit 1/Sa8 Bit of Frame 13 (TSa8F13) Bit 2/Sa8 Bit of Frame 11 (TSa8F11) Bit 3/Sa8 Bit of Frame 9 (TSa8F9) Bit 4/Sa8 Bit of Frame 7 (TSa8F7) Bit 5/Sa8 Bit of Frame 5 (TSa8F5) Bit 6/Sa8 Bit of Frame 3 (TSa8F3) Bit 7/Sa8 Bit of Frame 1 (TSa8F1) 124 of 238 2 TSa8F11 0 1 TSa8F13 0 0 TSa8F15 0
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 SiAF 0 TSACR Transmit Sa Bit Control Register DAh 6 SiNAF 0 5 RA 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 Bit 0/Additional Bit 8 Insertion Control Bit (Sa8) 0 = do not insert data from the TSa8 register into the transmit data stream 1 = insert data from the TSa8 register into the transmit data stream Bit 1/Additional Bit 7 Insertion Control Bit (Sa7) 0 = do not insert data from the TSa7 register into the transmit data stream
DS2155 23. HDLC CONTROLLERS This device has two enhanced HDLC controllers, HDLC #1 and HDLC #2. Each controller is configurable for use with time slots, Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). Each HDLC controller has 128-byte buffers in the transmit and receive paths. When used with time slots, the user can select any time slot or multiple time slots, contiguous or noncontiguous, as well as any specific bits within the time slot(s) to assign to the HDLC controllers.
DS2155 Table 23-A.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 NOFS 0 H1TC, H2TC HDLC #1 Transmit Control HDLC #2 Transmit Control 90h, A0h 6 TEOML 0 5 THR 0 4 THMS 0 3 TFS 0 2 TEOM 0 1 TZSD 0 0 TCRCD 0 Bit 0/Transmit CRC Defeat (TCRCD). A 2-byte CRC code is automatically appended to the outbound message. This bit can be used to disable the CRC function. 0 = enable CRC generation (normal operation) 1 = disable CRC generation Bit 1/Transmit Zero-Stuffer Defeat (TZSD).
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 RHR 0 H1RC, H2RC HDLC #1 Receive Control HDLC #2 Receive Control 31h, 32h 6 RHMS 0 5 — 0 4 — 0 3 — 0 2 — 0 1 — 0 0 RSFD 0 Bit 0/Receive SS7 Fill-In Signal Unit Delete (RSFD) 0 = normal operation; all FISUs are stored in the receive FIFO and reported to the host. 1 = When a consecutive FISU having the same BSN the previous FISU is detected, it is deleted without host intervention.
DS2155 23.2.1 FIFO Control The FIFO control register (HxFC) controls and sets the watermarks for the transmit and receive FIFOs. Bits 3, 4, and 5 set the transmit low watermark and the lower 3 bits set the receive high watermark. When the transmit FIFO empties below the low watermark, the TLWM bit in the appropriate HDLC status register SR6 or SR7 is set. TLWM is a real-time bit and remains set as long as the transmit FIFO’s read pointer is below the watermark.
DS2155 23.3 HDLC Mapping 23.3.1 Receive The HDLC controllers must be assigned a space in the T1/E1 bandwidth in which they transmit and receive data. The controllers can be mapped to either the FDL (T1), Sa bits (E1), or to channels. If mapped to channels, then any channel or combination of channels, contiguous or not, can be assigned to an HDLC controller. When assigned to a channel(s), any combination of bits within the channel(s) can be avoided.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 RCB8SE 0 H1RTSBS, H2RTSBS HDLC # 1 Receive Time Slot Bits/Sa Bits Select HDLC # 2 Receive Time Slot Bits/Sa Bits Select 96h, A6h 6 RCB7SE 0 5 RCB6SE 0 4 RCB5SE 0 3 RCB4SE 0 2 RCB3SE 0 1 RCB2SE 0 0 RCB1SE 0 Bit 0/Receive Channel Bit 1 Suppress Enable/Sa8 Bit Enable (RCB1SE ). LSB of the channel. Set to 1 to stop this bit from being used. Bit 1/Receive Channel Bit 2 Suppress Enable/Sa7 Bit Enable (RCB2SE).
DS2155 23.3.2 Transmit The HxTCS1–HxTCS4 registers are used to assign the transmit controllers to channels 1–24 (T1) or 1–32 (E1) according to the following table.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 TCB8SE 0 H1TTSBS, H2TTSBS HDLC # 1 Transmit Time Slot Bits/Sa Bits Select HDLC # 2 Transmit Time Slot Bits/Sa Bits Select 9Bh, ABh 6 TCB7SE 0 5 TCB6SE 0 4 TCB5SE 0 3 TCB4SE 0 2 TCB3SE 0 1 TCB2SE 0 0 TCB1SE 0 Bit 0/Transmit Channel Bit 1 Suppress Enable/Sa8 Bit Enable (TCB1SE). LSB of the channel. Set to 1 to stop this bit from being used. Bit 1/Transmit Channel Bit 2 Suppress Enable/Sa7 Bit Enable (TCB1SE).
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 SR6, SR7 HDLC #1 Status Register 6 HDLC #2 Status Register 7 20h, 22h 6 TMEND 0 5 RPE 0 4 RPS 0 3 RHWM 0 2 RNE 0 1 TLWM 0 0 TNF 0 Bit 0/Transmit FIFO Not Full Condition (TNF). Set when the transmit 128-byte FIFO has at least 1 byte available. Bit 1/Transmit FIFO Below Low-Watermark Condition (TLWM).
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 IMR6, IMR7 HDLC # 1 Interrupt Mask Register 6 HDLC # 2 Interrupt Mask Register 7 21h, 23h 6 TMEND 0 5 RPE 0 4 RPS 0 3 RHWM 0 2 RNE 0 Bit 0/Transmit FIFO Not Full Condition (TNF) 0 = interrupt masked 1 = interrupt enabled—interrupts on rising edge only Bit 1/Transmit FIFO Below Low-Watermark Condition (TLWM) 0 = interrupt masked 1 = interrupt enabled—interrupts on rising edge only Bit 2/Receive FIFO Not Empty Condit
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 INFO5, INFO6 HDLC #1 Information Register HDLC #2 Information Register 2Eh, 2Fh 6 — 0 5 TEMPTY 0 4 TFULL 0 3 REMPTY 0 2 PS2 0 1 PS1 0 0 PS0 0 Bits 0 to 2/Receive Packet Status (PS0 to PS2). These are real-time bits indicating the status as of the last read of the receive FIFO.
DS2155 23.3.3 FIFO Information The transmit FIFO buffer-available register indicates the number of bytes that can be written into the transmit FIFO. The count form this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer.
DS2155 23.3.5 HDLC FIFOs Register Name: Register Description: Register Address: Bit # Name Default 7 THD7 0 H1TF, H2TF HDLC # 1 Transmit FIFO HDLC # 2 Transmit FIFO 9Dh, ADh 6 THD6 0 5 THD5 0 4 THD4 0 3 THD3 0 2 THD2 0 1 THD1 0 0 THD0 0 Bit 0/Transmit HDLC Data Bit 0 (THD0). LSB of an HDLC packet data byte.
DS2155 23.4 Receive HDLC Code Example The following is an example of a receive HDLC routine: 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15) Reset receive HDLC controller. Set HDLC mode, mapping, and high watermark. Start new message buffer. Enable RPE and RHWM interrupts. Wait for interrupt. Disable RPE and RHWM interrupts. Read HxRPBA register. N = HxRPBA (lower 7 bits are byte count, MSB is status). Read (N and 7Fh) bytes from receive FIFO and store in message buffer. Read INFO5 register.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 RFDL7 0 RFDL Receive FDL Register C0h 6 RFDL6 0 5 RFDL5 0 4 RFDL4 0 3 RFDL3 0 2 RFDL2 0 1 RFDL1 0 0 RFDL0 0 The receive FDL register (RFDL) reports the incoming FDL or the incoming Fs bits. The LSB is received first. Bit 0/Receive FDL Bit 0 (RFDL0). LSB of the received FDL code.
DS2155 23.5.3 Transmit Section The transmit section shifts out into the T1 data stream either the FDL (in the ESF framing mode) or the Fs bits (in the D4 framing mode) contained in the transmit FDL register (TFDL). When a new value is written to the TFDL, it is multiplexed serially (LSB first) into the proper position in the outgoing T1 data stream. After the full 8 bits have been shifted out, the framer signals the host microcontroller by setting the SR8.
DS2155 24. LINE INTERFACE UNIT (LIU) The LIU contains three sections: the receiver that handles clock and data recovery, the transmitter that waveshapes and drives the T1 line, and the jitter attenuator. These three sections are controlled by the line interface control registers (LIC1–LIC4), which are described in the following sections. The LIU has its own T1/E1 mode-select bit and can operate independently of the framer function.
DS2155 Normally, the clock that is output at the RCLK pin is the recovered clock from the E1 AMI/HDB3 or T1 AMI/B8ZS waveform presented at the RTIP and RRING inputs. If the jitter attenuator is placed in the receive path (as is the case in most applications), the jitter attenuator restores the RCLK to an approximate 50% duty cycle. If the jitter attenuator is either placed in the transmit path or is disabled, the RCLK output can exhibit slightly shorter high cycles of the clock.
DS2155 24.3 Transmitter The DS2155 uses a phase-lock loop along with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the E1 or T1 line. The waveforms created by the DS2155 meet the latest ETSI, ITU, ANSI, and AT&T specifications. The user selects which waveform is generated by setting the ETS bit (LIC2.7) for E1 or T1 operation, then programming the L2/L1/L0 bits in register LIC1 for the appropriate application. A 2.048MHz or 1.
DS2155 24.4 MCLK Prescaler A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz clock must be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specifications require an accuracy of ±32ppm for T1 interfaces. A prescaler divides the 16MHz, 8MHz, or 4MHz clock down to 2.048MHz. There is an on-board PLL for the jitter attenuator, which converts the 2.048MHz clock to a 1.544MHz rate for T1 applications. Setting JAMUX (LIC2.
DS2155 24.
DS2155 T1 Mode L2 0 0 0 0 1 1 1 1 L1 0 0 1 1 0 0 1 1 L0 0 1 0 1 0 1 0 1 Application DSX-1 (0ft to 133ft) / 0dB CSU DSX-1 (133ft to 266ft) DSX-1 (266ft to 399ft) DSX-1 (399ft to 533ft) DSX-1 (533ft to 655ft) -7.5dB CSU -15dB CSU -22.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 0 TLBC Transmit Line Build-Out Control 7Dh 6 AGCE 0 5 GC5 0 4 GC4 0 3 GC3 0 2 GC2 0 1 GC1 0 0 GC0 0 Bit 0–5 Gain Control Bits 0–5 (GC0–GC5). The GC0 through GC5 bits control the gain setting for the nonautomatic gain mode. Use the tables below for setting the recommended values. The LB (line build-out) column refers to the value in the L0–L2 bits in LIC1 (Line Interface Control 1) register.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 ETS 0 LIC2 Line Interface Control 2 79h 6 LIRST 0 5 IBPV 0 4 TUA1 0 3 JAMUX 0 2 — 0 1 SCLD 0 0 CLDS 0 Bit 0/Custom Line Driver Select (CLDS). Setting this bit to a 1 redefines the operation of the transmit line driver. When this bit is set to a 1 and LIC1.5 = LIC1.6 = LIC1.7 = 0, the device generates a square wave at the TTIP and TRING outputs instead of a normal waveform. When this bit is set to a 1 and LIC1.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 LIC3 Line Interface Control 3 7Ah 6 TCES 0 5 RCES 0 4 MM1 0 3 MM0 0 2 RSCLKE 0 1 TSCLKE 0 0 TAOZ 0 Bit 0/Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern (customer disconnect indication signal) at TTIP and TRING. The transmission of this data pattern is always timed off of TCLK. 0 = disabled 1 = enabled Bit 1/Transmit Synchronization G.703 Clock Enable (TSCLKE) 0 = disable 1.544MHz (T1)/2.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default LIC4 Line Interface Control 4 7Bh 7 CMIE 0 6 CMII 0 5 MPS1 0 4 MPS0 0 3 TT1 0 2 TT0 0 Bits 0, 1/Receive Termination Select (RT0, RT1) RT1 0 0 1 1 RT0 0 1 0 1 Internal Receive-Termination Configuration Internal receive-side termination disabled Internal receive-side 75Ω enabled Internal receive-side 100Ω enabled Internal receive-side 120Ω enabled Bits 2, 3/Transmit Termination Select (TT0, TT1) TT1 0 0 1 1 TT0 0 1 0
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 BSYNC 0 INFO2 Information Register 2 11h 6 BD 0 5 TCLE 0 4 TOCD 0 3 RL3 0 2 RL2 0 1 RL1 0 0 RL0 0 Bits 0 to 3/Receive Level Bits (RL0 to RL3). Real-time bits RL3 RL2 RL1 RL0 Receive Level (dB) 0 0 0 0 Greater than -2.5 0 0 0 1 -2.5 to -5.0 0 0 1 0 -5.0 to -7.5 0 0 1 1 -7.5 to -10.0 0 1 0 0 -10.0 to -12.5 0 1 0 1 -12.5 to -15.0 0 1 1 0 -15.0 to -17.5 0 1 1 1 -17.5 to -20.0 1 0 0 0 -20.0 to -22.5 1 0 0 1 -22.5 to -25.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 ILUT 0 SR1 Status Register 1 16h 6 TIMER 0 5 RSCOS 0 4 JALT 0 3 LRCL 0 2 TCLE 0 1 TOCD 0 0 LOLITC 0 Bit 0/Loss of Line-Interface Transmit-Clock Condition (LOLITC). Set when TCLKI has not transitioned for one channel time. This is a double interrupt bit (Section 6.2). Bit 1/Transmit Open-Circuit Detect Condition (TOCD). Set when the device detects that the TTIP and TRING outputs are open-circuited.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 ILUT 0 IMR1 Interrupt Mask Register 1 17h 6 TIMER 0 5 RSCOS 0 4 JALT 0 3 LRCL 0 2 TCLE 0 Bit 0/Loss-of-Transmit Clock Condition (LOLITC) 0 = interrupt masked 1 = interrupt enabled—generates interrupts on rising and falling edges Bit 1/Transmit Open-Circuit Detect Condition (TOCD) 0 = interrupt masked 1 = interrupt enabled—generates interrupts on rising and falling edges Bit 2/Transmit Current-Limit Exceeded Condition (
DS2155 24.8 Recommended Circuits Figure 24-3. Software-Selected Termination, Metallic Protection VCC DVDD 0.01 µF 2 T3 1 F1 75/100/110/120 Ω Tw isted Pair/Coax TTIP 1.0 µF T1 0.1 µF 2 DVSS S3 S1 TRING VCC 2:1 68 µF 2 Dallas Semiconductor T1/E1/J1 SCT or LIU VCC RTIP TVDD T2 F2 75/100/110/120 Ω Tw isted Pair/Coax 0.1 µF 2 T4 1 TVSS S4 S2 RRING RVDD 0.1 µF 2 RVSS 1:1 60 Ω Design Notes: 1 Choke is optional but should be included when necessary f or common mode noise reduction.
DS2155 Figure 24-4. Software-Selected Termination, Longitudinal Protection VCC F1 100/110/120 Ω Tw isted Pair S3 TTIP 1.0 µF T1 0.01 µF 2 T3 1 0.1 µF 2 DVSS S7 S1 TRING S4 F2 DVDD VCC 2:1 68 µF 2 Dallas Semiconductor T1/E1/J1 SCT or LIU VCC RTIP F3 100/110/120 Ω Tw isted Pair S5 0.1 µF 2 T4 1 TVSS S8 F4 TVDD T2 S2 RRING S6 RVDD 0.1 µF 2 RVSS 1:1 60 Ω Design Notes: 1 Choke is optional but should be included when necessary f or common mode noise reduction.
DS2155 24.9 Component Specifications Table 24-C. Transformer Specifications SPECIFICATION Turns Ratio 3.3V Applications Primary Inductance Leakage Inductance Intertwining Capacitance Transmit Transformer DC Resistance Primary (Device Side) Secondary Receive Transformer DC Resistance Primary (Device Side) Secondary RECOMMENDED VALUE 1:1 (receive) and 1:2 (transmit) ±2% 600µH (min) 1.0µH (max) 40pF (max) 1.0Ω (max) 2.0Ω (max) 1.2Ω (max) 1.
DS2155 Figure 24-5. E1 Transmit Pulse Template 1.2 SCALED AMPLITUDE (IN 75Ω SYSTEMS, 1.0 ON THE SCALE = 2.37VPEAK IN 120Ω SYSTEMS, 1.0 ON THE SCALE = 3.00VPEAK) 1.1 269ns 1.0 0.9 0.8 0.7 G.703 TEMPLATE 194ns 0.6 0.5 219ns 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 -200 -150 -100 -50 0 50 100 150 200 250 TIME (ns) Figure 24-6. T1 Transmit Pulse Template 1.2 1.0 -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 0.9 0.8 0.7 NORMALIZED AMPLITUDE MINIMUM CURVE UI Time Amp.
DS2155 Figure 24-7. Jitter Tolerance UNIT INTERVALS (UIP-P) 1k DS2155 TOLERANCE 100 TR 62411 (DEC. 90) 10 ITU-T G.823 1 0.1 1 10 100 1k FREQUENCY (Hz) 10k 100k Figure 24-8. Jitter Tolerance (E1 Mode) UNIT INTERVALS (UIP-P) 1k DS2155 TOLERANCE 100 40 10 1.5 1 MINIMUM TOLERANCE LEVEL AS PER 0.2 ITU G.823 0.1 1 10 20 100 1k FREQUENCY (Hz) 160 of 238 2.
DS2155 Figure 24-9. Jitter Attenuation (T1 Mode) -20dB C ve ur A TR 62411 (Dec. 90) Prohibited Area -40dB rve Cu JITTER ATTENUATION (dB) 0dB B DS2155 T1 MODE -60dB 1 10 100 1K FREQUENCY (Hz) 10K 100K Figure 24-10. Jitter Attenuation (E1 Mode) JITTER ATTENUATION (dB) 0 TBR12 Prohibited Area ITU G.
DS2155 Figure 24-11. Optional Crystal Connections DS2155 XTALD 1.544MHz/2.048MHz MCLK C1 C2 Note 1: C1 and C2 should be 5pF lower than two times the nominal loading capacitance of the crystal to adjust for the input capacitance of the DS2155.
DS2155 25. PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION The DS2155 has the ability to generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. To transmit a pattern, the user loads the pattern into the transmit code-definition registers (TCD1 and TCD2) and selects the proper length of the pattern by setting the TC0 and TC1 bits in the in-band code control (IBCC) register.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 TC1 0 IBCC In-Band Code Control Register B6h 6 TC0 0 5 RUP2 0 4 RUP1 0 3 RUP0 0 2 RDN2 0 Bits 0 to 2/Receive Down-Code Length Definition Bits (RDN0 to RDN2) RDN2 0 0 0 0 1 1 1 1 RDN1 0 0 1 1 0 0 1 1 RDN0 0 1 0 1 0 1 0 1 Length Selected (bits) 1 2 3 4 5 6 7 8/16 Bits 3 to 5/Receive Up-Code Length Definition Bits (RUP0 to RUP2) RUP2 0 0 0 0 1 1 1 1 RUP1 0 0 1 1 0 0 1 1 RUP0 0 1 0 1 0 1 0 1 Length Selected (bits) 1
DS2155 Register Name: Register Description: Register Address: TCD1 Transmit Code-Definition Register 1 B7h Bit # Name Default 6 C6 0 7 C7 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit 0/Transmit Code-Definition Bit 0 (C0). A don’t care if a 5-, 6-, or 7-bit length is selected. Bit 1/Transmit Code-Definition Bit 1 (C1). A don’t care if a 5-bit or 6-bit length is selected. Bit 2/Transmit Code-Definition Bit 2 (C2). A don’t care if a 5-bit length is selected.
DS2155 Register Name: Register Description: Register Address: RUPCD1 Receive Up-Code Definition Register 1 B9h Bit # Name Default 6 C6 0 7 C7 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Up-Code Definition Bits 0 (C0). A don’t care if a 1-bit to 7-bit length is selected. Bit 1/Receive Up-Code Definition Bit 1 (C1). A don’t care if a 1-bit to 6-bit length is selected. Bit 2/Receive Up-Code Definition Bit 2 (C2).
DS2155 Register Name: Register Description: Register Address: RDNCD1 Receive Down-Code Definition Register 1 BBh Bit # Name Default 6 C6 0 7 C7 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Down-Code Definition Bit 0 (C0). A don’t care if a 1-bit to 7-bit length is selected. Bit 1/Receive Down-Code Definition Bit 1 (C1). A don’t care if a 1-bit to 6-bit length is selected.
DS2155 Register Name: Register Description: Register Address: RSCC In-Band Receive Spare Control Register BDh Bit # Name Default 6 — 0 7 — 0 5 — 0 4 — 0 3 — 0 2 RSC2 0 Bits 0 to 2/Receive Spare Code Length Definition Bits (RSC0 to RSC2) RSC2 RSC1 RSC0 Length Selected (bits) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 2 3 4 5 6 7 8/16 Bits 3 to 7/Unused, must be set to 0 for proper operation 168 of 238 1 RSC1 0 0 RSC0 0
DS2155 Register Name: Register Description: Register Address: RSCD1 Receive Spare-Code Definition Register 1 BEh Bit # Name Default 6 C6 0 7 C7 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Note: Writing this register resets the detector’s integration period. Bit 0/Receive Spare-Code Definition Bit 0 (C0). A don’t care if a 1-bit to 7-bit length is selected. Bit 1/Receive Spare-Code Definition Bit 1 (C1). A don’t care if a 1-bit to 6-bit length is selected.
DS2155 26. BERT FUNCTION The BERT block can generate and detect pseudorandom and repeating bit patterns. It is used to test and stress data communication links, and it is capable of generating and detecting the following patterns: The pseudorandom patterns 2E7, 2E11, 2E15, and QRSS A repetitive pattern from 1 to 32 bits in length Alternating (16-bit) words that flip every 1 to 256 words Daly pattern The BERT receiver has a 32-bit bit counter and a 24-bit error counter.
DS2155 Figure 26-1. Simplified Diagram of BERT in Network Direction TO RECEIVE SYSTEM BACKPLANE INTERFACE FROM RECEIVE FRAMER PER-CHANNEL AND F-BIT (T1 MODE) MAPPING TO TRANSMIT FRAMER BERT RECEIVER BERT TRANSMITTER 1 FROM TRANSMIT SYSTEM BACKPLANE INTERFACE 0 Figure 26-2.
DS2155 26.3 BERT Register Descriptions Register Name: Register Description: Register Address: Bit # Name Default 7 TC 0 BC1 BERT Control Register 1 E0h 6 TINV 0 5 RINV 0 4 PS2 0 3 PS1 0 2 PS0 0 1 LC 0 0 RESYNC 0 Bit 0/Force Resynchronization (RESYNC). A low-to-high transition forces the receive BERT synchronizer to resynchronize to the incoming data stream. This bit should be toggled from low to high whenever the host wishes to acquire synchronization on a new pattern.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default BC2 BERT Control Register 2 E1h 7 EIB2 0 6 EIB1 0 5 EIB0 0 4 SBE 0 3 RPL3 0 2 RPL2 0 1 RPL1 0 0 RPL0 0 Bits 0 to 3/Repetitive Pattern Length Bit 3 (RPL0 to RPL3). RPL0 is the LSB and RPL3 is the MSB of a nibble that describes how long the repetitive pattern is. The valid range is 17 (0000) to 32 (1111). These bits are ignored if the receive BERT is programmed for a pseudorandom pattern.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 SR9 Status Register 9 26h 6 BBED 0 5 BBCO 0 4 BEC0 0 3 BRA1 0 2 BRA0 0 1 BRLOS 0 0 BSYNC 0 Bit 0/BERT in Synchronization Condition (BSYNC). Set when the incoming pattern matches for 32 consecutive bit positions. Refer to BSYNC in the INFO2 register for a real-time version of this bit. This is a double interrupt bit (Section 6.2). Bit 1/BERT Receive Loss-of-Synchronization Condition (BRLOS).
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 IMR9 Interrupt Mask Register 9 27h 6 BBED 0 5 BBCO 0 4 BEC0 0 3 BRA1 0 2 BRA0 0 1 BRLOS 0 0 BSYNC 0 Bit 0/BERT in Synchronization Condition (BSYNC) 0 = interrupt masked 1 = interrupt enabled—interrupts on rising and falling edges Bit 1/Receive Loss-of-Synchronization Condition (BRLOS) 0 = interrupt masked 1 = interrupt enabled—interrupts on rising and falling edges Bit 2/Receive All-Zeros Condition (BRA0) 0 = int
DS2155 26.4 BERT Repetitive Pattern Set These registers must be properly loaded for the BERT to generate and synchronize to a repetitive pattern, a pseudorandom pattern, alternating word pattern, or a Daly pattern. For a repetitive pattern that is fewer than 32 bits, the pattern should be repeated so that all 32 bits are used to describe the pattern.
DS2155 26.5 BERT Bit Counter Once BERT has achieved synchronization, this 32-bit counter increments for each data bit (i.e., clock) received. Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and sets the BBCO status bit. Register Name: Register Description: Register Address: Bit # Name Default 7 BBC7 0 BBC1 BERT Bit Count Register 1 E3h 6 BBC6 0 5 BBC5 0 4 BBC4 0 3 BBC3 0 2 BBC2 0 1 BBC1 0 0 BBC0 0 Bits 0 to 7/BERT Bit Counter Bits 0 to 7 (BBC0 to BBC7).
DS2155 26.6 BERT Error Counter Once BERT has achieved synchronization, this 24-bit counter increments for each data bit received in error. Toggling the LC control bit in BC1 can clear this counter. This counter saturates when full and sets the BECO status bit. Register Name: Register Description: Register Address: Bit # Name Default 7 EC7 0 BEC1 BERT Error-Count Register 1 E7h 6 EC6 0 5 EC5 0 4 EC4 0 3 EC3 0 2 EC2 0 1 EC1 0 0 EC0 0 Bits 0 to 7/Error Counter Bits 0 to 7 (EC0 to EC7).
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 BIC BERT Interface Control Register EAh 6 RFUS 0 5 — 0 4 TBAT 0 3 TFUS 0 2 — 0 1 BERTDIR 0 0 BERTEN 0 Bit 0/BERT Enable (BERTEN) 0 = BERT disabled 1 = BERT enabled Bit 1/BERT Direction (BERTDIR) 0 = network BERT transmits toward the network (TTIP and TRING) and receives from the network (RTIP and RRING). The BERT pattern can be looped back to the receiver internally by using the framer loopback function.
DS2155 27. PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY) An error-insertion function is available in the DS2155 and is used to create errors in the payload portion of the T1 frame in the transmit path. This function is only available in T1 mode. Errors can be inserted over the entire frame or the user can select which channels are to be corrupted. Errors are created by inverting the last bit in the count sequence. For example, if the error rate 1 in 16 is selected, the 16th bit is inverted.
DS2155 Register Name: Register Description: Register Address: ERC Error-Rate Control Register EBh Bit # Name Default 6 — 0 7 WNOE 0 5 — 0 4 CE 0 3 ER3 0 2 ER2 0 1 ER1 0 0 ER0 0 Bits 0 to 3/Error-Insertion Rate Select Bits (ER0 to ER3) ER3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 ER2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 ER1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ER0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Error Rate No errors inserted 1 in 16 1 in 32 1 in 64 1 in 128 1 in 256 1 in 512 1 in 1024 1 in 2048 1 in 4096 1 in 81
DS2155 27.1 Number-of-Errors Registers The number-of-error registers determine how many errors are generated. Up to 1023 errors can be generated. The host loads the number of errors to be generated into the NOE1 and NOE2 registers. The host can also update the number of errors to be created by first loading the prescribed value into the NOE registers and then toggling the WNOE bit in the error-rate control registers. Table 27-B.
DS2155 27.1.1 Number-of-Errors Left Register The host can read the NOELx registers at any time to determine how many errors are left to be inserted. Register Name: Register Description: Register Address: NOEL1 Number-of-Errors Left 1 EEh Bit # Name Default 6 C6 0 7 C7 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bits 0 to 7/Number-of-Errors Left Counter Bits 0 to 7 (C0 to C7). Bit C0 is the LSB of the 10-bit counter.
DS2155 28. INTERLEAVED PCM BUS OPERATION (IBO) In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The DS2155 can be configured to allow PCM data to be multiplexed into higher speed buses eliminating external hardware, saving board space and cost. The DS2155 can be configured for channel or frame interleave. The interleaved PCM bus operation (IBO) supports three bus speeds. The 4.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 IBOC Interleave Bus Operation Control Register C5h 6 IBS1 0 5 IBS0 0 4 IBOSEL 0 3 IBOEN 0 2 DA2 0 1 DA1 0 0 DA0 0 Bits 0 to 2/Device Assignment Bits (DA0 to DA2) DA2 0 0 0 0 1 1 1 1 DA1 0 0 1 1 0 0 1 1 DA0 0 1 0 1 0 1 0 1 Device Position on Bus 1st 2nd 3rd 4th 5th 6th 7th 8th Bit 3/Interleave Bus Operation Enable (IBOEN) 0 = IBO disabled 1 = IBO enabled Bit 4/Interleave Bus Operation Select (IBOSEL).
DS2155 Figure 28-1. IBO Example RSYSCLK TSYSCLK RSYSCLK TSYSCLK RSYNC TSSYNC RSYNC TSSYNC RSIG TSIG RSIG TSIG TSER DS2155 #1 RSER TSER DS2155 #3 RSER 8.
DS2155 29. EXTENDED SYSTEM INFORMATION BUS (ESIB) The extended system information bus (ESIB) allows up to eight DS2155s to share an 8-bit CPU bus for reporting alarms and interrupt status as a group. With a single bus read, the host can be updated with alarm or interrupt status from all members of the group. There are two control registers (ESIBCR1 and ESIBCR2) and four information registers (ESIB1, ESIB2, ESIB3, and ESIB4). For example, eight DS2155s can be grouped into an ESIB group.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 ESIBCR1 Extended System Information Bus Control Register 1 B0h 6 — 0 5 — 0 4 — 0 3 ESIBSEL2 0 2 ESIBSEL1 0 1 ESIBSEL0 0 0 ESIEN 0 Bit 0/Extended System Information Bus Enable (ESIEN) 0 = disabled 1 = enabled Bits 1 to 3/Output Data Bus Line Select (ESIBSEL0 to ESIBSEL2). These bits tell the DS2155 what data bus bit to output the ESIB data on when one of the ESIB information registers is accessed.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 ESIBCR2 Extended System Information Bus Control Register 2 B1h 6 ESI4SEL2 0 5 ESI4SEL1 0 4 ESI4SEL0 0 3 — 0 2 ESI3SEL2 0 1 ESI3SEL1 0 0 ESI3SEL0 0 Bits 0 to 2/Address ESI3 Data Output Select (ESI3SEL0 to ESI3SEL2). These bits select what status is to be output when the DS2155 decodes an ESI3 address during a bus read operation.
DS2155 Register Name: Register Description: Register Address: ESIB1 Extended System Information Bus Register 1 B2h Bit # Name Default 6 DISn 0 7 DISn 0 5 DISn 0 4 DISn 0 3 DISn 0 2 DISn 0 1 DISn 0 0 DISn 0 Bits 0 to 7/Device Interrupt Status (DISn). Causes all devices participating in the ESIB group to output their interrupt status on the appropriate data bus line selected by the ESIBSEL0 to ESIBSEL2 bits of the ESIBCR1 register.
DS2155 30. PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER The DS2155 contains an on-chip clock synthesizer that generates a user-selectable clock output on the BPCLK pin, referenced to the recovered receive clock (RCLK). The synthesizer uses a phase-locked loop to generate low-jitter clocks. Common applications include generation of port and backplane system clocks. The CCR2 register is used to enable (CCR2.0) and select (CCR2.1 and CCR2.2) the clock frequency of the BPCLK pin.
DS2155 Register Name: Register Description: Register Address: Bit # Name Default 7 TMSS 0 CCR3 Common Control Register 3 72h 6 INTDIS 0 5 0 4 0 3 TDATFMT 0 2 TGPCKEN 0 1 RDATFMT 0 0 RGPCKEN 0 Bit 0/Receive Gapped-Clock Enable (RGPCKEN) 0 = RCHCLK functions normally 1 = enable gapped bit-clock output on RCHCLK Bit 1/Receive Channel-Data Format (RDATFMT) 0 = 64kbps (data contained in all 8 bits) 1 = 56kbps (data contained in seven out of the 8 bits) Bit 2/Transmit Gapped-Clock Enable (TGPCKEN) 0 =
DS2155 32. USER-PROGRAMMABLE OUTPUT PINS The DS2155 provides four user-programmable output pins. The pins are automatically cleared to 0 at power-up or as a result of a hardware- or software-issued reset.
DS2155 33. TRANSMIT FLOW DIAGRAMS Figure 33-1. T1 Transmit Flow Diagram TSIG TSER T1 TRANSMIT FLOW DIAGRAM Hardware Signaling HSIE1-3 through PCPR TX ESTORE KEY - PIN Estore Mux ESCR.4 TESE - SELECTOR TESO Off-Chip Connection RDATA From T1_rcv_logic - REGISTER TDATA LBCR1.1 PLB Payload Loopback HDLC Engine #1 TLINK H1TC.4 THMS1 HDLC FDL #1 HDLC Mux #1 HDLC Engine #2 H2TC.4 THMS2 THMS2 H2TC.4 H2TCS1-3 HDLC Mux #2 HDLC FDL #2 TFDL T1TCR2.5 TZSE THMS1 H1TC.
DS2155 From ESF Yellow Alarm From BOC Mux From F-bit Mux TFPT T1TCR1.5 FDL Mux TFM T1CCR1.2 ESF Yellow TYEL T1TCR1.0 CRC Mux TCPT T1TCR1.5 D4 bit 2 Yellow Alm BERT Engine TFM T1CCR1.2 TD4YM T1TCR2.2 TYEL T1TCR1.0 TFUS BIC.3 F-bit BERT Mux T1TCR2.3 FBCT1 T1TCR2.4 FBCT2 F-bit Corruption BTCS1-3 Payload error insertion NOEL != 0 ERC.4 CE BERTEN BIC.0 PEICS1-3 SSIE1-3 Bit 7 stuffing T1CCR1.1 PDE GB7S T1TCR1.3 B7SE T1TCR2.0 Pulse Density Enforcer TPDV INFO1.
DS2155 Figure 33-2. E1 Transmit Flow Diagram TSER E1 TRANSMIT FLOW DIAGRAM TSIG Hardware Signaling HSIE1-4 through PCPR TX ESTORE Estore Mux ESCR.4 TESE TESO Off-Chip Connection TDATA RDATA From E1_rcv_logic Payload Loopback Mux LBCR1.1 PLB HDLC Engine #1 THMS1 H1TC.4 HDLC DS0 Mux #1 H1TCS1-4 H1TTSBS THMS1 H1TC.4 HDLC Sa-bit Mux #1 T1SaBE4T1SaBE8 H1TTSBS.4 - H1TTSBS.0 HDLC Engine #2 THMS2 H2TC.4 H2TCS1-4 H2TTSBS HDLC DS0 Mux #2 KEY THMS2 H2TC.
DS2155 From Idle Code Mux RDATA From E1_rcv_logic Per-Channel Loopback E1 TRANSMIT FLOW DIAGRAM PCLR1-4 TNAF THMS1 Sa-bit Mux TS0 Mux E1TCR1.4 TSIS H1TC.4 THMS2 H2TC.4 TAF/TNAF(non Sa) TFPT E1TCR1.7 Si-bit Mux Si = CRC4 MF Align Word (Does not overwrite E-bits) E1TCR1.0 TCRC4 E1TCR2.2 AEBE Sa4S - Sa8S E1TCR2.5 - E1TCR2.7 E1TCR2.8 ARA TSaCR Si/CRC4 Mux TLINK Auto Ebit Gen TLINK Mux TSiAF TSiNAF TRA TSa4 Auto RA Gen TSa5 TSa6 TSa7 TSa8 TSaCR Mux TSA1 E1TCR1.3 SSIE1-4 E1TCR1.
DS2155 From HDB3 Encoding Mux IOCR1.0 ODF Bipolar/ NRZ coding E1 TRANSMIT FLOW DIAGRAM FLB LBCR1.0 FLB Select RPOS TO RECEIVER RNEG RLB Mux RLB Mux RLB LBCR1.2 1/2 CLK/ FULL CLK CCR1.
DS2155 34. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT 34.1 Description The DS2155 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGH-Z, CLAMP, and IDCODE (Figure 34-1.). The DS2155 contains the following features as required by IEEE 1149.1 standard test access port (TAP) and boundary scan architecture.
DS2155 TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK (Figure 34-2). Test-Logic-Reset Upon power-up, the TAP controller is in the Test-Logic-Reset state. The instruction register contains the IDCODE instruction. All system logic of the device operates normally. Run-Test-Idle The Run-Test-Idle is used between scan operations or during specific tests. The instruction register and test registers remain idle.
DS2155 Select-IR-Scan All test registers retain their previous state. The instruction register remains unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the Test-Logic-Reset state. Capture-IR The Capture-IR state is used to load the shift register in the instruction register with a fixed value.
DS2155 Figure 34-2. TAP Controller State Diagram 1 Test Logic Reset 0 0 Run Test/ Idle 1 Select DR-Scan 1 Select IR-Scan 0 1 0 1 Capture DR Capture IR 0 Shift DR 0 Shift IR 0 1 Exit DR Exit IR 1 0 Pause IR 0 1 0 0 1 1 0 Pause DR 1 Exit2 DR 1 0 Exit2 IR 1 1 Update DR Update IR 1 1 0 0 0 34.2 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length.
DS2155 Table 34-A. Instruction Codes for IEEE 1149.1 Architecture INSTRUCTION SELECTED REGISTER INSTRUCTION CODES SAMPLE/PRELOAD BYPASS EXTEST CLAMP HIGHZ IDCODE Boundary Scan Bypass Boundary Scan Bypass Bypass Device Identification 010 111 000 011 100 001 SAMPLE/PRELOAD This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions.
DS2155 Table 34-B. ID Code Structure MSB LSB Version Contact Factory Device ID JEDEC 1 4 bits 16 bits 00010100001 1 Table 34-C. Device ID Codes PART DS2155 DS2156 DS21354 DS21554 DS21352 DS21552 16-BIT ID 0010h 0019h 0005h 0003h 0004h 0002h 34.3 Test Registers IEEE 1149.1 requires a minimum of two test registers, the boundary scan register and the bypass register. An optional test register, the identification register, has been included with the DS2155 design.
DS2155 Table 34-D. Boundary Scan Control Bits BIT PIN NAME TYPE 3 — 1 2 RCHBLK JTMS O I 2 — BPCLK.cntl — 1 — — 0 — 3 4 5 6 7 BPCLK JTCLK JTRST RCL JTDI I/O I I O I 98 — UOP0.cntl — 97 8 UOP0 I/O 96 — UOP1.cntl — 95 94 9 10 11 UOP1 JTDO BTS I/O O I 93 — LIUC.cntl — 92 91 90 89 — — — — — — 12 13 14 15 16 17 18 19, 20, 24 21 22 LIUC 8XCLK TSTRST UOP2 RTIP RRING RVDD RVSS MCLK XTALD I/O O I O I I — — I O 88 — UOP3.
DS2155 BIT PIN NAME TYPE 74 73 39 40 TNEGI TCLKI I I 72 — TCLKO.cntl — 71 41 TCLKO I/O 70 — TNEGO.cntl — 69 42 TNEGO I/O 68 — TPOSO.cntl 67 — — 66 65 64 63 62 61 60 43 44 45 46 47 48 49 50 51 52 TPOSO DVDD DVSS TCLK TSER TSIG TESO TDATA TSYSCLK TSSYNC 59 — TCHCLK.cntl 58 53 TCHCLK 57 — ESIBS1.cntl 56 55 54 55 ESIBS1 MUX 54 — BUS.
DS2155 BIT PIN NAME TYPE 30 29 82 85 RCLK RDATA O O 28 — RPOSI.cntl — 27 86 RPOSI I/O 26 — RNEGI.cntl — 25 87 RNEGI I/O 24 — RCLKI.cntl — 23 22 21 20 88 89 90 91 RCLKI RCLKO RNEGO RPOSO I/O O O O 19 — RCHCLK.cntl I/O 18 92 RCHCLK I/O 17 — RSIGF.cntl — 16 93 RSIGF I/O 15 — RSIG.cntl — 14 13 12 11 94 95 — 96 RSIG RSER RMSYNC.cntl RMSYNC I/O O — I/O 10 — RFSYNC.cntl — 9 97 RFSYNC I/O 8 — RSYNC.
DS2155 35. FUNCTIONAL TIMING DIAGRAMS 35.1 T1 Mode Figure 35-1. Receive-Side D4 Timing 1 FRAME# 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 RFSYNC RSYNC 1 RSYNC 2 3 RSYNC RLCLK 4 RLINK Note 1: RSYNC in the frame mode (IOCR1.5 = 0) and double-wide frame sync is not enabled (IOCR1.6 = 0). Note 2: RSYNC in the frame mode (IOCR1.5 = 0) and double-wide frame sync is enabled (IOCR1.6 = 1). Note 3: RSYNC in the multiframe mode (IOCR1.5 = 1).
DS2155 Figure 35-3. Receive-Side Boundary Timing (Elastic Store Disabled) RCLK CHANNEL 23 RSER CHANNEL 24 CHANNEL 1 LSB LSB MSB F MSB RSYNC RFSYNC RSIG CHANNEL 23 A B C/A D/B CHANNEL 24 A B C/A D/B CHANNEL 1 A RCHCLK RCHBLK1 RLCLK RLINK 2 Note 1: RCHBLK is programmed to block channel 24. Note 2: Shown is RLINK/RLCLK in the ESF framing mode. Figure 35-4. Receive-Side 1.
DS2155 Figure 35-5. Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) RSYSCLK CHANNEL 31 1 CHANNEL 32 RSER CHANNEL 1 LSB LSB MSB F 5 2 RSYNC RMSYNC 3 RSYNC A RSIG CHANNEL 31 B C/A D/B A CHANNEL 1 CHANNEL 32 B C/A D/B RCHCLK 4 RCHBLK Note 1: RSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 are forced to 1. Note 2: RSYNC is in the output mode (IOCR1.4 = 0). Note 3: RSYNC is in the input mode (IOCR1.4 = 1).
DS2155 Figure 35-7. Transmit-Side ESF Timing FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 TSYNC1 TSSYNC TSYNC 2 3 TSYNC TLCLK 4 TLINK TLCLK 5 TLINK 6 Note 1: TSYNC in frame mode (IOCR1.2 = 0) and double-wide frame sync is not enabled (IOCR1.3 = 0). Note 2: TSYNC in frame mode (IOCR1.2 = 0) and double-wide frame sync is enabled (IOCR1.3 = 1). Note 3: TSYNC in multiframe mode (IOCR1.2 = 1).
DS2155 Figure 35-9. Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) TSYSCLK CHANNEL 23 CHANNEL 24 LSB MSB TSER CHANNEL 1 LSB F MSB TSSYNC CHANNEL 23 TSIG A B CHANNEL 24 C/A D/B A B CHANNEL 1 C/A D/B A TCHCLK TCHBLK 1 Note 1: TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG is ignored during channel 24). Figure 35-10. Transmit-Side 2.
DS2155 35.2 E1 Mode Figure 35-11. Receive-Side Timing 1 FRAME# 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 RFSYNC RSYNC 1 RSYNC 2 RLCLK RLINK 3 4 Note 1: RSYNC in frame mode (IOCR1.5 = 0). Note 2: RSYNC in multiframe mode (IOCR1.5 = 1). Note 3: RLCLK is programmed to output just the Sa bits. Note 4: RLINK always outputs all five Sa bits as well as the rest of the receive data stream. Note 5: This diagram assumes the CAS MF begins in the RAF frame. Figure 35-12.
DS2155 Figure 35-13. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (Elastic Store Enabled) RSYSCLK CHANNEL 23/31 1 RSER CHANNEL 24/32 CHANNEL 1/2 LSB LSB MSB F MSB RSYNC2 RMSYNC 3 RSYNC RCHCLK RCHBLK 4 Note 1: Data from the E1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is mapped to channel 1 of the T1 link, etc.) and the F-bit position is added (forced to on 1). Note 2: RSYNC in the output mode (IOCR1.4 = 0). Note 3: RSYNC in the input mode (IOCR1.4 = 1).
DS2155 Figure 35-15.
DS2155 Figure 35-16. Receive IBO Frame Interleave Mode Timing FRAMER #1, CHANNELS 1 through 32 RSYNC 1 RSER F2 F1 F2 F1 RSIG1 F2 F1 F2 F1 RSER2 F3 RSIG2 F4 F3 RSER3 F5 RSIG3 F5 F4 F6 F7 F6 F8 F7 F1 F8 F1 F2 F2 F1 F2 F3 F4 F1 F2 F3 F4 F1 F2 F3 F4 F1 F2 F3 F4 F2 F2 F3 F3 F4 F4 F5 F5 F6 F7 F6 F8 F7 F8 F1 F1 F2 F2 F3 F3 F4 F4 F5 F6 F5 F7 F6 F8 F7 F8 BIT LEVEL DETAIL (4.
DS2155 Figure 35-17. G.802 Timing, E1 Mode Only TS # 31 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 RSYNC TSYNC RCHCLK TCHCLK RCHBLK TCHBLK RCLK / RSYSCLK TCLK / TSYSCLK CHANNEL 25 CHANNEL 26 LSB MSB RSER / TSER RCHCLK / TCHCLK RCHBLK / TCHBLK Note 1: RCHBLK or TCHBLK programmed to pulse high during time slots 1 through 15, 17 through 25, and bit 1 of time slot 26. Figure 35-18.
DS2155 Figure 35-19. Transmit-Side Boundary Timing (Elastic Store Disabled) TCLK CHANNEL 1 LSB TSER Si 1 A CHANNEL 2 Sa4 Sa5 Sa6 Sa7 Sa8 MSB LSB MSB TSYNC1 TSYNC2 CHANNEL 1 TSIG CHANNEL 2 D A B C D TCHCLK TCHBLK 3 TLCLK TLINK 4 4 DON'T CARE DON'T CARE Note 1: TSYNC is in the output mode (IOCR1.1 = 1). Note 2: TSYNC is in the input mode (IOCR1.1 = 0). Note 3: TCHBLK is programmed to block channel 2. Note 4: TLINK is programmed to source the Sa4 bit.
DS2155 Figure 35-21. Transmit-Side Boundary Timing, TSYSCLK = 2.048MHz (Elastic Store Enabled) TSYSCLK CHANNEL 31 TSER CHANNEL 32 1 CHANNEL 1 LSB MSB LSB F 4 TSSYNC CHANNEL 31 TSIG A B CHANNEL 32 C D A TCHCLK TCHBLK 2,3 Note 1: TCHBLK is programmed to block channel 31.
DS2155 Figure 35-22.
DS2155 Figure 35-23. Transmit IBO Frame Interleave Mode Timing FRAMER #1, CHANNELS 1 through 32 TSSYNC 1 TSER TSIG1 TSER2 F2 F1 F2 F1 F2 F1 F2 F1 F3 TSIG2 F4 F3 TSER3 F5 TSIG3 F5 F4 F6 F7 F6 F8 F7 F1 F8 F1 F2 F2 F1 F2 F3 F4 F1 F2 F3 F4 F1 F2 F3 F4 F1 F2 F3 F4 F2 F2 F3 F3 F4 F4 F5 F5 F6 F7 F6 F8 F7 F8 F1 F1 F2 F2 F3 F3 F4 F4 F5 F6 F5 F7 F6 F8 F7 F8 BIT LEVEL DETAIL (4.
DS2155 36. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Operating Temperature Range for DS2155L Operating Temperature Range for DS2155LN Storage Temperature Range Soldering Temperature -1.0V to +6.
DS2155 DC CHARACTERISTICS (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS2155L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS2155LN.) PARAMETER SYMBOL Supply Current Input Leakage Output Leakage Output Current (2.4V) Output Current (0.4V) IDD IIL ILO IOH IOL CONDITIONS (Note 5) (Note 6) (Note 7) MIN TYP MAX 75 -1.0 -1.0 +4.0 +1.0 1.0 UNITS mA μA μA mA mA Note 2: The package is mounted on a four-layer JEDEC standard test board.
DS2155 37. AC TIMING PARAMETERS AND DIAGRAMS Capacitive test loads are 40pF for bus signals, 20pF for all others. 37.1 Multiplexed Bus AC Characteristics AC CHARACTERISTICS: MULTIPLEXED PARALLEL PORT (MUX = 1) (Figure 37-1, Figure 37-2, and Figure 37-3) (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS2155L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS2155LN.
DS2155 Figure 37-1. Intel Multiplexed Bus Read Timing (BTS = 0/MUX = 1) t CYC ALE WR* PWASH t ASD t ASD t ASED PWEH RD* t CH t CS PWEL CS* t ASL t DHR t DDR AD0-AD7 t AHL Figure 37-2.
DS2155 Figure 37-3.
DS2155 37.2 Nonmultiplexed Bus AC Characteristics AC CHARACTERISTICS: NONMULTIPLEXED PARALLEL PORT (MUX = 0) (Figure 37-4, Figure 37-5, Figure 37-6, and Figure 37-7) (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS2155L; VDD = 3.3V ±5%, TA = -40°C to +85°C; for DS2155LN.
DS2155 Figure 37-4. Intel Nonmultiplexed Bus Read Timing (BTS = 0/MUX = 0) ADDRESS VALID A0 to A7 D0 to D7 DATA VALID t5 5ns (min) / 20ns (max) WR t1 CS 0ns (min) 0ns (min) t2 t3 t4 0ns (min) 50ns (max) RD Figure 37-5.
DS2155 Figure 37-6. Motorola Nonmultiplexed Bus Read Timing (BTS = 1/MUX = 0) A0 to A7 ADDRESS VALID DATA VALID D0 to D7 5ns (min) / 20ns (max) R/W t1 CS 0ns (min) t5 0ns (min) t2 t3 t4 0ns (min) 75ns (max) DS Figure 37-7.
DS2155 37.3 Receive-Side AC Characteristics AC CHARACTERISTICS: RECEIVE SIDE (Figure 37-8., Figure 37-9, and Figure 37-10) (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS2155L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS2155LN.) PARAMETER RCLKO Period RCLKO Pulse Width RCLKO Pulse Width SYMBOL MIN TYP (Note 1) 200 488 (E1) 648 (T1) 0.5 tLP 0.5 tLP tLH (Note 1) (Note 2) 200 150 0.5 tLP tLL (Note 2) 150 (Note 3) 0.5 tLP 488 (E1) 648 (T1) 0.5 tCP 0.
DS2155 Figure 37-8. Receive-Side Timing RCLK t D1 RSER / RDATA / RSIG 1ST FRAME BIT t D2 RSYNC 1 t D2 RFSYNC / RMSYNC t D2 RCHCLK t D2 RCHBLK t D2 RLCLK 2 t D1 RLINK (T1MODE) 4 RLINK (E1 MODE) Sa4 to Sa8 Bit Position Note 1: RSYNC is in the output mode. Note 2: Shown is RLINK/RLCLK in the ESF framing mode. Note 3: No relationship between RCHCLK and RCHBLK and other signals is implied. Note 4: RLCLK only pulses high during Sa bit locations as defined in the E1RCR2 register.
DS2155 Figure 37-9. Receive-Side Timing, Elastic Store Enabled t SL tF tR RSYSCLK t SH t SP t D3 SEE NOTE 3 RSER / RSIG t D4 RCHCLK t D4 RCHBLK t D4 RMSYNC RSYNC RSYNC t D4 1 t HD t SU 2 Note 1: RSYNC is in the output mode. Note 2: RSYNC is in the input mode. Note 3: F-bit when MSTRREG.1 = 0, MSB of TS0 when MSTREG.1 = 1. Figure 37-10.
DS2155 37.4 Backplane Clock Timing: AC Characteristics AC CHARACTERISTICS: BACKPLANE CLOCK SYNTHESIS (Figure 37-11) (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS2155L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS2155LN.) PARAMETER SYMBOL Delay RCLK to BPCLK CONDITIONS MIN tD1 Figure 37-11 Receive Timing Delay RCLK to BPCLK RCLK t D1 BPCLK Note 1: If RCLK is 1.544 MHz, BPCLK will be asynchronous.
DS2155 37.5 Transmit AC Characteristics AC CHARACTERISTICS: TRANSMIT SIDE (Figure 37-12, Figure 37-13, and Figure 37-14) (VDD = 3.3V ±5%, TA = -40°C to +85°C for DS2155L; VDD = 3.3V ±5%, TA = 0°C to +70°C for DS2155LN) PARAMETER SYMBOL TCLK Period tCP TCLK Pulse Width tCH tCL TCLKI Period tLP TCLKI Pulse Width tLH tLL CONDITIONS MIN 20 20 20 20 (Note 8) (Note 9) (Note 10) (Note 11) (Note 12) TYP (E1) 488 (E1) 648 (T1) 0.5 tCP 0.5 tCP 488 (E1) 648 (T1) 0.5 tLP 0.5 tLP 648 448 244 122 61 0.
DS2155 Figure 37-12. Transmit-Side Timing t CP t CL tF tR t CH TCLK t D1 TESO t SU TSER / TSIG / TDATA t HD t D2 TCHCLK t D2 TCHBLK t D2 TSYNC1 t HD t SU TSYNC2 5 TLCLK t D2 t HD TLINK t SU Note 1: TSYNC is in the output mode (IOCR1.1 = 1). Note 2: TSYNC is in the input mode (IOCR1.1 = 0). Note 3: TSER is sampled on the falling edge of TCLK when the transmit-side elastic store is disabled. Note 4: TCHCLK and TCHBLK are synchronous with TCLK when the transmit-side elastic store is disabled.
DS2155 Figure 37-13. Transmit-Side Timing, Elastic Store Enabled t SP t SL tF tR t SH TSYSCLK t SU TSER t D3 t HD TCHCLK t D3 TCHBLK t SU t HD TSSYNC Note 1: TSER is only sampled on the falling edge of TSYSCLK when the transmit-side elastic store is enabled. Note 2: TCHCLK and TCHBLK are synchronous with TSYSCLK when the transmit-side elastic store is enabled. Figure 37-14.
DS2155 38. PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 38.
DS2155 38.2 100-Ball CSBGA (56-G6008-001) 238 of 238 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
