Datasheet

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2. FUNCTIONAL DESCRIPTION
A clock input at CLKIN is converted to an alternate clock rate available on CLKOUT1. A higher multiple-rate clock
also is available on CLKOUT2. Additionally, an 8kHz clock locked to CLKIN is always available at the SYNCOUT
pin. The SEL pin controls clock-rate conversion selection.
2.1 Mode Select
The SEL pin is used to select the operating frequencies. Table 2-A shows the SEL state for the various operating
modes of the DS21600, DS21602, and DS21604.
Table 2-A. Frequency Conversions (MHz)
PART SEL CLKIN CLKOUT1 CLKOUT2
0 1.544 2.048 6.144
DS21600
1 2.048 1.544 6.176
0 1.544 2.048 8.192
DS21602
1 2.048 1.544 6.176
0 1.544 4.096 8.192
DS21604
1 4.096 1.544 6.176
2.2 Frame-Sync Input
In all cases, CLKOUT1 and CLKOUT2 are frequency-locked to CLKIN. CLKOUT1, CLKOUT2, and SYNCOUT
are phased-locked to SYNCIN when SYNCIN is asserted. The signal applied to SYNCIN can be 8kHz or some
integer subrate such as 1kHz, 2kHz, or 4kHz. Phase synchronization occurs within a maximum of 50ms when
SYNCIN is 8kHz.
3. OUTPUT JITTER
Table 3-A shows the output jitter specifications for 2.048MHz (or 4.096MHz) to 1.544MHz conversions (SEL = 1)
and 1.544MHz to 2.048MHz (or 4.096MHz) conversions (SEL = 0).
Table 3-A. Output Jitter Specifications
CLKIN
(MHz)
CLKOUT1
(MHz)
FREQUENCY
BAND
SPECIFICATION VALUE TYP MAX UNITS
20Hz–100kHz G.823 1.500 0.018 0.035 UI
P-P
1.544 2.048
18kHz–100kHz G.823 0.200 0.012 0.025 UI
P-P
No bandlimiting TR62411 0.050 0.010 0.020 UI
P-P
10Hz–40kHz TR62411 0.025 0.005 0.010 UI
P-P
2.048 or
4.096
1.544
8kHz–40kHz TR62411 0.025 0.006 0.012 UI
P-P