DS21Q50 Quad E1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS21Q50 E1 quad transceiver contains all the necessary functions for connecting to four E1 lines. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. The DS21Q50 automatically adjusts to E1 22AWG (0.6mm) twisted-pair cables from 0km to over 2km in length. The device can generate the necessary G.703 waveshapes for both 75W coax and 120W twisted-pair cables.
DS21Q50 TABLE OF CONTENTS 1. INTRODUCTION ...............................................................................................................................6 2. PIN DESCRIPTION............................................................................................................................9 2.1 PIN FUNCTION DESCRIPTION.........................................................................................................15 2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.1.6 2.1.
DS21Q50 17. CMI (CODE MARK INVERSION).................................................................................................64 18. INTERLEAVED PCM BUS OPERATION....................................................................................66 19. FUNCTIONAL TIMING DIAGRAMS...........................................................................................68 19.1 RECEIVE TIMING DIAGRAMS .....................................................................................................
DS21Q50 LIST OF FIGURES Figure 1-1. Block Diagram ............................................................................................................................8 Figure 3-1. Serial Port Operation Mode 1 ...................................................................................................21 Figure 3-2. Serial Port Operation Mode 2 ...................................................................................................21 Figure 3-3. Serial Port Operation Mode 3 ........
DS21Q50 LIST OF TABLES Table 2-1. Pin Assignments (by Function) ....................................................................................................9 Table 2-2. Pin Assignment (by LQFP Pin Number)....................................................................................12 Table 3-1. Bus Mode Select.........................................................................................................................20 Table 3-2. Register Map ......................................
DS21Q50 1. INTRODUCTION The DS21Q50 is optimized for high-density termination of E1 lines. Two significant features are included for this type of application: the interleave bus option (IBO) and a system clock synthesizer feature. The IBO allows up to eight E1 data streams to be multiplexed onto a single high-speed PCM bus without additional external logic.
DS21Q50 Note: This data sheet assumes a particular nomenclature of the E1 operating environment. In each 125µs frame, there are 32 8-bit time slots numbered 0 to 31. Time slot 0 is transmitted first and received first. These 32 time slots are also referred to as channels with a numbering scheme of 1 to 32. Time slot 0 is identical to channel 1; time slot 1 is identical to channel 2; and so on. Each time slot (or channel) is made up of eight bits that are numbered 1 to 8.
DS21Q50 Figure 1-1.
DS21Q50 2. PIN DESCRIPTION Table 2-1.
DS21Q50 NAME PIN 60 35 10 85 95 75 72 67 42 17 92 63 38 13 88 64 39 14 89 66 41 16 91 93 68 43 18 90 65 40 15 62 37 12 87 80 55 30 5 79 54 29 4 99 100 81 PARALLEL PORT ENABLED OUTB1 OUTB2 OUTB3 OUTB4 PBTS RD (DS) REFCLK RRING1 RRING2 RRING3 RRING4 RSER1 RSER2 RSER3 RSER4 RSYNC1 RSYNC2 RSYNC3 RSYNC4 RTIP1 RTIP2 RTIP3 RTIP4 RVDD1 RVDD2 RVDD3 RVDD4 RVSS1 RVSS2 RVSS3 RVSS4 SYSCLK1 SYSCLK2 SYSCLK3 SYSCLK4 TCLK1 TCLK2 TCLK3 TCLK4 TRING1 TRING2 TRING3 TRING4 TS0 TS1 TSER1 SERIAL PORT ENABLED TYPE FUNCTION [Se
DS21Q50 NAME PIN 56 31 6 82 57 32 7 76 51 26 1 78 53 28 3 77 52 27 2 74 PARALLEL PORT ENABLED TSER2 TSER3 TSER4 TSYNC1 TSYNC2 TSYNC3 TSYNC4 TTIP1 TTIP2 TTIP3 TTIP4 TVDD1 TVDD2 TVDD3 TVDD4 TVSS1 TVSS2 TVSS3 TVSS4 WR (R/W) SERIAL PORT ENABLED TYPE FUNCTION [Serial Port Mode in Brackets] I I I I/O I/O I/O I/O O O O O — — — — — — — — I Transmit Serial Data Transmit Serial Data Transmit Serial Data Transmit Sync Transmit Sync Transmit Sync Transmit Sync Transmit Analog Tip Output Transmit Analog Tip Outpu
DS21Q50 Table 2-2.
DS21Q50 NAME PIN PARALLEL PORT ENABLED SERIAL PORT ENABLED TYPE 45 A0 ICES I 46 A1 OCES I 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 A2 A3 A4 ALE (AS)/A5 TTIP2 TVSS2 TVDD2 TRING2 TCLK2 TSER2 TSYNC2 DVSS2 DVDD2 OUTB1 OUTA1 SYSCLK1 RSER1 RSYNC1 RVSS2 RTIP1 RRING1 RVDD2 AJACKO AJACKI 4/8/16MCK REFCLK MCLK WR (R/W) RD (DS) TTIP1 TVSS1 TVDD1 TRING1 TCLK1 TSER1 TSYNC1 DVSS1 DVDD1 OUTB4 OUTA4 SDI SCLK I I I I O — — O I I I
DS21Q50 NAME PIN PARALLEL PORT ENABLED 87 88 89 90 91 92 93 94 95 96 97 98 99 100 — — — — SYSCLK4 RSER4 RSYNC4 RVSS1 RTIP4 RRING4 RVDD1 INT PBTS BTS0 BTS1 CS TS0 TS1 EQVSS1 EQVSS2 EQVSS3 EQVSS4 SERIAL PORT ENABLED TYPE I O I/O – I I — O I I I I — — — — Note: EQVSS lines are tied to RVSS lines in the 100-pin LQFP package.
DS21Q50 2.1 Pin Function Description 2.1.1 System (Backplane) Interface Pins Signal Name: TCLK Signal Description: Transmit Clock Signal Type: Input A 2.048MHz primary clock. Used to clock data through the transmit formatter. Signal Name: TSER Signal Description: Transmit Serial Data Signal Type: Input Transmit NRZ serial data. Sampled on the falling edge of TCLK when IBO disabled. Sampled on the falling edge of SYSCLK when the IBO function is enabled.
DS21Q50 2.1.2 Alternate Jitter Attenuator Signal Name: AJACKI Signal Description: Alternate Jitter Attenuator Clock Input Signal Type: Input Clock input to alternate jitter attenuator. Signal Name: AJACKO Signal Description: Alternate Jitter Attenuator Clock Output Signal Type: Output Clock output of alternate jitter attenuator. 2.1.3 Clock Synthesizer Signal Name: 4/8/16MCK Signal Description: 4.096MHz/8.192MHz/16.384MHz Clock Output Signal Type: Output A 4.096MHz, 8.192MHz, or 16.
DS21Q50 Signal Name: PBTS Signal Description: Parallel Bus Type Select Signal Type: Input Used to select between Motorola and Intel parallel bus types. Signal Name: Signal Description: AD0 to AD7/SDO Data Bus or Address/Data Bus [D0 to D6] Data Bus or Address/Data Bus [D7]/Serial Port Output Signal Type: Input/Output In nonmultiplexed bus operation (MUX = 0), serves as the data bus. In multiplexed bus operation (MUX = 1), serves as an 8-bit multiplexed address/data bus.
DS21Q50 Signal Name: ICES Signal Description: Input Clock Edge Select Signal Type: Input Used to select which SCLK clock edge samples data at SDI. Signal Name: OCES Signal Description: Output Clock Edge Select Signal Type: Input Used to select which SCLK clock edge updates data at SDO. Signal Name: SCLK Signal Description: Serial Port Clock Signal Type: Input Used to clock data into and out of the serial port. 2.1.
DS21Q50 Signal Name: DVSS Signal Description: Digital Signal Ground Signal Type: Supply 0V. Should be tied to the RVSS and TVSS pins. Signal Name: RVSS Signal Description: Receive Analog Signal Ground Signal Type: Supply 0V. Should be tied to DVSS and TVSS. Signal Name: EQVSS Signal Description: Receiver Equalizer Analog Signal Ground Signal Type: Supply 0V. Should be tied to DVSS and TVSS. Not accessible in the 100-pin LQFP package.
DS21Q50 3. HOST INTERFACE PORT The DS21Q50 is controlled either through a nonmultiplexed bus, a multiplexed bus, or serial interface bus by an external microcontroller or microprocessor. The device can operate with either Intel or Motorola bus timing configurations. See Table 3-1 for a description of the bus configurations. All Motorola bus signals are listed in parentheses (). See Functional Timing Diagrams in Section 19 for more details. Table 3-1.
DS21Q50 Figure 3-1. Serial Port Operation Mode 1 ICES = 1 (SAMPLE SDI ON THE FALLING EDGE OF SCLK) OCES = 1 (UPDATE SDO ON RISING EDGE OF SCLK) SCLK 1 2 3 4 5 6 7 A0 A1 A2 A3 A4 A5 8 9 10 11 12 13 14 15 16 D0 D1 D2 D3 D4 D5 D6 D7 CS SDI R/W (lsb) B (msb) SDO (lsb) (msb) Figure 3-2.
DS21Q50 Figure 3-3. Serial Port Operation Mode 3 ICES = 0 (SAMPLE SDI ON THE RISING EDGE OF SCLK) OCES = 0 (UPDATE SDO ON FALLING EDGE OF SCLK) SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CS SDI A0 R/W A1 A2 A3 A4 B A5 (lsb) (msb) SDO D1 D0 D2 D3 D4 D5 D6 D7 (msb) (lsb) Figure 3-4.
DS21Q50 3.3 Register Map Table 3-2.
DS21Q50 ADDRESS R/W NAME 2C 2D 2E 2F R/W R/W R/W R/W PCLB2 PCLB3 PCLB4 TEST1 (set to 00h) FUNCTION Per-Channel Loopback Control 2 Per-Channel Loopback Control 3 Per-Channel Loopback Control 4 Test 1 (Note 2) Note 1: The device ID register and the system clock interface control register exist in Transceiver 1 only. (TS0, TS1 = 0). Note 2: Only the factory uses the test registers; these registers must be cleared (set to all zeros) on power-up initialization to ensure proper operation. 4.
DS21Q50 4.1 Power-Up Sequence On power-up and after the supplies are stable, the DS21Q50 should be configured for operation by writing to all of the internal registers (this includes setting the test registers to 00h) since the contents of the internal registers cannot be predicted on power-up. The LIRST (CCR5.4) should be toggled from 0 to 1 to reset the line interface circuitry (it takes the device about 40ms to recover from the LIRST bit being toggled).
DS21Q50 Table 4-1. Sync/Resync Criteria FRAME OR MULTIFRAME LEVEL SYNC CRITERIA FAS FAS present in frame N and N + 2, and FAS not present in frame N + 1 Two valid MF alignment words found within 8ms Valid MF alignment word found and previous time slot 16 contains code other than all zeros CRC4 CAS Register Name: Register Description: Register Address: Bit Name NAME 7 IFSS BIT IFSS 7 TFPT 6 AEBE 5 TUA1 4 TSiS 3 TSA1 2 TSM 1 TSIO 0 RESYNC CRITERIA ITU SPEC.
DS21Q50 Register Name: Register Description: Register Address: Bit Name 7 FLB CCR1 Common Control Register 1 12 Hex 6 THDB3 NAME BIT FLB 7 THDB3 6 TIBE 5 TCRC4 4 RSMS 3 RHDB3 2 PCLMS 1 RCRC4 0 5 TIBE 4 TCRC4 3 RSMS 2 RHDB3 1 PCLMS 0 RCRC4 FUNCTION Framer Loopback. See Section 4.2 for details. 0 = loopback disabled 1 = loopback enabled Transmit HDB3 Enable 0 = HDB3 disabled 1 = HDB3 enabled Transmit Insert Bit Error.
DS21Q50 4.2 Framer Loopback When CCR1.7 is set to 1, the DS21Q50 enters a framer loopback (FLB) mode (Figure 1-1). This loopback is useful in testing and debugging applications. In FLB, the SCT loops data from the transmitter back to the receiver. When FLB is enabled, the following occurs: 1) Data is transmitted as normal at TTIP and TRING. 2) The RCLK output is replaced with the TCLK input.
DS21Q50 4.3 Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is enabled (CCR2.5 = 1), the device monitors the receive framer to determine if any of the following conditions are present: loss of receive frame synchronization, AIS alarm (all ones) reception, or loss-of-receive carrier (or signal). If any one (or more) of the above conditions is present, then the framer forces an AIS alarm.
DS21Q50 4.4 Remote Loopback When CCR4.7 is set to 1, the DS21Q50 is forced into remote loopback (RLB). In this loopback, data input through the RTIP and RRING pins is transmitted back to the TTIP and TRING pins. Data continues to pass through the receive framer of the DS21Q50 as it would normally and the data from the transmit formatter is ignored (Figure 1-1). 4.5 Local Loopback When CCR4.6 is set to 1, the DS21Q50 is forced into local loopback (LLB).
DS21Q50 Register Name: Register Description: Register Address: Bit Name 7 LIUODO NAME CCR5 Common Control Register 5 16 Hex 6 CDIG 5 LIUSI 4 IRTSEL 3 TPRBS1 BIT LIUODO 7 CDIG 6 LIUSI 5 IRTSEL 4 TPRBS1 TPRBS0 RPRBS1 RPRBS0 3 2 1 0 2 TPRBS0 1 RPRBS1 0 RPRBS0 FUNCTION Line Interface Open-Drain Option. This control bit determines whether the TTIP and TRING outputs are open drain or not.
DS21Q50 5. STATUS AND INFORMATION REGISTERS A set of four registers—status register 1 (SR1), status register 2 (SR2), receive information register (RIR), and synchronizer status register (SSR)—contains information about the DS21Q50 framer’s real-time status When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers sets to 1. The bits in the SR1, SR2, and RIR1 registers operate in a latched fashion. The SSR contents are not latched.
DS21Q50 Register Name: Register Description: Register Address: Bit Name 7 RGM1 RIR Receive Information Register 08 Hex 6 RGM0 5 JALT 4 RESF 3 RESE 2 CRCRC 1 FASRC 0 CASRC NAME BIT FUNCTION RGM1 7 Receive Gain Monitor Bit 1. See the Level Indication table below for level indication. RGM0 6 Receive Gain Monitor Bit 0. See the Level Indication table below for level indication. JALT 5 RESF 4 RESE 3 CRCRC 2 CRC Resync Criteria Met. Set when 915/1000 codewords are received in error.
DS21Q50 Register Name: Register Description: Register Address: Bit Name 7 CSC5 SSR Synchronizer Status Register 09 Hex 6 CSC4 5 CSC3 4 CSC2 3 CSC0 2 FASSA 1 CASSA 0 CRC4SA NAME BIT FUNCTION CSC5 7 CRC4 Sync Counter Bit 5. MSB of the 6-bit counter. CSC4 6 CRC4 Sync Counter Bit 4 CSC3 5 CRC4 Sync Counter Bit 3 CSC2 4 CRC4 Sync Counter Bit 2 CSC0 3 CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. Counter Bit 1 is not accessible. FASSA 2 CASSA 1 CRC4SA 0 FAS Sync Active.
DS21Q50 Register Name: Register Description: Register Address: Bit Name 7 RSA1 NAME BIT RSA1 7 RDMA 6 RSA0 5 RSLIP 4 RUA1 3 RRA 2 RCL 1 RLOS 0 SR1 Status Register 1 0A Hex 6 RDMA 5 RSA0 4 RSLIP 3 RUA1 2 RRA 1 RCL 0 RLOS FUNCTION Receive Signaling All Ones. Set when the contents of time slot 16 contain fewer than three 0s over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode. RSA1 and RSA0 are set if a change in signaling is detected.
DS21Q50 Register Name: Register Description: Register Address: Bit Name 7 RSA1 NAME BIT RSA1 7 RDMA 6 RSA0 5 RSLIP 4 RUA1 3 RRA 2 RCL 1 RLOS 0 IMR1 Interrupt Mask Register 1 18 Hex 6 RDMA 5 RSA0 4 RSLIP 3 RUA1 FUNCTION Receive Signaling All Ones 0 = interrupt masked 1 = interrupt enabled Receive Distant MF Alarm 0 = interrupt masked 1 = interrupt enabled Receive Signaling All Zeros 0 = interrupt masked 1 = interrupt enabled Receive Elastic Store Slip Occurrence 0 = interrupt masked
DS21Q50 Register Name: Register Description: Register Address: Bit Name 7 RMF SR2 Status Register 2 0B Hex 6 RAF NAME BIT RMF 7 RAF 6 TMF 5 SEC 4 TAF 3 LOTC 2 RCMF 1 PRBSD 0 5 TMF 4 SEC 3 TAF 2 LOTC 1 RCMF 0 PRBSD FUNCTION Receive CAS Multiframe. Set every 2ms (regardless if CAS signaling is enabled or not) on receive multiframe boundaries. Receive Align Frame. Set every 250µs at the beginning of align frames.
DS21Q50 Register Name: Register Description: Register Address: Bit Name 7 RMF IMR2 Interrupt Mask Register 2 19 Hex 6 RAF NAME BIT RMF 7 RAF 6 TMF 5 SEC 4 TAF 3 LOTC 2 RCMF 1 PRBSD 0 5 TMF 4 SEC 3 TAF FUNCTION Receive CAS Multiframe 0 = interrupt masked 1 = interrupt enabled Receive Align Frame 0 = interrupt masked 1 = interrupt enabled Transmit Multiframe 0 = interrupt masked 1 = interrupt enabled One-Second Timer 0 = interrupt masked 1 = interrupt enabled Transmit Align Frame 0 =
DS21Q50 6. ERROR COUNT REGISTERS A set of four counters in each transceiver of the DS21Q50 record bipolar (BPV) or code violations (CV), errors in the CRC4 SMF codewords, E bits as reported by the far end, and word errors in the FAS. The Ebit counter is reconfigured for counting errors in the PRBS pattern if receive PRBS is enabled. Each of these four counters is automatically updated on either one-second boundaries (CCR2.70 = 0) or every 62.5ms (CCR2.
DS21Q50 6.2 CRC4 Error Counter CRC4 count register 1 (CRCCR1) is the most significant word and CRCCR2 is the least significant word of a 16-bit counter that records word errors in the cyclic redundancy check 4 (CRC4). Since the maximum CRC4 count in a one-second period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC4 level; it continues to count if loss-of-multiframe sync occurs at the CAS level. CRCCR1 and CRCCR2 have alternate functions.
DS21Q50 6.4 FAS Error Counter FAS count register 1 (FASCR1) is the most significant word and FASCR2 is the least significant word of a 16-bit counter that records word errors in the frame alignment signal (FAS) in time slot 0. This counter is disabled when RLOS is high. FAS errors are not counted when the framer is searching for FAS alignment and/or synchronization at either the CAS or CRC4 multiframe level. Since the maximum FASword error count in a one-second period is 4000, this counter cannot saturate.
DS21Q50 7. DS0 MONITORING FUNCTION Each DS21Q50 framer can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR3 register. In the receive direction, the RCM0–RCM4 bits in the CCR4 register need to be properly set.
DS21Q50 Register Name: Register Description: Register Address: Bit Name 7 B1 TDS0M Transmit Ds0 Monitor Register 22 Hex 6 B2 5 B3 4 B4 3 B5 2 B6 1 B7 0 B8 NAME BIT B1 7 B2 6 Transmit DS0 Channel Bit 1. MSB of the DS0 channel (first bit to be transmitted). Transmit DS0 Channel Bit 2 B3 5 Transmit DS0 Channel Bit 3 B4 4 Transmit DS0 Channel Bit 4 B5 3 Transmit DS0 Channel Bit 5 B6 2 Transmit DS0 Channel Bit 6 B7 1 B8 0 Transmit DS0 Channel Bit 7 Transmit DS0 Channel Bit 8.
DS21Q50 Register Name: Register Description: Register Address: Bit Name 7 B1 RDS0M Receive Ds0 Monitor Register 2A Hex 6 B2 5 B3 4 B4 3 B5 2 B6 1 B7 0 B8 NAME BIT FUNCTION B1 7 Receive DS0 Channel Bit 1. MSB of the DS0 channel (first bit received). B2 6 Receive DS0 Channel Bit 2 B3 5 Receive DS0 Channel Bit 3 B4 4 Receive DS0 Channel Bit 4 B5 3 Receive DS0 Channel Bit 5 B6 2 Receive DS0 Channel Bit 6 B7 1 Receive DS0 Channel Bit 7 B8 0 Receive DS0 Channel Bit 8.
DS21Q50 8. PRBS GENERATION AND DETECTION The DS21Q50 can transmit and receive the 215 - 1 PRBS pattern. This PRBS pattern complies with ITUT O.151 specifications. The PRBS pattern can be unframed (in all 256 bits of the frame), framed (in all time slots except TS0), or in any single time slot. Register CCR5 contains the control bits for configuring the transmit and receive PRBS functions. Table 8-1 and Table 8-2 show the selection criteria for transmit and receive operation modes.
DS21Q50 9. SYSTEM CLOCK INTERFACE A single system clock interface (SCI) is common to the four DS21Q50 transceivers. The SCI allows any one of the four receivers to act as the master reference clock for the system. When multiple DS21Q50s are used to build an N port system, the SCI allows any one of the N ports to be the master. The selected reference is then distributed to the other DS21Q50s through the REFCLK pin.
DS21Q50 Table 9-1. Master Port Selection SCS2 SCS1 SCS0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 PORT SELECTED AS MASTER None (Master Port can be derived from another DS21Q50 in the system.) Transceiver 1 Transceiver 2 Transceiver 3 Transceiver 4 Reserved for future use Reserved for future use Reserved for future use Table 9-2. Synthesizer Output Select CSS1 CSS0 0 0 1 1 0 1 0 1 10. SYNTHESIZER OUTPUT FREQUENCY (MHz) 2.048 4.096 8.192 16.
DS21Q50 11. IDLE CODE INSERTION The transmit idle registers (TIR1/2/3/4) determine which of the 32 E1 channels should be overwritten with the code placed in the transmit idle-definition register (TIDR). This allows the same 8-bit code to be placed into any of the 32 E1 channels. Each of the bit positions in the TIRs represents a DS0 channel in the outgoing frame. When these bits are set to 1, the corresponding channel transmits the idle code contained in the TIDR.
DS21Q50 12. PER-CHANNEL LOOPBACK The DS21Q50 has per-channel loopback capability that can operate in one of two modes: remote perchannel loopback or local per-channel loopback. PCLB1/2/3/4 are used for both modes to determine which channels are looped back. In remote per-channel loopback mode, PCLB1/2/3/4 determine which channels (if any) in the transmit direction should be replaced with the data from the receiver or, rather, off the E1 line.
DS21Q50 14. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION On the receiver, the RAF and RNAF registers always report the data as it is received in the additional (Sa) and international (Si) bit locations. The RAF and RNAF registers are updated with the setting of the receive align frame bit in status register 2 (SR2.6). The host can use the SR2.6 bit to know when to read the RAF and RNAF registers. It has 250ms to retrieve the data before it is lost.
DS21Q50 Register Name: Register Description: Register Address: Bit Name 7 Si RNAF Receive Nonalign Frame Register 29 Hex 6 1 5 A 4 Sa4 3 Sa5 NAME BIT Si 7 International Bit 1 6 Frame Nonalignment Signal Bit A 5 Remote Alarm Sa4 4 Additional Bit 4 Sa5 3 Additional Bit 5 Sa6 2 Additional Bit 6 Sa7 1 Additional Bit 7 Sa8 0 Additional Bit 8 Register Name: Register Description: Register Address: 2 Sa6 1 Sa7 0 Sa8 1 1 0 1 FUNCTION TAF Transmit Align Frame Register 20 Hex (
DS21Q50 Register Name: Register Description: Register Address: TNAF Transmit Nonalign Frame Register 21 Hex (Bit 6 must be programmed to 1; the DS21Q50 does not automatically set this bit.) Bit Name 7 Si 6 1 5 A 4 Sa4 3 Sa5 2 Sa6 NAME BIT FUNCTION Si 7 International Bit 1 6 Frame Nonalignment Signal Bit. Set this bit = 1.
DS21Q50 15. USER-CONFIGURABLE OUTPUTS There are two user-configurable output pins for each transceiver, OUTA and OUTB. These pins can be programmed to output various clocks, alarms for line monitoring, logic 0 and 1 levels to control external circuitry, or access transmit data between the framer and transmit line interface unit. OUTA and OUTB can be active low or active high when operating as clock and alarm outputs. OUTA is active high if OUTAC.4 =1 and active low if OUTAC.3 = 0.
DS21Q50 Register Name: Register Description: Register Address: Bit Name 7 NRZE NAME OUTBC OUTB Control Register 1B Hex 6 — 5 — 4 OB4 3 OB3 2 OB2 1 OB1 0 OB0 BIT FUNCTION NRZE 7 NRZ Enable. When this bit is set, the receiver can accept TTL-type NRZ data at the RTIP input. RRING becomes a clock input. 0 = RTIP and RRING are in normal mode 1 = RTIP becomes an NRZ TTL type input and RRING is its associated clock input. Data at RTIP is clocked in on the falling edge of the clock present on RRING.
DS21Q50 Table 15-1. OUTA and OUTB Function Select OA3 OB3 OA2 OB2 OA1 OB1 OA0 OB0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 FUNCTION External Hardware Control Bit. In this mode, OUTA and OUTB can be used as simple control pins for external circuitry. Use OA4 and OB4 to toggle OUTA and OUTB. Receive Recovered Clock, RCLK Receive Loss-of-Sync Indicator.
DS21Q50 16. LINE INTERFACE UNIT The line interface unit in the DS21Q50 contains three sections: the receiver, which handles clock and data recovery; the transmitter, which waveshapes and drives the E1 line; and the jitter attenuator. The line interface control register (LICR), described below, controls each of these three sections.
DS21Q50 16.2 Termination The DS21Q50 is designed to be fully software-selectable for 75W and 120W termination without the need to change any external resistors. The user can configure the DS21Q50 for 75W or 120W receive termination by setting the IRTSEL (CCR5.4) bit. When using the internal termination feature, the external termination resistance should be 120W (typically two 60W resistors).
DS21Q50 Register Name: Register Description: Register Address: Bit Name NAME — MM2 7 0 RMM Receive Monitor Mode Register 1F Hex 6 MM1 BIT 7 6 MM1 5 MM0 4 — — — — 3 2 1 0 5 MM1 4 MM0 3 0 2 0 FUNCTION Reserved. Must be set = 0 for proper operation Monitor Mode 2. Sets the internal linear gain boost (dB) for monitor mode applications. Please refer to the table below for proper settings. Monitor Mode 1. Sets the internal linear gain boost (dB) for monitor mode applications.
DS21Q50 16.4 Transmit Waveshaping and Line Driving The DS21Q50 uses a set of laser-trimmed delay lines with a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the E1 line. The waveforms meet the ITU G.703 specifications (Figure 16-4). The user selects which waveform is to be generated by properly programming the L2/L1/L0 bits in the LICR. The DS21Q50 can be set up in a number of various configurations, depending on the application (Table 16-3). Table 16-3.
DS21Q50 Figure 16-2. External Analog Connections (Basic Configuration) 0.47mF 1/4 DS21Q50 +3.3V (NONPOLARIZED) E1 TRANSMIT LINE 0.1mF TTIP DVDD TRING DVSS 2:1 0.01mF RVDD 1:1 0.1mF RVSS E1 RECEIVE LINE RTIP TVDD Rr Rr 0.1mF TVSS RRING 2.048MHz MCLK 0.1mF Figure 16-3. External Analog Connections (Protected Interface) +VDD Fuse D2 D1 2:1 +VDD TTIP1 TRANSMIT LINE 0.
DS21Q50 Figure 16-4. Transmit Waveform Template 1.2 1.1 269ns SCALED AMPLITUDE (in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 1.0 0.9 0.8 0.7 G.703 Template 194ns 0.6 0.5 219ns 0.4 0.3 0.2 0.1 0 -0.1 -0.
DS21Q50 16.5 Jitter Attenuators The DS21Q50 contains an on-board clock and data jitter attenuator for each transceiver and a single, undedicated “clock only” jitter attenuator. Figure 1-1 shows this undedicated jitter attenuator as the alternate jitter attenuator. Clock and Data Jitter Attenuators The clock and data jitter attenuators can be mapped into the receive or transmit paths and can be set to buffer depths of either 32 or 128 bits through the LICR.
DS21Q50 Figure 16-5. Jitter Tolerance UNIT INTERVALS (UIpp) 1K Ds21Q50 Tolerance 100 40 10 1.5 1 0.1 Minimum Tolerance Level as per ITU G.823 1 10 20 0.2 100 1K FREQUENCY (Hz) 2.4K 10K 18K 100K Figure 16-6. Jitter Attenuation ITU G.
DS21Q50 17. CMI (CODE MARK INVERSION) The DS21Q50 provides a CMI interface for connection to optical transports. This interface is a unipolar 1T2B-coded signal. Ones are alternately encoded as a logical 1 or 0 level for the full duration of the clock period. Zeros are encoded as a 0-to-1 transition at the middle of the clock period. Figure 17-1 shows an example data pattern and its CMI result. The control bit for enabling CMI is in the OUTAC register as shown below.
DS21Q50 Transmit and receive CMI is enabled through OUTAC.7. When this register bit is set, the TTIP pin outputs CMI-coded data at normal TTL-type levels. This signal can be used to directly drive an optical interface. When CMI is enabled, the user can also use HDB3 coding. When this register bit is set, the RTIP pin becomes a unipolar CMI input. The CMI signal is processed to extract and align the clock with data. The BPV counts CVs (code violations) in the CMI signal.
DS21Q50 18. INTERLEAVED PCM BUS OPERATION In many architectures, the PCM outputs of individual framers are combined into higher speed PCM buses to simplify transport across the system backplane. The DS21Q50 can be configured to allow PCM data buses to be multiplexed into higher speed data buses, eliminating external hardware, saving board space and cost. The DS21Q50 uses a channel interleave method. See Figure 19-4 and Figure 19-7 for details about the channel interleave.
DS21Q50 Table 18-2. IBO System Clock Select SCS1 0 0 1 1 SCS0 0 1 0 1 FUNCTION 2.048MHz, Single device on bus 4.096MHz, Two devices on bus 8.192MHz, Four devices on bus 16.384MHz, Eight devices on bus Figure 18-1. IBO Configuration Using Two DS21Q50 Transceivers (Eight E1 Lines) Note: See Section 16 for details about the line interface circuit.
DS21Q50 19. FUNCTIONAL TIMING DIAGRAMS 19.1 Receive Timing Diagrams Figure 19-1. Receive Frame and Multiframe Timing FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RSYNC 1 RSYNC 2 NOTE 1: RSYNC IN FRAME/OUTPUT MODE (RCR.6 = 0). NOTE 2: RSYNC IN MULTIFRAME/OUTPUT MODE (RCR.6 = 1). NOTE 3: THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME. Figure 19-2.
DS21Q50 Figure 19-3. Receive Boundary Timing (With Elastic Store Enabled) SYSCLK CHANNEL 31 CHANNEL 32 RSER CHANNEL 1 LSB MSB LSB MSB RSYNC1 RSYNC 2 NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR.5 = 0). NOTE 2: RSYNC IS IN THE INPUT MODE (RCR.5 = 1). Figure 19-4.
DS21Q50 19.2 Transmit Timing Diagrams Figure 19-5. Transmit Frame and Multiframe Timing FRAME# 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 1 TSYNC TSYNC 2 NOTE 1: TSYNC IN FRAME MODE (TCR.1 = 0). NOTE 2: TSYNC IN MULTIFRAME MODE (TCR.1 = 1). Figure 19-6. Transmit Boundary Timing TCLK CHANNEL 1 TSER LSB Si 1 A CHANNEL 2 Sa4 Sa5 Sa6 Sa7 Sa8 MSB TSYNC1 TSYNC2 NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR.0 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (TCR.0 = 0).
DS21Q50 Figure 19-7. Transmit Interleave Bus Operation TSYNC 1 TSER TSER2 FR1 CH32 FR0 CH1 FR2 CH32 FR3 CH32 FR0 CH1 FR1 CH1 FR1 CH1 FR2 CH1 FR3 CH1 FR0 CH2 FR0 CH2 FR1 CH2 FR1 CH2 FR2 CH2 FR3 CH2 BIT DETAIL SYSCLK 3 TSYNC FRAMER 3, CHANNEL 32 TSER FRAMER 1, CHANNEL 1 FRAMER 0, CHANNEL 1 LSB MSB LSB MSB NOTE 1: 4.096MHZ BUS CONFIGURATION. NOTE 2: 8.192MHZ BUS CONFIGURATION. NOTE 3: TSYNC IS IN THE INPUT MODE (TCR.0 = 0).
DS21Q50 Figure 19-8. Framer Synchronization Flowchart Power Up RLOS = 1 FAS Search FASSA = 1 RLOS = 1 FAS Sync Criteria Met FASSA = 0 Resync if RCR1.0 = 0 Increment CRC4 Sync Counter; CRC4SA = 0 8ms Time Out CRC4 Multiframe Search (if enabled via CCR1.0) CRC4SA = 1 CRC4 Sync Criteria Met; CRC4SA = 0; Reset CRC4 Sync Counter Set FASRC (RIR.1) CRC4 Resync Criteria Met (RIR.2) CAS Resync Criteria Met; Set CASRC (RIR.0) Check for FAS Framing Error (depends on RCR1.
DS21Q50 Figure 19-9. Transmit Data Flow TSER TAF TNAF.5-7 1 0 Timeslot 0 Pass-Through (TCR.6) 1 0 Si Bit Insertion Control (TCR.3) CRC4 Multiframe Alignment Word Generation (CCR.4) Receive Side CRC4 Error Detector 0 1 1 E-Bit Generation (TCR.5) Auto Remote Alarm Generation (CCR.4) TIDR 1 0 Idle Code / Channel Insertion Control via TIR1/2/3/4 0 Code Word Generation 1 CRC4 Enable (CCR.4) Transmit Unframed All Ones (TCR.4) or Auto AIS (CCR2.5) AMI or HDB3 Converter CCR.
DS21Q50 20. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground………………………………………………………………-1.0V to +6.0V Operating Temperature Range for DS21Q50L………………………………………………………………..0°C to +70°C Operating Temperature Range for DS21Q50LN……………………………………………………………-40°C to +85°C Storage Temperature Range………………………………………………………………………………...-55°C to +125°C Soldering Temperature………………………………………………………..
DS21Q50 21. AC TIMING PARAMETERS AND DIAGRAMS 21.1 Multiplexed Bus AC Characteristics AC CHARACTERISTICS—MULTIPLEXED PARALLEL PORT (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21Q50L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21Q50LN.
DS21Q50 Figure 21-1. Intel Bus Read AC Timing (PBTS = 0) t CYC ALE PWASH t ASD WR t ASD RD PWEL t ASED PWEH t CH t CS CS t ASL t DHR t DDR AD0–AD7 t AHL Figure 21-2.
DS21Q50 Figure 21-3.
DS21Q50 21.2 Nonmultiplexed Bus AC Characteristics AC CHARACTERISTICS—NONMULTIPLEXED PARALLEL PORT (VDD = 3.3V ± 5%, TA = 0°C to +70°C for DS21Q50L; VDD = 3.3V ± 5%, TA = -40°C to +85°C for DS21Q50N.
DS21Q50 Figure 21-4. Intel Bus Read Timing (PBTS = 0) A0–A7 Address Valid D0–D7 Data Valid t5 5ns (min)/20ns (max) WR t1 0ns (min) CS 0ns (min) t2 RD t3 t4 75ns (max) 0ns (min) Figure 21-5. Intel Bus Write Timing (PBTS = 0) A0–A7 Address Valid D0–D7 t7 10ns (min) 10ns (min) RD t1 CS 0ns (min) WR t8 0ns min.
DS21Q50 Figure 21-6. Motorola Bus Read Timing (PBTS = 1) A0–A7 Address Valid D0–D7 Data Valid 5ns (min)/20ns (max) t5 R/W t1 CS 0ns (min) 0ns (min) t2 t3 t4 0ns (min) 75ns (max) DS Figure 21-7.
DS21Q50 21.3 Serial Port AC CHARACTERISTICS—SERIAL PORT (BTS1 = 1, BTS0 = 0) (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21Q50L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21Q50N.
DS21Q50 21.4 Receive AC Characteristics AC CHARACTERISTICS—RECEIVER (VDD = 3.3.0V ±5%, TA = 0°C to +70°C for DS21Q50L; VDD = 3.3.0V ± 5%, TA = -40°C to +85°C for DS21Q50LN.
DS21Q50 Figure 21-10. Receive AC Timing (Receive Elastic Store Enabled) tR t SL tF t SH SYSCLK t SP t D3 MSB of Channel 1 RSER 1 t D4 RSYNC OUTA / OUTB 2 RSYNC 3 t HD t SU NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR.5 = 0). NOTE 2: OUTA OR OUTB CONFIGURED AS CRCR MF SYNC OR CAS MF SYNC. NOTE 3: RSYNC IS IN THE OUTPUT MODE (RCR.5 = 1).
DS21Q50 21.5 Transmit AC Characteristics AC CHARACTERISTICS—TRANSMIT (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21Q50L; VDD = 3.3V ± 5%, TA = -40°C to +85°C for DS21Q50LN.
DS21Q50 Figure 21-11. Transmit AC Timing (IBO Disabled) t CP t CH t CL tF tR TCLK SU TSER t D2 TSYNC1 t HD t SU TSYNC 2 t D2 OUTA/OUTB 3 NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR.0 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (TCR.0 = 0). NOTE 3: APPLIES TO OUTA AND OUTB WHEN CONFIGURES FOR TPOS AND TNEG OUTPUTS. Figure 21-12. Transmit AC Timing (IBO Enabled) t SP tR t SL tF t SH SYSCLK t SU TSER NOTE 1: TSER IS ONLY SAMPLED ON THE FALLING EDGE OF SYSCLK WHEN THE IBO MODE IS ENABLED.
DS21Q50 21.6 Special Modes AC Characteristics AC CHARACTERISTICS—SPECIAL MODES (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21Q50L; VDD = 3.3V ± 5%, TA = -40°C to +85°C for DS21Q50LN.) PARAMETER SYMBOL RTIP Period MIN TYP tCP MAX 488 UNITS ns RTIP Setup to RRING Falling tCH tCL tSU 75 75 20 ns ns ns TSER Hold from TCLK Falling tHD 20 ns RTIP Pulse Width RTIP, RRING Rise and Fall Times t R, t F 25 Special Mode: OUTBC.7 = 1 Note: RTIP and RRING become NRZ data and clock inputs.
DS21Q50 22. PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied.