DS21Q59 E1 Quad Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS21Q59 E1 quad transceiver contains all the necessary functions for connecting to four E1 lines. The DS21Q59 is a direct replacement for the DS21Q50, with the addition of signaling access and improved interrupt handling. It is composed of a line interface unit (LIU), framer, and a TDM backplane interface, and is controlled through an 8-bit parallel port configured for Intel or Motorola bus operations or serial port operation.
DS21Q59 Quad E1 Transceiver TABLE OF CONTENTS 1. ACRONYMS .......................................................................................................................6 2. DETAILED DESCRIPTION.................................................................................................6 3. BLOCK DIAGRAM .............................................................................................................7 4. PIN DESCRIPTION.........................................................
DS21Q59 Quad E1 Transceiver 17. PER-CHANNEL LOOPBACK ..........................................................................................42 18. ELASTIC STORE OPERATION .......................................................................................42 19. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION..................................43 20. USER-CONFIGURABLE OUTPUTS ................................................................................45 21. LINE INTERFACE UNIT ........
DS21Q59 Quad E1 Transceiver LIST OF FIGURES Figure 3-1. Block Diagram ....................................................................................................................... 7 Figure 6-1. Serial Port Operation Mode 1 ...............................................................................................14 Figure 6-2. Serial Port Operation Mode 2 ...............................................................................................15 Figure 6-3.
DS21Q59 Quad E1 Transceiver LIST OF TABLES Table 4-A. Pin Description (Sorted by Function) ...................................................................................... 8 Table 4-B. Pin Assignments (Sorted by Number) ...................................................................................10 Table 4-C. System (Backplane) Interface Pins .......................................................................................12 Table 4-D. Alternate Jitter Attenuator .........................
DS21Q59 Quad E1 Transceiver 1. ACRONYMS The following abbreviations are used throughout this data sheet: FAS CAS MF Si CRC4 CCS Sa E-Bit LOC TCLK RCLK Frame Alignment Signal Channel Associated Signaling Multiframe International Bits Cyclical Redundancy Check Common Channel Signaling Additional bits CRC4 Error Bits Loss of Clock This generally refers to the transmit rate clock and can reference an actual input signal to the device (TCLK) or an internally derived signal used for transmission.
DS21Q59 Quad E1 Transceiver 3. BLOCK DIAGRAM Figure 3-1.
DS21Q59 Quad E1 Transceiver 4. PIN DESCRIPTION Table 4-A.
DS21Q59 Quad E1 Transceiver NAME PIN 89 66 41 16 91 93 68 43 18 90 65 40 15 62 37 12 87 80 55 30 5 79 54 29 4 99 100 81 56 31 6 82 57 32 7 76 51 26 1 78 53 28 3 77 52 27 2 74 PARALLEL PORT ENABLED RSYNC4 RTIP1 RTIP2 RTIP3 RTIP4 RVDD1 RVDD2 RVDD3 RVDD4 RVSS1 RVSS2 RVSS3 RVSS4 SYSCLK1 SYSCLK2 SYSCLK3 SYSCLK4 TCLK1 TCLK2 TCLK3 TCLK4 TRING1 TRING2 TRING3 TRING4 TS0 TS1 TSER1 TSER2 TSER3 TSER4 TSYNC1 TSYNC2 TSYNC3 TSYNC4 TTIP1 TTIP2 TTIP3 TTIP4 TVDD1 TVDD2 TVDD3 TVDD4 TVSS1 TVSS2 TVSS3 TVSS4 WR (R/W) SERIAL PO
DS21Q59 Quad E1 Transceiver Table 4-B.
DS21Q59 Quad E1 Transceiver NAME PIN PARALLEL PORT ENABLED SERIAL PORT ENABLED TYPE 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 TCLK2 TSER2 TSYNC2 DVSS2 DVDD2 OUTB1 OUTA1 SYSCLK1 RSER1 RSYNC1 RVSS2 RTIP1 RRING1 RVDD2 AJACKO AJACKI 4/8/16MCK REFCLK MCLK WR (R/W) RD (DS) TTIP1 TVSS1 TVDD1 TRING1 TCLK1 TSER1 TSYNC1 DVSS1 DVDD1 OUTB4 OUTA4 SYSCLK4 RSER4 RSYNC4 RVSS1 RTIP4 RRING4 RVDD1 INT PBTS BTS0 BTS1 CS TS0 TS
DS21Q59 Quad E1 Transceiver 4.1 Pin Function Descriptions Table 4-C. System (Backplane) Interface Pins NAME TYPE TCLK I TSER I TSYNC I/O RSER O RSYNC I/O SYSCLK I OUTA O OUTB O FUNCTION Transmit Clock. TCLK is a 2.048MHz primary clock that is used to clock data through the transmit formatter. Transmit Serial Data. Transmit NRZ serial data. TSER is sampled on the falling edge of TCLK when IBO disabled. It is sampled on the falling edge of SYSCLK when the IBO function is enabled.
DS21Q59 Quad E1 Transceiver Table 4-G. Serial Port Control Pins NAME TYPE SDO O Serial Port Data Output. Data at this output can be updated on the rising or falling edge of SCLK. FUNCTION SDI ICES OCES SCLK I I I I Serial Port Data Input. Data at this input can be sampled on the rising or falling edge of SCLK. Input Clock-Edge Select. ICES is used to select which SCLK clock edge samples data at SDI. Output Clock-Edge Select. OCES is used to select which SCLK clock edge updates data at SDO.
DS21Q59 Quad E1 Transceiver 6. HOST INTERFACE PORT The DS21Q59 is controlled through either a nonmultiplexed bus, a multiplexed bus, or serial interface bus by an external microcontroller or microprocessor. The device can operate with either Intel or Motorola bus timing configurations. See Table 6-A for a description of the bus configurations. Motorola bus signals are listed in parentheses (). See the timing diagrams in the AC Electrical Characteristics in Section 26 for more details. Table 6-A.
DS21Q59 Quad E1 Transceiver Figure 6-2. Serial Port Operation Mode 2 ICES = 1 (SAMPLE SDI ON THE FALLING EDGE OF SCLK) OCES = 0 (UPDATE SDO ON THE FALLING EDGE OF SCLK) SCLK 1 2 3 4 5 6 7 8 A0 A1 A2 A3 A4 A5 9 10 11 12 13 14 15 16 CS SDI R/W B LSB MSB SDO D0 D1 D2 D3 D4 D5 D6 D7 LSB MSB Figure 6-3.
DS21Q59 Quad E1 Transceiver 7. REGISTER MAP Table 7-A.
DS21Q59 Quad E1 Transceiver ADDRESS 37 38 39 3A 3B 3C 3D 3E 3F R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W NAME SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 FUNCTION Signaling Access Register 8 Signaling Access Register 9 Signaling Access Register 10 Signaling Access Register 11 Signaling Access Register 12 Signaling Access Register 13 Signaling Access Register 14 Signaling Access Register 15 Signaling Access Register 16 Note 1: The device ID register and the system clock-interface control register exist in T
DS21Q59 Quad E1 Transceiver 8.1 Power-Up Sequence On power-up and after the supplies are stable, the DS21Q59 should be configured for operation by writing to all the internal registers (this includes setting the test register to 00h) since the contents of the internal registers cannot be predicted on power-up. The LIRST (CCR5.4) should be toggled from 0 to 1 to reset the line interface circuitry. (It takes the device about 40ms to recover from the LIRST bit being toggled.
DS21Q59 Quad E1 Transceiver Table 8-A. Sync/Resync Criteria FRAME OR MULTIFRAME LEVEL FAS CRC4 CAS SYNC CRITERIA FAS present in frame N and N + 2, and FAS not present in frame N + 1 Two valid MF alignment words found within 8ms Valid MF alignment word found and previous time slot 16 contains code other than all zeros Register Name: Register Description: Register Address: Bit # Name RESYNC CRITERIA 7 IFSS NAME BIT IFSS 7 TFPT 6 AEBE 5 TUA1 4 TSiS 3 TSA1 2 TSM 1 TSIO 0 ITU SPEC.
DS21Q59 Quad E1 Transceiver Register Name: Register Description: Register Address: Bit # Name 7 FLB CCR1 Common Control Register 1 12 Hex 6 THDB3 NAME BIT FLB 7 THDB3 6 TIBE 5 TCRC4 4 RSMS 3 RHDB3 2 PCLMS 1 RCRC4 0 5 TIBE 4 TCRC4 3 RSMS 2 RHDB3 1 PCLMS 0 RCRC4 FUNCTION Framer Loopback. See Section 8.2 for details. 0 = loopback disabled 1 = loopback enabled Transmit HDB3 Enable 0 = HDB3 disabled 1 = HDB3 enabled Transmit Insert Bit Error.
DS21Q59 Quad E1 Transceiver 8.2 Framer Loopback When CCR1.7 is set to 1, the DS21Q59 enters a framer loopback (FLB) mode (Figure 3-1). This loopback is useful in testing and debugging applications. In FLB mode, the SCT loops data from the transmitter back to the receiver. When FLB is enabled, the following occurs: 1) Data is transmitted as normal at TPOSO and TNEGO. 2) Data input through RPOSI and RNEGI is ignored. 3) The RCLK output is replaced with the TCLK input.
DS21Q59 Quad E1 Transceiver 8.3 Automatic Alarm Generation The device can be programmed to automatically transmit AIS or remote alarm. When automatic AIS generation is enabled (CCR2.5 = 1), the device monitors the receive framer to determine if any of the following conditions are present: loss-of-receive frame synchronization, AIS alarm (all ones) reception, or loss-of-receive carrier (or signal). If one (or more) of these conditions is present, the framer forces an AIS alarm.
DS21Q59 Quad E1 Transceiver 8.5 Local Loopback When CCR4.6 is set to 1, the DS21Q59 is forced into local loopback (LLB) mode. In this loopback, data continues to be transmitted as normal. Data being received at RTIP and RRING is replaced with the data being transmitted. Data in this loopback passes through the jitter attenuator (Figure 3-1).
DS21Q59 Quad E1 Transceiver CCR5 Common Control Register 5 16 Hex Register Name: Register Description: Register Address: Bit # Name 7 LIUODO NAME BIT LIUODO 7 CDIG 6 LIUSI 5 IRTSEL 4 TPRBS1 TPRBS0 RPRBS1 RPRBS0 3 2 1 0 6 CDIG 5 LIUSI 4 IRTSEL 3 TPRBS1 2 TPRBS0 1 RPRBS1 0 RPRBS0 FUNCTION Line Interface Open-Drain Option. This control bit determines whether or not the TTIP and TRING outputs are open drain.
DS21Q59 Quad E1 Transceiver Register Name: Register Description: Register Address: Bit # Name 7 OTM1 CCR6 Common Control Register 6 2F Hex 6 OTM0 5 SRAS 4 LTC/SC 3 T16S 2 — 1 — 0 RESET NAME OTM1 OTM0 BIT 7 6 SRAS 5 LTC/SC 4 T16S 3 — 2 FUNCTION Output Test Mode 1 (Table 8-C) Output Test Mode 0 (Table 8-C) Signaling Read Access Select. This bit controls the function of registers SA1 through SA16 when reading.
DS21Q59 Quad E1 Transceiver Register Name: Register Description: Register Address: Bit: Name: 7 — CCR7 Common Control Register 7 1F Hex 6 — NAME — — — — BIT 7 6 5 4 136S 3 ALB 2 — 1 TG703 0 5 — 4 — 3 136S 2 ALB 1 — 0 TG703 FUNCTION Unused. Should be set = 0 for proper operation. Unused. Should be set = 0 for proper operation. Unused. Should be set = 0 for proper operation. Unused. Should be set = 0 for proper operation. 1:1.36 Transformer Select 0 = 1:2 transmit transformer 1 = 1:1.
DS21Q59 Quad E1 Transceiver 9. STATUS AND INFORMATION REGISTERS The DS21Q59 has a set of four registers that contain information about a framer’s real-time status. The registers include status register 1 (SR1), status register 2 (SR2), receive information register (RIR), and synchronizer status register (SSR). When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers is set to 1. All the bits in the SR1, SR2, and RIR1 registers operate in a latched fashion.
DS21Q59 Quad E1 Transceiver 9.1 Interrupt Handling The host can quickly determine which status registers in the four ports are causing an interrupt by reading one of the unused addresses such as 0Ch, 0Dh, or 0Eh in any port.
DS21Q59 Quad E1 Transceiver Register Name: Register Description: Register Address: Bit # Name 7 CSC5 NAME CSC5 CSC4 CSC3 CSC2 BIT 7 6 5 4 CSC0 3 FASSA 2 CASSA 1 CRC4SA 0 9.2 SSR Synchronizer Status Register 09 Hex 6 CSC4 5 CSC3 4 CSC2 3 CSC0 2 FASSA 1 CASSA 0 CRC4SA FUNCTION CRC4 Sync Counter Bit 5. MSB of the 6-bit counter. CRC4 Sync Counter Bit 4 CRC4 Sync Counter Bit 3 CRC4 Sync Counter Bit 2 CRC4 Sync Counter Bit 0. LSB of the 6-bit counter. Counter bit 1 is not accessible.
DS21Q59 Quad E1 Transceiver Register Name: Register Description: Register Address: Bit # Name 7 RSA1 NAME BIT RSA1 7 RDMA 6 RSA0 5 RSLIP 4 RUA1 3 RRA 2 RCL 1 RLOS 0 SR1 Status Register 1 0A Hex 6 RDMA 5 RSA0 4 RSLIP 3 RUA1 2 RRA 1 RCL 0 RLOS FUNCTION Receive Signaling All Ones. Set when the contents of time slot 16 contains fewer than three zeros over 16 consecutive frames. This alarm is not disabled in the CCS signaling mode.
DS21Q59 Quad E1 Transceiver Register Name: Register Description: Register Address: Bit # Name 7 RSA1 NAME BIT RSA1 7 RDMA 6 RSA0 5 RSLIP 4 RUA1 3 RRA 2 RCL 1 RLOS 0 IMR1 Interrupt Mask Register 1 18 Hex 6 RDMA 5 RSA0 4 RSLIP 3 RUA1 FUNCTION Receive Signaling All Ones 0 = interrupt masked 1 = interrupt enabled Receive Distant MF Alarm 0 = interrupt masked 1 = interrupt enabled Receive Signaling All Zeros 0 = interrupt masked 1 = interrupt enabled Receive Elastic Store Slip Occurrence
DS21Q59 Quad E1 Transceiver Register Name: Register Description: Register Address: Bit # Name 7 RMF NAME BIT RMF 7 RAF 6 TMF 5 SEC 4 TAF 3 LOTC 2 RCMF 1 PRBSD 0 SR2 Status Register 2 0B Hex 6 RAF 5 TMF 4 SEC 3 TAF 2 LOTC 1 RCMF 0 PRBSD FUNCTION Receive CAS Multiframe. Set every 2ms (regardless if CAS signaling is enabled or not) on receive multiframe boundaries. Receive Align Frame. Set every 250µs at the beginning of align frames.
DS21Q59 Quad E1 Transceiver Register Name: Register Description: Register Address: Bit # Name 7 RMF IMR2 Interrupt Mask Register 2 19 Hex 6 RAF NAME BIT RMF 7 RAF 6 TMF 5 SEC 4 TAF 3 LOTC 2 RCMF 1 PRBSD 0 5 TMF 4 SEC 3 TAF FUNCTION Receive CAS Multiframe 0 = interrupt masked 1 = interrupt enabled Receive Align Frame 0 = interrupt masked 1 = interrupt enabled Transmit Multiframe 0 = interrupt masked 1 = interrupt enabled One-Second Timer 0 = interrupt masked 1 = interrupt enabled Tran
DS21Q59 Quad E1 Transceiver 10. ERROR COUNT REGISTERS Each DS21Q59 transceiver contains a set of four counters that record bipolar (BPVs) or code violations (CVs), errors in the CRC4 SMF codewords, E bits as reported by the far end, and word errors in the FAS. The E-bit counter is reconfigured for counting errors in the PRBS pattern if receive PRBS is enabled. Each of these four counters is automatically updated on either one-second boundaries (CCR2.70 = 0) or every 62.5ms (CCR2.
DS21Q59 Quad E1 Transceiver 10.3 E-Bit/PRBS Bit-Error Counter E-bit count register 1 (EBCR1) is the most significant word and EBCR2 is the least significant word of a 16-bit counter that records far-end block errors (FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running with CRC4 multiframe. These error count registers increment once each time the received E-bit is set to 0. Since the maximum E-bit count in a one-second period is 1000, this counter cannot saturate.
DS21Q59 Quad E1 Transceiver 11. SIGNALING OPERATION Registers SA1 and SA16 are used to access the transmit and receive signaling function. Normally, reading these registers accesses the receive signaling data and writing these registers sources signaling data for the transmitter. The user can read what was written to the transmit signaling buffer by setting CCR6.5 = 1, then reading SA1–SA16. In most applications, however, CCR6.5 should be set = 0. 11.
DS21Q59 Quad E1 Transceiver 12. DS0 MONITORING FUNCTION Each DS21Q59 framer can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. In the transmit direction, the user determines which channel is to be monitored by properly setting the TCM0 to TCM4 bits in the CCR3 register. In the receive direction, the RCM0 to RCM4 bits in the CCR4 register need to be properly set.
DS21Q59 Quad E1 Transceiver Register Name: Register Description: Register Address: Bit # Name 7 LIRST NAME LIRST RESA RESR BIT 7 6 5 RCM4 4 RCM3 RCM2 RCM1 RCM0 3 2 1 0 Register Name: Register Description: Register Address: Bit # Name NAME B1 B2 B3 B4 B5 B6 B7 B8 7 B1 BIT 7 6 5 4 3 2 1 0 CCR4 (Repeated here from Section 6 for convenience.
DS21Q59 Quad E1 Transceiver 13. PRBS GENERATION AND DETECTION 15 The DS21Q59 can transmit and receive the 2 - 1 PRBS pattern. This PRBS pattern complies with ITU-T O.151 specifications. The PRBS pattern can be unframed (in all 256 bits of the frame), framed (in all time slots except TS0), or in any single time slot. Register CCR5 contains the control bits for configuring the transmit and receives PRBS functions. See Table 13-A and Table 13-B for selecting the transmit and receive modes of operation.
DS21Q59 Quad E1 Transceiver 14. SYSTEM CLOCK INTERFACE A single system clock interface (SCI) is common to all four DS21Q59 transceivers. The SCI is designed to allow any one of the four receivers to act as the master reference clock for the system. When multiple DS21Q59s are used to build an N port system, the SCI allows any one of the N ports to be the master. The selected reference is then distributed to the other DS21Q59s through the REFCLK pin.
DS21Q59 Quad E1 Transceiver 15. TRANSMIT CLOCK SOURCE Depending on the DS21Q59’s operating mode, the transmit clock can be derived from different sources. In a basic configuration, where the IBO function is disabled, the transmit clock is normally sourced from the TCLK pin. In this mode, a 2.048MHz clock with ±50ppm accuracy is applied to the TCLK pin.
DS21Q59 Quad E1 Transceiver 17. PER-CHANNEL LOOPBACK The DS21Q59 has per-channel loopback capability that can operate in one of two modes: remote per-channel loopback or local per-channel loopback. PCLB1/2/3/4 are used for both modes to determine which channels are looped back. In remote per-channel loopback mode, PCLB1/2/3/4 determine which channels (if any) in the transmit direction should be replaced with the data from the receiver or, in other words, off the E1 line.
DS21Q59 Quad E1 Transceiver 19. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION On the receiver, the RAF and RNAF registers always report the data as it is received in the additional (Sa) and international (Si) bit locations. The RAF and RNAF registers are updated with the setting of the receive align frame bit in status register 2 (SR2.6). The host can use the SR2.6 bit to know when to read the RAF and RNAF registers. It has 250ms to retrieve the data before it is lost.
DS21Q59 Quad E1 Transceiver Register Name: Register Description: Register Address: Bit # Name 7 Si TAF Transmit Align Frame Register 20 Hex 6 0 5 0 4 1 3 1 2 0 1 1 0 1 Note: This register must be programmed with the 7-bit FAS word. The DS21Q59 does not automatically set these bits. NAME Si 0 0 1 1 0 1 1 BIT 7 6 5 4 3 2 1 0 Register Name: Register Description: Register Address: Bit # Name 7 Si FUNCTION International Bit Frame Alignment Signal Bit. Set this bit = 0. Frame Alignment Signal Bit.
DS21Q59 Quad E1 Transceiver 20. USER-CONFIGURABLE OUTPUTS There are two user-configurable output pins for each transceiver, OUTA and OUTB. These pins can be programmed to output various clocks, alarms for line monitoring, or logic 0 and 1 levels to control external circuitry. They can also be used to access transmit data between the framer and transmit LIU. OUTA and OUTB can be active low or active high when operating as clock and alarm outputs. OUTA is active high if OUTAC.4 = 1 and active low if OUTAC.
DS21Q59 Quad E1 Transceiver Table 20-A. OUTA and OUTB Function Select OA3 OB3 OA2 OB2 OA1 OB1 OA0 OB0 0 0 0 0 External Hardware Control Bit. In this mode, OUTA and OUTB can be used as simple control pins for external circuitry. Use OA4 and OB4 to toggle OUTA and OUTB. 0 0 0 1 RCLK. Receive recovered clock. 0 0 1 0 Receive Loss-of-Sync Indicator. Real-time hardware version of SR1.0 (Table 9-A). 0 0 1 1 Receive Loss-of-Carrier Indicator. Real-time hardware version of SR1.1 (Table 9-A).
DS21Q59 Quad E1 Transceiver 21. LINE INTERFACE UNIT The line interface unit contains three sections: the receiver, which handles clock and data recovery; the transmitter, which waveshapes and drives the E1 line; and the jitter attenuator. The line interface control register (LICR), described below, controls each of these three sections.
DS21Q59 Quad E1 Transceiver 21.2 Transmit Waveshaping and Line Driving The DS21Q59 uses a set of laser-trimmed delay lines and a precision digital-to-analog converter (DAC) to create the waveforms that are transmitted onto the E1 line. The waveforms meet the ITU G.703 specifications (Figure 21-3). The user selects which waveform is to be generated by properly programming the L2/L1/L0 bits in the line interface control register (LICR).
DS21Q59 Quad E1 Transceiver Figure 21-2. External Analog Connections (Protected Interface) +VDD FUSE D2 D1 2:1 +VDD TTIP1 TRANSMIT LINE 0.47mF S (NONPOLARIZED) FUSE C1 TRING1 +VDD FUSE RECEIVE LINE TVDD TVSS 0.1mF 0.01mF 0.1mF 0.1mF 1/4 DS21Q59 D6 D5 1:1 RVDD RVSS D4 D3 DVDD DVSS RTIP1 S C2 RRING1 FUSE 60 60 D7 MCLK D8 0.1mF Note 1: All resistor values are ±1%. Note 2: C1 = C2 = 0.1mF. Note 3: S is a 6V transient suppressor. Note 4: D1 to D8 are Schottky diodes.
DS21Q59 Quad E1 Transceiver Figure 21-3. Transmit Waveform Template 1.2 1.1 269ns (in 75W systems, 1.0 on the scale = 2.37Vpeak in 120W systems, 1.0 on the scale = 3.00Vpeak) SCALED AMPLITUDE 1.0 0.9 0.8 0.7 G.703 TEMPLATE 194ns 0.6 0.5 219ns 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 -200 -150 -100 -50 0 50 100 150 200 250 TIME (ns) 21.
DS21Q59 Quad E1 Transceiver 21.3.2 Undedicated Clock Jitter Attenuator The undedicated jitter attenuator is useful for preparing a user-supplied clock for use as a transmission clock (TCLK). AJACKI is the input pin and AJCAKO is the output pin. Clocks generated by certain types of PLL or other synthesizers can contain too much jitter to be appropriate for transmission. Network requirements limit the amount of jitter that can be transmitted onto the network. This feature is enabled by setting SC1CR.
DS21Q59 Quad E1 Transceiver 22. CODE MARK INVERSION (CMI) The DS21Q59 provides a CMI interface for connecting to optical transports. This interface is a unipolar 1T2Bcoded signal. Ones are alternately encoded as a logical 1 or 0 level for the full duration of the clock period. Zeros are encoded as a 0-to-1 transition at the middle of the clock period. Figure 22-1 shows an example data pattern and its CMI result. The control bit for enabling CMI is in the OUTAC register, as shown below.
DS21Q59 Quad E1 Transceiver Transmit and receive CMI is enabled through OUTAC.7. When this register bit is set, the TTIP pin outputs CMIcoded data at normal TTL-type levels. This signal can be used to directly drive an optical interface. When CMI is enabled, the user can also use HDB3 coding. When this register bit is set, the RTIP pin becomes a unipolar CMI input. The CMI signal is processed to extract and align the clock with data. The bipolar code-violation counter counts CVs in the CMI signal.
DS21Q59 Quad E1 Transceiver 23. INTERLEAVED PCM BUS OPERATION In many architectures, the PCM outputs of individual framers are combined into higher-speed PCM buses to simplify transport across the system backplane. The DS21Q59 can be configured to allow PCM data buses to be multiplexed into higher-speed data buses, eliminating external hardware and saving board space and cost. The DS21Q59 uses a channel interleave method. See Figure 24-4 and Figure 24-7 for details of the channel interleave.
DS21Q59 Quad E1 Transceiver Figure 23-1.
DS21Q59 Quad E1 Transceiver 24. FUNCTIONAL TIMING DIAGRAMS 24.1 Receive Figure 24-1. Receive Frame and Multiframe Timing FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 RSYNC 1 RSYNC 2 NOTE 1: RSYNC IN FRAME/OUTPUT MODE (RCR.6 = 0). NOTE 2: RSYNC IN MULTIFRAME/OUTPUT MODE (RCR.6 = 1). THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME. Figure 24-2.
DS21Q59 Quad E1 Transceiver Figure 24-4.
DS21Q59 Quad E1 Transceiver 24.2 Transmit Figure 24-5. Transmit Frame and Multiframe Timing FRAME# 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 1 TSYNC TSYNC 2 NOTE 1: TSYNC IN FRAME MODE (TCR.1 = 0). NOTE 2: TSYNC IN MULTIFRAME MODE (TCR.1 = 1). Figure 24-6. Transmit Boundary Timing TCLK CHANNEL 1 TSER LSB Si 1 A CHANNEL 2 Sa4 Sa5 Sa6 Sa7 Sa8 MSB LSB MSB TSYNC1 TSYNC2 NOTE 1: TSYNC IS IN THE OUTPUT MODE (TCR.0 = 1).
DS21Q59 Quad E1 Transceiver Figure 24-7.
DS21Q59 Quad E1 Transceiver Figure 24-8. Framer Synchronization Flowchart Power Up RLOS = 1 FAS Search FASSA = 1 RLOS = 1 FAS Sync Criteria Met FASSA = 0 Resync if RCR1.0 = 0 Increment CRC4 Sync Counter; CRC4SA = 0 8ms Time Out CRC4 Multiframe Search (if enabled via CCR1.0) CRC4SA = 1 CRC4 Sync Criteria Met; CRC4SA = 0; Reset CRC4 Sync Counter Set FASRC (RIR.1) CRC4 Resync Criteria Met (RIR.2) CAS Resync Criteria Met; Set CASRC (RIR.0) Check for FAS Framing Error (depends on RCR1.
DS21Q59 Quad E1 Transceiver Figure 24-9. Transmit Data Flow TSER TAF TNAF.5-7 0 1 Timeslot 0 Pass-Through (TCR.6) 1 0 Si Bit Insertion Control (TCR.3) CRC4 Multiframe Alignment Word Generation (CCR.4) Receive Side CRC4 Error Detector 0 1 1 E-Bit Generation (TCR.5) Auto Remote Alarm Generation (CCR.4) TIDR 0 1 Idle Code / Channel Insertion Control via TIR1/2/3/4 SA1 - SA16 0 1 Signaling Insertion CCR6.3 Code Word Generation 0 1 CRC4 Enable (CCR.4) Transmit Unframed All Ones (TCR.
DS21Q59 Quad E1 Transceiver 25. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground Operating Temperature Range for DS21Q59L Operating Temperature Range for DS21Q59LN Storage Temperature Range Soldering Temperature Range -1.0V to +6.0V 0°C to +70°C -40°C to +85°C -55°C to +125°C See IPC/JEDEC J-STD-020A Specification Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
DS21Q59 Quad E1 Transceiver 26. AC TIMING PARAMETERS AND DIAGRAMS 26.1 Multiplexed Bus AC Characteristics Table 26-A. AC Characteristics—Multiplexed Parallel Port (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21Q59L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21Q59LN.
DS21Q59 Quad E1 Transceiver Figure 26-1. Intel Bus Read AC Timing (PBTS = 0) t CYC ALE PWASH t ASD WR t ASED t ASD RD PWEL PWEH t CH t CS CS t ASL t DHR t DDR AD0–AD7 t AHL Figure 26-2.
DS21Q59 Quad E1 Transceiver Figure 26-3.
DS21Q59 Quad E1 Transceiver 26.2 Nonmultiplexed Bus AC Characteristics Table 26-B. AC Characteristics—Nonmultiplexed Parallel Port (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21Q59L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21Q59LN.
DS21Q59 Quad E1 Transceiver Figure 26-5. Intel Bus Write Timing (PBTS = 0) A0–A7 ADDRESS VALID D0–D7 t7 10ns MIN RD t1 CS 0ns MIN t8 10ns MIN 0ns MIN t2 t6 75ns MIN WR t4 0ns MIN Figure 26-6. Motorola Bus Read Timing (PBTS = 1) ADDRESS VALID A0–A7 DATA VALID D0–D7 5ns MIN/20ns MAX t5 R/W t1 0ns MIN CS 0ns MIN t2 t3 t4 0ns MIN 75ns MAX DS Figure 26-7.
DS21Q59 Quad E1 Transceiver 26.3 Serial Port Table 26-C. AC Characteristics—Serial Port (BTS1 = 1, BTS0 = 0) (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21Q59L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21Q59LN.
DS21Q59 Quad E1 Transceiver 26.4 Receive AC Characteristics Table 26-D. AC Characteristics—Receiver (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21Q59L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21Q59LN.) (Figure 26-9 and Figure 26-10) PARAMETER SYMBOL CONDITIONS (Note 1) (Note 2) (Note 3) (Note 4) (Note 5) MIN TYP 648 488 244 122 61 0.5 tSP 0.
DS21Q59 Quad E1 Transceiver Figure 26-9. Receive AC Timing (Receive Elastic Store Disabled) 1 OUTA/OUTB (RCLK) 2 OUTA/OUTB (RCLK) t D1 MSB OF CHANNEL 1 RSER tD2 3 RSYNC 4 OUTA/OUTB 5 OUTA/OUTB NOTE 1: OUTA OR OUTB CONFIGURED TO OUTPUT RCLK (NONINVERTED). NOTE 2: OUTA OR OUTB CONFIGURED TO OUTPUT RCLK (INVERTED). NOTE 3: RSYNC IS IN THE OUTPUT MODE (RCR1.5 = 0). NOTE 4: OUTA OR OUTB CONFIGURED TO OUTPUT RFSYNC, CRC4 MF SYNC, OR CAS MF SYNC (NONINVERTED).
DS21Q59 Quad E1 Transceiver Figure 26-10. Receive AC Timing (Receive Elastic Store Enabled) tR t SL tF t SH SYSCLK t SP t D3 RSER MSB OF CHANNEL 1 t D4 1 RSYNC 2 OUTA/OUTB t HD t SU 3 RSYNC NOTE 1: RSYNC IS IN THE OUTPUT MODE (RCR.5 = 0). NOTE 2: OUTA OR OUTB CONFIGURED AS CRCR MF SYNC OR CAS MF SYNC. NOTE 3: RSYNC IS IN THE INPUT MODE (RCR.5 = 1).
DS21Q59 Quad E1 Transceiver 26.5 Transmit AC Characteristics Table 26-E. AC Characteristics—Transmit (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21Q59L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21Q59LN.) (Figure 26-11 and Figure 26-12) PARAMETER TCLK Period TCLK Pulse Width SYSCLK Period SYMBOL tCP CONDITIONS (Note 1) MIN (Note 2) TYP 648 20 0.5 tCP tCL 20 0.5 tCP (Note 1) 648 (Note 2) 488 (Note 3) 244 (Note 4) 122 (Note 5) 61 UNITS ns 488 tCH tSP MAX ns ns tSH 20 0.
DS21Q59 Quad E1 Transceiver Figure 26-11. Transmit AC Timing (IBO Disabled) t CP tR t CL tF t CH TCLK SU TSER t D2 1 TSYNC t HD t SU 2 TSYNC t D2 3 OUTA/OUTB NOTE 1: TSYNC IS IN OUTPUT MODE (TCR.0 = 1). NOTE 2: TSYNC IS IN INPUT MODE (TCR.0 = 0). TSYNC MAY BE HELD HIGH FOR MULTIPLE CLOCK CYCLES AS LONG AS IT TRANSITIONS LOW AT LEAST TWO CLOCK CYCLES BEFORE TRANSITIONING HIGH AGAIN. NOTE 3: APPLIES TO OUTA AND OUTB WHEN CONFIGURED FOR TPOS AND TNEG OUTPUTS.
DS21Q59 Quad E1 Transceiver Figure 26-12. Transmit AC Timing (IBO Enabled) t SP t SH t SL tF tR SYSCLK tSU TSER t HD NOTE: TSER IS ONLY SAMPLED ON THE FALLING EDGE OF SYSCLK WHEN THE IBO MODE IS ENABLED. 26.6 Special Modes AC Characteristics Table 26-F. AC Characteristics—Special Modes (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS21Q59L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS21Q59LN.
DS21Q59 Quad E1 Transceiver 27. PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.
DS21Q59 Quad E1 Transceiver 28. REVISION HISTORY DATE DESCRIPTION 042403 New product release. 1) Add 16MHz IBO timing diagram and AC characteristics 2) Correct typos in Figure 26-10. Reference to RSYNC as an input, not an output as shown in Note 3. 3) Added clarification to Section 23 regarding the TSYNCx pin when the part is configured for IBO mode. 4) Modified Table 26-D for clarification and corrected values. 5) Modified Table 26-E for clarification and corrected values.
