DS2406 Dual Addressable Switch Plus 1Kb Memory www.maxim-ic.com FEATURES PIN ASSIGNMENT Open drain PIO pins are controlled and their logic level can be determined over 1-Wire® bus for closed-loop control Replaces and is fully compatible with DS2407 but no user-programmable power-on settings and no Hidden Mode PIO channel A sink capability of 50mA at 0.4V with soft turn-on; channel B 8mA at 0.4V Maximum operating voltage of 13V at PIO-A, 6.
DS2406 ADDRESSABLE SWITCH DESCRIPTION The DS2406 Dual Addressable Switch Plus Memory offers a simple way to remotely control a pair of open drain transistors and to monitor the logic level at each transistor’s output via the 1-Wire bus for closed loop control. Each DS2406 has its own 64-bit ROM registration number that is factory lasered into the chip to provide a guaranteed unique identity for absolute traceability.
DS2406 OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS2406. The device has four major data components: 64-bit lasered ROM, 1024 bits of EPROM data memory, status memory, and the PIO-control block. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the five ROM function commands: Read ROM, Match ROM, Search ROM, Skip ROM, or Conditional Search ROM.
DS2406 PARASITE POWER The DS2406 can derive its power entirely from the 1-Wire bus by storing energy on an internal capacitor during periods of time when the signal line is high. During low times the device continues to operate off of this “parasite” power source until the 1-Wire bus returns high to replenish the parasite (capacitor) supply.
DS2406 MEMORY MAP The DS2406 has two memory sections, called data memory and status memory. The data memory consists of 1024 bits of one-time programmable EPROM organized as 4 pages of 32 bytes each. The address range of the device’s status memory is 8 bytes. The first seven bytes of status memory (addresses 0 to 6) are implemented as EPROM. The eighth byte (address 7) consists of static RAM. The complete memory map is shown in Figure 5.
DS2406 STATUS MEMORY The Status Memory can be read or written to indicate various conditions to the software interrogating the DS2406. These conditions include special features for the data memory, definition of the settings for the Conditional Search as well as the channel flip-flops and the external power supply indication. How these functions are assigned to the bits of the Status Memory is detailed in Figure 6.
DS2406 Status Memory location 7 serves three purposes: 1) it holds the selection code for the Conditional Search function, 2) provides the bus master a memory mapped access to the channel flip-flops that control the PIO output transistors, and 3) allows the bus master to determine whether the device is hooked up to a VCC power supply. Bit locations 0 to 4 store the conditional search settings. Their codes are explained in the section “ROM Function Commands” later in this document.
DS2406 Extended Read Memory [A5h] The Extended Read Memory command supports page redirection when reading data from the 1024-bit EPROM data field. One major difference between the Extended Read Memory and the basic Read Memory command is that the bus master receives the Redirection Byte (see description of Status Memory) first before investing time in reading data from the addressed memory location.
DS2406 WRITING EPROM MEMORY The function flow for writing to the Data Memory and Status Memory is almost identical. After the appropriate write command has been issued, the bus master will send a two-byte starting address (TA1=(T7:T0), TA2=(T15:T8)) and a byte of data (D7:D0). A 16-bit CRC of the command byte, address bytes, and data byte is computed by the DS2406 and read back by the bus master to confirm that the correct command word, starting address, and data byte were received.
DS2406 Memory Function Flow Chart Figure 7 Bus Master TX Memory Function Command F0h Read Memory ? A5h Extended Rd. Memory ? Y N Y Bus Master TX TA1(T7:T0), TA2 (T15:T8) DS2406 sets Memory Address = (T15:T0) Bus Master RX Redirection Byte Bus Master RX Data from Data Memory Master TX Reset ? N N End of Data Mem. ? Y Master TX Reset ? Y Bus Master RX CRC16 of Command, Address, Redir. Byte (1st pass) CRC16 of Redir. Byte (subs.
DS2406 Memory Function Flow Chart (continued) Figure 7 From Figure 7 1st Part 0Fh Write Memory ? 55h Write Status N ? Legend: Y Bus Master TX TA1(T7:T0), TA2 (T15:T8) DS2406 sets Memory Address = (T15:T0) Decision made by Bus Master Decision made by DS2406 N To Figure 7 3rd Part Y Bus Master TX TA1(T7:T0), TA2 (T15:T8) DS2406 sets Memory Address = (T15:T0) Bus Master TX Data Byte (D7:D0) Bus Master TX Data Byte (D7:D0) Bus Master RX CRC16 of Command, Address, Data (1st pass); CRC16 of Addr
DS2406 Memory Function Flow Chart (continued) Figure 7 From Figure 7 2nd Part AAh Read Status F5h Channel Access ? N ? Y Bus Master TX TA1(T7:T0), TA2 (T15:T8) Y Bus Master TX Ch.Control Bytes 1, 2 Bus Master TX Reset Pulse Bus Master RX Channel Info Byte DS2406 TX Presence Pulse DS2406 sets Status Address = (T15:T0) Y Bus Master RX Data from Status Memory N Master TX Reset ? N DS2406 increments Address Counter Master TX Reset ? N N End of Status Mem.
DS2406 Write Memory [0Fh] The Write Memory command is used to program the 1024-bit EPROM data memory. The details of the functional flow chart are described in the section “Writing EPROM Memory”. The data memory address range is 0000h to 007Fh. If the bus master sends a starting address higher than this, the nine most significant address bits are set to zeros by the internal circuitry of the chip.
DS2406 Most easily understood are the bits CHS0 and CHS1, which select the channels to communicate with. One can select one of the two channels or both channels together. The selection codes are shown in the table below.
DS2406 The TOG bit of Channel Control Byte 1 specifies if one is always reading or writing (TOG = 0) or if one is going to change from reading to writing or vice versa after every data byte that has been sent to or received from the DS2406 (TOG = 1). When accessing one channel, one byte is equivalent to eight reads from or writes to the selected PIO pin. When accessing two channels, one byte is equivalent to four reads or writes from/to each channel.
DS2406 After the Channel Control bytes have been transmitted the bus master receives the Channel Info byte (Figure 9). This byte indicates the status of the channel flip-flops, the PIO pins, the activity latches as well as the availability of channel B and external power supply. To be able to read from a PIO channel, the output transistor needs to be non-conducting, which is equivalent to a 1 for the channel flip-flop.
DS2406 TWO-CHANNEL WRITE Figure 10c td1 1-WIRE 15 µs < td1 < 60 µs A1 B1 A2 td0 B2 200 ns < td0 < 300 ns A3 B3 A4 B4 IC=1, SYNCHRONOUS MODE PIO-A A1 A2 A3 A4 PIO-B B1 B2 B3 B4 IC=0, ASYNCHRONOUS MODE PIO-A PIO-B A1 A2 B1 A3 B2 A4 B3 B4 1-WIRE BUS SYSTEM The 1-Wire bus is a system, which has a single bus master and one or more slaves. In all instances, the DS2406 is a slave device. The bus master is typically a microcontroller.
DS2406 DS2406 EQUIVALENT CIRCUIT Figure 11 PIO Channel 1-Wire Interface Activity Latch "1" DATA to PIOControl RX Q Edge Detector PIO D Q Reset 5 µA Typ. 10 M Ω Typ.
DS2406 INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). The presence pulse lets the bus master know that the DS2406 is on the bus and is ready to operate. For more details, see the “1-Wire Signaling” section.
DS2406 ROM FUNCTIONS FLOW CHART Figure 13 Bus Master TX Reset Pulse DS2406 TX Presence Pulse R Bus Master TX ROM Function Command 33h Read ROM Command ? Y N 55h Match ROM Command ? Y N F0h Search ROM Command ? Y N S ECh Conditional Search ? Y Condition Fulfilled ? DS2406 TX Family Code (1 Byte) Master TX Bit 0 Bit 0 Match ? DS2406 TX Serial Number (6 Byte) Master TX Bit 1 Bit 1 Match ? DS2406 TX CRC Byte Master TX Bit 63 DS2406 TX Bit 0 DS2406 TX Bit 0 Master TX Bit 0 Bit 0 Match ? DS2406
DS2406 Conditional Search ROM [ECh] The Conditional Search ROM command operates similarly to the Search ROM command except that only devices fulfilling the specified condition will participate in the search. This command provides an efficient means for the bus master to identify devices in a multidrop system that have to signal a status change, e.g. the opening of a window in a building control application. The condition is specified by the bit functions CSS0 to CSS4 in Status Memory location 7.
DS2406 The activity latch (Figure 11) captures an event for interrogation by the bus master at a later time. This way, the bus master needs not interrogate devices continuously. The activity latch is set to 1 with the first negative or positive edge detected on the associated PIO channel. It can be cleared with the Channel Access command if the ALR bit of the Channel Control Byte 1 is set. The activity latch is automatically cleared when the DS2406 powers up.
DS2406 1-WIRE SIGNALING The DS2406 requires strict protocols to ensure data integrity. The protocol consists of five types of signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, Read Data, and Program Pulse. Except for the presence pulse the bus master initiates all these signals. The initialization sequence required to begin any communication with the DS2406 is shown in Figure 14.
DS2406 READ/WRITE TIMING DIAGRAM Figure 15 Write-one Time Slot tSLOT VPULLUP tREC VPULLUP MIN VIH MIN DS2406 Sampling Window VIL MAX 0V tLOW1 15µs 60µs RESISTOR MASTER 60 µs ≤ tSLOT < 120 µs 1 µs ≤ tLOW1 < 15 µs 5 µs ≤ tREC < ∞ Write-zero Time Slot tSLOT VPULLUP VPULLUP MIN VIH MIN DS2406 Sampling Window VIL MAX 0V 15µs 60µs t LOW0 RESISTOR 60 µs ≤ tLOW0 < tSLOT < 120 µs MASTER 5 µs ≤ tREC < ∞ 24 of 32 tREC
DS2406 READ/WRITE TIMING DIAGRAM (continued) Figure 15 Read-data Time Slot tREC tSLOT VPULLUP VPULLUP MIN VIH MIN Master Sampling Window VIL MAX 0V tSU tRELEASE tLOWR tRDV RESISTOR MASTER DS2406 * 60 µs ≤ tSLOT < 120 µs 2 µs ≤ tLOWR < 15 µs 0 ≤ tRELEASE < 45 µs 5 µs ≤ tREC < ∞ tRDV = 15 µs tSU < 2 µs The optimal sampling point for the master is as close as possible to the end time of the 15μs tRDV period without exceeding tRDV.
DS2406 PROGRAM PULSE TIMING DIAGRAM Figure 16 V PP V PULLUP t GND Normal 1-Wire Communication Ends > 5 µs t DP t RP 480 µs t PP FP > 5 µs t Normal 1-Wire Communication Resumes DV LINE TYPE LEGEND: Bus master active high (12 V @ 10 mA) Resistor pull-up CRC GENERATION With the DS2406 there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is an 8-bit type. It is computed at the factory and lasered into the most significant byte of the 64-bit ROM.
DS2406 the command byte into the cleared CRC generator, followed by the two address bytes and the Redirection Byte. Subsequent passes through the Extended Read Memory flow chart will generate a 16-bit CRC that is the result of clearing the CRC generator and then shifting in only the Redirection Byte. When writing to the DS2406 (either data memory or status memory), the bus master receives a 16-bit CRC to verify that the data transfer was correct before applying the programming pulse.
DS2406 ABSOLUTE MAXIMUM RATINGS* Voltage on DATA or PIO-A to Ground Voltage on VCC or PIO-B to Ground Operating Temperature Range Storage Temperature Range Soldering Temperature * -0.5V to +13.0V -0.5V to +6.5V -40°C to +85°C -55°C to +125°C See J-STD-020A Specifications This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
DS2406 CAPACITANCES PARAMETER Capacitance DATA Pin Capacitance PIO-A Pin Capacitance PIO-B Pin Capacitance VCC Pin (tA = 25°C) SYMBOL CD CA CB CC MIN SYMBOL tSLOT tLOW1 tLOW0 tLOWR tRDV tRELEASE tSU tREC tRSTH tRSTL tPDH tPDL tSUA tSUB tDP tDV tPP tRP tFP MAX 800 100 25 10 AC ELECTRICAL CHARACTERISTICS PARAMETER Time Slot Write 1 Low Time Write 0 Low Time Read Low Time Read Data Valid Release Time Read Data Setup 1-Wire Recovery Time Reset High Time Reset Low Time Presence Detect High Presence Detect
DS2406 PIO SINK CURRENT I SA , I SB 100 mA @ 0.4V 90 mA max. 80 mA 70 mA PIO-A 60 mA 50 mA 40 mA min. 30 mA max. 20 mA PIO-B 10 mA min. V PUP 2.8V 4V 5V 6V NOTE: The sink current is production-tested at VPUP = 2.8V; the specification for VPUP of 4V, 5V and 6V is guaranteed by design. NOTES: 1. All voltages are referenced to ground. 2. VPUP, VPUPA, VPUPB = external pull-up voltage. 3. VIH is a function of the chip-internal supply voltage.
DS2406 13. Read data setup time refers to the time the host must pull the 1-Wire bus low to read a bit. Data is guaranteed to be valid within 2µs of this falling edge and will remain valid for 15µs total from falling edge on 1-Wire bus. 14. An additional reset or communication sequence cannot begin until the reset high time has expired. 15. The Reset Low Time (tRSTL) should be restricted to a maximum of 960μs to allow interrupt signaling; otherwise, it could mask or conceal interrupt pulses. 16.
DS2406 REVISION HISTORY REVISION DATE DESCRIPTION PAGES CHANGED Relocated VPUP specification from headline to Data Pin parameter block in the DC ELECTRICAL CHARACTERISTICS table. Changed VILmax spec from 0.8V to 0.5V. 033109 Removed VOH spec for 1-Wire port. Changed VILAmax spec from 0.6V to 0.3V. Replaced input resistance RI with input leakage current ILA, ILB. Replaced VOHA with VPUPA. Replaced VOHB with VPUPB. Added GBD note to ILA, ILB, ISA, ISB, VPUPA, VPUPB. Changed ICCmax from 4μA to 6μA.
