LE AVAILAB DS2408 1-Wire 8-Channel Addressable Switch FEATURES Eight Channels of Programmable I/O with Open-Drain Outputs On-Resistance of PIO Pulldown Transistor 100Ω (max); Off-Resistance 10MΩ (typ) Individual Activity Latches Capture Asynchronous State Changes at PIO Inputs for Interrogation by the Bus Master Data-Strobe Output to Synchronize PIO Logic States to External Read/Write Circuitry Built-in Multidrop Controller Ensures Compatibility with Other Dallas Semiconductor 1-Wire®
DS2408 ABSOLUTE MAXIMUM RATINGS* P0 to P7, RSTZ, I/O Voltage to GND P0 to P7, RSTZ, I/O combined sink current Operating Temperature Range Junction Temperature Storage Temperature Range Lead temperature (soldering 10s) Soldering Temperature (reflow) * -0.5V, +6V 20mA -40°C to +85°C +150°C -55°C to +125°C +300°C +260°C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied.
PARAMETER SYMBOL CONDITIONS I/O Pin, 1-Wire Reset, Presence-Detect Cycle Standard speed, VPUP > 4.5V Reset-Low Time tRSTL (Notes 1, 12) Standard speed Overdrive speed Standard speed Presence-Detect High tPDH Time (Note 12) Overdrive speed Standard speed, VPUP > 4.5V Presence-Detect Fall tFPD Time (Note 13) Standard speed Overdrive speed Standard speed, VPUP > 4.5V Presence-Detect Low tPDL Time (Note 12) Standard speed Overdrive speed Standard speed, VPUP > 4.
DS2408 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11: Note 12: Note 13: Note 14: Note 15: Note 16: Note 17: Note 18: System Requirement Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
DS2408 STANDARD VALUES DS2408 VALUES PARAMETER STANDARD OVERDRIVE STANDARD OVERDRIVE NAME SPEED SPEED SPEED SPEED MIN MAX MIN MAX MIN MAX MIN MAX tSLOT (incl. tREC) 61µs (undef.) 7µs (undef.) 65µs 1) (undef.) 10µs (undef.) tRSTL 480µs (undef.) 48µs 80µs 660µs 720µs 53µs 80µs tPDH 15µs 60µs 2µs 6µs 15µs 60µs 2µs 7µs tPDL 60µs 240µs 8µs 24µs 60µs 280µs 7µs 27µs tW0L 60µs 120µs 6µs 16µs 60µs 120µs 8µs 13µs tSLS, tSPD 15µs 60µs 2µs 6µs 15µs 60µs 1.
DS2408 APPLICATION The DS2408 is a multipurpose device. Typical applications include port expander for microcontrollers, remote multichannel sensor/actuator, communication and control unit of a microterminal, or as network interface of a microcontroller. Typical application circuits and communication examples are found later in this data sheet (Figures 17 to 22). OVERVIEW Figure 1 shows the relationships between the major function blocks of the DS2408.
DS2408 Figure 2. HIERARCHICAL STRUCTURE FOR 1-Wire PROTOCOL 1-Wire Net Bus Master Other Devices DS2408 Command Level: Cmd. Data Field Codes: Affected: Available Commands: 1-Wire ROM Function Commands DS2408-Specific Control Function Commands Read ROM Match ROM Search ROM Skip ROM Conditional Search ROM Overdrive Match Overdrive Skip Resume 33h 55h F0h CCh ECh 69h 3Ch A5h 64-BIT ROM, RC-FLAG 64-BIT ROM, RC-FLAG 64-BIT ROM, RC-FLAG RC-FLAG 64-BIT ROM, RC-FLAG, Port Status, Cond.
DS2408 The shift register bits are initialized to 0. Then, starting with the least significant bit of the family code, one bit at a time is shifted in. After the eighth bit of the family code has been entered, the serial number is entered. After the serial number has been entered, the shift register contains the CRC value. Shifting in the eight bits of CRC returns the shift register to all 0s. Figure 4.
DS2408 PIO Logic-State Register The logic state of the PIO pins can be obtained by reading this register using the Read PIO Registers command. Reading this register does not generate a signal at the RSTZ pin, even if it is configured as STRB . See the Channel-Access commands description for details on STRB . PIO Logic State Register Bitmap ADDR 0088h b7 P7 b6 P6 b5 P5 b4 P4 b3 P3 b2 P2 b1 P1 b0 P0 This register is read-only.
Figure 6. CHANNEL I/O AND RSTZ SIMPLIFIED LOGIC DIAGRAM TO PIO LOGIC STATE REGISTER PIO ACTIVITY LATCH "1" TO ACTIVITY LATCH STATE REGISTER POWER ON RESET Q R CLR ACT LATCH TO PIO OUTPUT LATCH STATE REG. DATA D CLOCK CHANNEL I/O PIN D Q S DS2408 EDGE DETECTOR Q Q PIO OUTPUT LATCH RSTZ PIN PORT FUNCTION CONTROL ROS STRB Conditional Search Channel Selection Mask Register The data in this register controls whether a PIO channel qualifies for participation in the conditional search command.
DS2408 Conditional Search Channel Polarity Selection Register The data in this register specifies the polarity of each selected PIO channel for the device to respond to the conditional search command. Within a PIO channel, the data source may be either the channel's input signal (pin) or the channel's activity latch, as specified by the PLS bit in the Control/Status register at address 008Dh. This register can only be written through the Write Conditional Search Registers command.
DS2408 Control/Status Register The data in this register reports status information, determines the function of the RSTZ pin and further configures the device for conditional search. This register can only be written through the Write Conditional Search Registers command. Control/Status Register Bitmap ADDR 008Dh b7 VCCP b6 0 b5 0 b4 0 b3 PORL b2 ROS b1 CT b0 PLS This register is read/write. Without VCC supply, this register reads 08h after a power-on reset.
DS2408 Figure 8-1. CONTROL FUNCTIONS FLOW CHART From ROM Functions Flow Chart (Figure 12) Bus Master TX Control Function Command F0h Read PIO Reg.? To Figure 8 nd 2 Part N Note: To read the three PIO state and latch register bytes, the target address should be 0088h. Returned data for a target address <0088h is undefined.
Figure 8-2.
Figure 8-3.
DS2408 CONTROL FUNCTION COMMANDS Once a ROM function command is completed, the Control Function Commands can be issued. The Control Functions Flow Chart (Figure 8) describes the protocols necessary for accessing the PIO channels and the special function registers of the DS2408. The communication between the master and the DS2408 takes place either at standard speed (default, OD = 0) or at overdrive speed (OD = 1). If not explicitly set into the overdrive mode, the device operates at standard speed.
DS2408 The status of all eight PIO channels is sampled at the same time. The first sampling occurs during the last (most significant) bit of the command code F5h. While the master receives the MSB of the PIO status (i.e., the status of pin P7) the next sampling occurs and so on until the master has received 31 PIO samples. Next, the master receives the inverted CRC16 of the command byte and 32 PIO samples (first pass) or the CRC of 32 PIO samples (subsequent passes).
DS2408 the data pattern AAh. If the RSTZ pin is configured as STRB , a strobe signal will be generated during the transmission of the first two (least significant) bits of the confirmation byte. The strobe can signal a FIFO or a microcontroller to read the new data byte from the PIO. While the last bit of the confirmation byte is transmitted, the DS2408 samples the status of the PIO pins, as shown in Figure 9, and sends it to the master.
DS2408 Figure 11. HARDWARE CONFIGURATION VPUP SIMPLE BUS MASTER RPUP RX DS2408 1-Wire PORT SEE TEXT DATA RX TX TX RX = RECEIVE DS2480B BUS MASTER +5V VDD VPP HOST CPU SERIAL PORT 100Ω MOSFET TX = TRANSMIT OPEN-DRAIN PORT PIN SERIAL IN SERIAL OUT POL 1-W RXD NC TO 1-Wire DATA TXD GND DS2480B A multidrop bus consists of a 1-Wire bus with multiple slaves attached. At standard speed the 1-Wire bus has a maximum data rate of 15.3kbps.
DS2408 TRANSACTION SEQUENCE The protocol for accessing the DS2408 through the 1-Wire port is as follows: Initialization ROM Function Command Control Function Command Transaction/Data Illustrations of the transaction sequence for the various control function commands are found later in this document. INITIALIZATION All transactions on the 1-Wire bus begin with an initialization sequence.
DS2408 PLS of the Control/Status Register (address 008Dh), and the state of the PIO channels. See Figure 7 for a description of the Conditional Search logic. The device also responds to the Conditional Search if the PORL bit is set. The Conditional Search ROM provides an efficient means for the bus master to determine devices on a multidrop system that have to signal an important event, such as a state change at a PIO pin caused by an external signal.
DS2408 Figure 12-1. ROM FUNCTIONS FLOW CHART Bus Master TX Reset Pulse From Control Functions Flow Chart (Figure 8) From Figure 12, 2 OD Reset Pulse? N nd Part OD = 0 Y Bus Master TX ROM Function Command 33h Read ROM Command? Y RC = 0 DS2408 TX Presence Pulse N 55h Match ROM Command? F0h Search ROM Command? N Y To Figure 12 nd 2 Part ECh Cond.
DS2408 Figure 12-2.
DS2408 1-WIRE SIGNALING The DS2408 requires strict protocols to ensure data integrity. The protocol consists of four types of signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write-Zero, Write-One, and Read-Data. Except for the presence pulse, the bus master initiates all these signals. The DS2408 can communicate at two different speeds, standard speed, and overdrive speed. If not explicitly set into the overdrive mode, the DS2408 will communicate at standard speed.
DS2408 Read/Write Time Slots Data communication with the DS2408 takes place in time slots, which carry a single bit each. Write time slots transport data from bus master to slave. Read time slots transfer data from slave to master. The definitions of the write and read time slots are illustrated in Figure 14. All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line falls below the threshold VTL, the DS2408 starts its internal time base.
DS2408 Read-Data Time Slot Slave-to-Master A read-data time slot begins like a write-one time slot. The voltage on the data line must remain below VTLMIN until the read low time tRL has expired. During the tRL window, when responding with a 0, the DS2408 starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again.
DS2408 3) The input buffer was designed with hysteresis. If a negative glitch crosses VTH but doesn’t go below VTH - VHY, it will not be recognized (Figure 15, Case A). The hysteresis is effective at any 1-Wire speed. 4) There is a time window specified by the rising edge hold-off time tREH during which glitches will be ignored, even if they extend below the VTH - VHY threshold (Figure 15, Case B, tGL < tREH).
DS2408 Figure 16. CRC-16 HARDWARE DESCRIPTION AND POLYNOMIAL POLYNOMIAL = X st X 0 X 1 th th 10 STAGE 9 STAGE X 8 X X 9 X X th th X 11 3 X th 12 STAGE 11 STAGE 10 2 X 12 4 14 STAGE X 13 X 2 +X +1 th th 5 th 7 STAGE 6 STAGE X th 13 STAGE 15 5 STAGE 4 STAGE 3 STAGE 2 STAGE +X th th rd nd 1 STAGE 16 X 6 8 STAGE X th 7 th 15 STAGE 16 STAGE 14 X 15 X 16 INPUT DATA CRC OUTPUT Figure 17.
Figure 18. DS2408 AS SLAVE INTERFACE FOR INTELLIGENT DISPLAY 1 6 2 5 4 DS9503 LCD Display VCC 47U 1 2 3 4 5 6 VCC 5VDC GND 1W 3 4 5 2 14 13 12 11 9 8 7 P0 P1 P2 P3 P4 P5 P6 P7 VCC IO GND RSTZ 7 8 9 10 11 12 13 14 VCC 15 16 10 DS2408 GND VCC CONTRAST D/ C R/ W S TB D0 D1 D2 D3 D4 D5 D6 D7 ACM1601B 16X1 Display with Back Light 3 Local iButton Probe 47 LEDA LEDK VCC 1 2 3 4 5 6 7 8 9 10 Up 10K Down Select Figure 19.
Figure 20. DS2408 AS µC-OPERATED KEYBOARD SCANNER 10kΩ 10U 1 2 3 4 5 6 7 8 9 10 VCC VCC GND 1W 3 VCC 4 IO 5 GND 2 14 13 12 11 9 8 7 P0 P1 P2 P3 P4 P5 P6 P7 10 RSTZ DS2408 VCC POR Circuit VCC RST GND DS1811 The DS1811 has an internal pull-up resistor of 5.5 kΩ To More Switch Rows (Up to 4 x 4, 3 x 5 or 2 x 6) Figure 21. DS2408 AS PARASITE-POWERED PUSH-BUTTON SENSOR VCC 0.
DS2408 Figure 22.
Command-Specific 1-Wire Communication Protocol—Legend SYMBOL DESCRIPTION RST PD Select RPR CAR CAW WCS RAL TA CRC16\ FF loop AA loop <32 samples>, CRC16\ loop , AAh, , 1-Wire Reset Pulse generated by master. 1-Wire Presence Pulse generated by slave. Command and data to satisfy the ROM function protocol. Command "Read PIO Registers". Command "Channel-Access Read". Command "Channel-Access Write". Command "Write Conditional Search Register".
DS2408 Channel-Access Write (Success) RST PD Select CAW , AAh, Loop Channel-Access Write (Fail New State) RST PD Select CAW , FF loop Write Conditional Search Register (Success) RST PD Select WCS TA FF loop Write Conditional Search Register (Fail Address) RST PD Select WCS TA FF loop Reset Activity Latches (Cannot Fail) RST PD Select RAL AA loop COMMUNICATION EXAMPLES The examples in this section demonstrate the
DS2408 MASTER MODE TX RX Step 2 TX TX TX TX RX TX RX Step 3 TX TX TX TX (—) DATA (LSB FIRST) (Reset) (Presence) CCh F0h 8Dh 00h 84h (Reset) (Presence) CCh 5Ah (—) RX (—) RX TX TX RX RX AAh (—) AAh (—) (—) TX RX (Reset) (Presence) COMMENTS Reset pulse Presence pulse Issue Skip ROM command Issue Read PIO Registers command TA1, target address = 8Dh TA2, target address =
MASTER MODE TX TX RX Step 2 TX TX TX TX RX TX RX Step 3 TX TX DATA (LSB FIRST) 04h (Reset) (Presence) CCh F0h 8Dh 00h 84h (Reset) (Presence) CCh F5h (—) RX (—) (—) (—) RX <2 bytes CRC16> (—) (—) TX RX (Reset) (Presence) DS2408 COMMENTS Write byte to Control/Status Register Reset pulse Presence pulse Issue Skip ROM command Issue Read PIO Registers command TA1, target address = 8Dh TA2, target address = 008Dh Read Control/Status Register and verify Reset pulse Presence pulse
DS2408 Control/Status register, Source is Activity Latch ⇒ PLS = 1 Term is OR ⇒ CT = 0 RSTZ = inactive (input) ⇒ ROS = 0 Clear Power-On Reset Latch ⇒ PORL = 0 The resulting setup data for the Control/Status Register is 01h.
After all DS2408s are initialized, perform the search process below as an endless loop: MASTER MODE Step 4 TX RX TX Step 5 DATA (LSB FIRST) (Reset) (Presence) ECh RX <2 bits> TX <1 bits> RX <2 bits> TX <1 bits> (—) (—) TX TX TX F0h 88h 00h RX <8 data bytes> RX <2 bytes CRC16> TX RX TX TX RX (Reset) (Presence) A5h C3 AAh (—) (—) COMMENTS Reset pulse Presence pulse Issue Conditional Search ROM command Read 2 bits; if both bits are 1, no push button has been pressed; in this case return
DS2408 APPLICATIONS INFORMATION Power-up timing The DS2408 is sensitive to the power-on slew rate and can inadvertently power up with a test mode feature enabled. When this occurs, the P0 port does not respond to the Channel Access Write command. For most reliable operation, it is recommended to disable the test mode after every power-on reset using the Disable Test Mode sequence shown below. The 64-bit ROM code must be transmitted in the same bit sequence as with the Match ROM command, i.e.
DS2408 Revision History REVISION DATE 051403 DESCRIPTION Initial release PAGES CHANGED — 122203 Corrected the wiring in Figure 18: in 4-bit mode, the display uses D4 to D7. 28 061604 Deleted empty page at the end 37 12/10 Updated the Ordering Information for lead(Pb)-free; updated soldering temperature in the Absolute Maximum Ratings. Applied EC table note 14 to tW0L. Deleted ε from the tW1L spec in the EC table.
