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DS2484

Single-Channel 1-Wire Master

with Adjustable Timing and Sleep Mode

General Description

The DS2484 is an I

C-to-1-Wire

bridge device that

interfaces directly to standard (100kHz max) or fast

(400kHz max) I

C masters to perform protocol con-

version between the I

C master and any downstream

1-Wire slave devices. Relative to any attached 1-Wire

slave device, the DS2484 is a 1-Wire master. Internal,

user-adjustable timers relieve the system host processor

from generating time-critical 1-Wire waveforms, support-

ing both standard and overdrive 1-Wire communication

speeds. In addition, the 1-Wire bus can be powered

down under software control. The dual-voltage operation

allows different operating voltages on the I

C and 1-Wire

side. Strong pullup features support 1-Wire power deliv-

ery to 1-Wire devices such as EEPROMs and sensors.

When not in use, the DS2484 can be put in sleep mode

where power consumption is minimal.

Applications

Printers

Medical Instruments

Industrial Sensors

Cell Phones

Benefits and Features

S I

C Host Interface Supports 100kHz and 400kHz

C Communication Speeds

S Standard and Overdrive 1-Wire Communication

Speeds

S Adjustable 1-Wire Timing for t

RSTL

, t

MSP

, t

W0L

and t

REC0

S 1-Wire Port Can Be Powered Down Under

Software Control

S Supports Power-Saving Sleep Mode (SLPZ Pin),

Where the 1-Wire Port is in High Impedance

S I

C Operating Voltages: 1.8V ±5%, 3.3V ±10%, and

5.0V +5/-10%

S Built-In Level Translator: 1-Wire Operating Voltage

from 1.8V -5% to 5.0V +5%, Independent of I

Voltage

S Built-In ESD Protection Level of ±8kV Human

Body Model (HBM) Contact Discharge on IO Pin

S -40NC to +85NC Operating Temperature Range

S 8-Pin TDFN and 6-Pin SOT23 Packages

Typical Application Circuit

19-6701; Rev 0; 5/13

Ordering Information appears at end of data sheet.

1-Wire is a registered trademark of Maxim Integrated Products, Inc.

= I

C PULLUP RESISTOR (SEE THE Pullup Resistor R

Sizing SECTION FOR R

SIZING)

For related parts and recommended products to use with this part, refer to: www.maximintegrated.com/DS2484.related

SDA

SCL

SLPZ IO

1-Wire BUS

µC

C PORT)

1-Wire

DEVICE #1

1-Wire

DEVICE #2

1-Wire

DEVICE #n

DS2484

For pricing, delivery, and ordering information, please contact Maxim Direct at

1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Summary of content (29 pages)

PAGE 1
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode General Description The DS2484 is an I2C-to-1-WireM bridge device that interfaces directly to standard (100kHz max) or fast (400kHz max) I2C masters to perform protocol conversion between the I2C master and any downstream 1-Wire slave devices. Relative to any attached 1-Wire slave device, the DS2484 is a 1-Wire master.
PAGE 2
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode ABSOLUTE MAXIMUM RATINGS Operating Temperature Range........................... -40NC to +85NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -55NC to +125NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................
PAGE 3
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode ELECTRICAL CHARACTERISTICS (continued) (TA = -40NC to +85NC, unless otherwise noted.) (Note 1) PARAMETER Presence-Detect Sample Time Sampling for Short and Interrupt SYMBOL tMSP tSI Write-One/Read Low Time tW1L Read Sample Time tMSR Write-Zero Low Time tW0L Write-Zero Recovery Time tREC0 1-Wire Time Slot tSLOT CONDITIONS Standard Overdrive MIN TYP MAX UNITS -5% See Table 7 +5% Fs Standard 7.6 8 8.
PAGE 4
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode ELECTRICAL CHARACTERISTICS (continued) (TA = -40NC to +85NC, unless otherwise noted.) (Note 1) PARAMETER SYMBOL Input Current with Input Voltage Between 0.1 O VCC(MAX) and 0.9 O VCC(MAX) II (Note 10) Input Capacitance CI (Note 4) SCL Clock Frequency CONDITIONS MIN -10 TYP MAX UNITS +10 FA 10 pF 400 kHz fSCL 0 tHD:STA 0.6 Fs Low Period of the SCL Clock tLOW 1.3 Fs High Period of the SCL Clock tHIGH 0.
PAGE 5
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode Pin Configurations TOP VIEW SDA 2 SLPZ N.C. DS2484 3 EP 4 8 GND 7 IO 6 VCC 5 N.C. + 1 + SCL TOP MARK TDFN (2mm x 3mm) 2484 YMrr TOP VIEW TOP MARK VCC IO GND 6 5 4 SOT23 3Hrr + + DS2484 1 2 3 SLPZ SDA SCL “rr” = REVISION CODE Pin Description PIN NAME FUNCTION TDFN-EP SOT23 1 3 SCL I2C Serial-Clock Input. Must be connected to the I2C bus supply voltage through a pullup resistor.
PAGE 6
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode VCC CONFIGURATION AND TIMING REGISTER INPUT/OUTPUT CONTROLLER I2C INTERFACE CONTROLLER SDA SCL T-TIME OSC SLPZ STATUS REGISTER GND READ DATA REGISTER LINE XCVR IO DS2484 Figure 1. Block Diagram Table 1.
PAGE 7
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode Active Pullup (APU) The APU bit controls whether an active pullup (low impedance transistor) or a passive pullup (RWPU resistor) is used to drive a 1-Wire line from low to high. When APU = 0, active pullup is disabled (resistor mode). Enabling active pullup is generally recommended for best 1-Wire bus performance. The active pullup does not apply to the rising edge of a recovery after a short on the 1-Wire line.
PAGE 8
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode case), the SPU bit in the Device Configuration register is written to 0, or the DS2484 receives the Device Reset command. When the strong pullup ends, the SPU bit is automatically reset to 0. Using the strong pullup feature does not change the state of the APU bit in the Device Configuration register.
PAGE 9
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode Table 3. Status Register Bit Assignment BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 DIR TSB SBR RST LL SD PPD 1WB Status Register The read-only Status register is the general means for the DS2484 to report bit-type data from the 1-Wire side, 1-Wire busy status, and its own reset status to the host processor (Table 3).
PAGE 10
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode Table 4. Port Configuration Register Bit Assignment BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 0 0 VAL3 VAL2 VAL1 VAL0 BITS 3:0 VAL[3:0]: Parameter Value Code See Table 7 for the conversion between binary code and parameter value.
PAGE 11
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode Device Reset Command Code F0h Command Parameter None Description Performs a global reset of device state machine logic. Terminates any ongoing 1-Wire communication. Typical Use Device initialization after power-up; reinitialization (reset) as desired. Restriction None (can be executed at any time) Error Response None Command Duration Maximum 525ns. Counted from falling SCL edge of the command code acknowledge bit.
PAGE 12
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode Write Device Configuration Command Code D2h Command Parameter Configuration Byte Description Writes a new device configuration byte. The new settings take effect immediately. Note: When writing to the Device Configuration register, the new data is accepted only if the upper nibble (bits 7 to 4) is the one’s complement of the lower nibble (bits 3 to 0). When read, the upper nibble is always 0h.
PAGE 13
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode Table 6.
PAGE 14
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode 1-Wire Reset Command Code B4h Command Parameter None Description Generates a 1-Wire reset/presence-detect cycle at the 1-Wire line (Figure 4). The state of the 1-Wire line is sampled at tSI and tMSP and the result is reported to the host processor through the Status register bits PPD and SD. Typical Use To initiate or end any 1-Wire communication sequence.
PAGE 15
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode 1-Wire Single Bit Command Code 87h Command Parameter Bit Byte Description Generates a single 1-Wire time slot with a bit value “V” as specified by the bit byte at the 1-Wire line (Table 8). A V value of 0b generates a write-zero time slot (Figure 5); a V value of 1b generates a write-one time slot, which also functions as a read-data time slot (Figure 6).
PAGE 16
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode tWOL tMSR VCC VIH1 VIL1 0V tF1 tREC0 tSLOT PULLUP (SEE FIGURE 2) DS2484 PULLDOWN Figure 5. Write-Zero Time Slot tMSR tW1L VCC VIH1 VIL1 0V tF1 tSLOT PULLUP (SEE FIGURE 2) DS2484 PULLDOWN 1-Wire SLAVE PULLDOWN NOTE: DEPENDING ON ITS INTERNAL STATE, A 1-Wire SLAVE DEVICE TRANSMITS DATA TO ITS MASTER (e.g., THE DS2484). WHEN RESPONDING WITH A 0, A 1-Wire SLAVE STARTS PULLING THE LINE LOW DURING tW1L.
PAGE 17
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode 1-Wire Write Byte Command Code A5h Command Parameter Data Byte Description Writes a single data byte to the 1-Wire line. Typical Use To write commands or data to the 1-Wire line. Equivalent to executing eight 1-Wire Single Bit commands, but faster due to less I2C traffic. Restriction 1-Wire activity must have ended before the DS2484 can process this command.
PAGE 18
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode 1-Wire Triplet Command Code 78h Command Parameter Direction Byte Description Generates three time slots: two read time slots and one write time slot at the 1-Wire line. The type of write time slot depends on the result of the read time slots and the direction byte. The direction byte determines the type of write time slot if both read time slots are 0 (a typical case).
PAGE 19
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode MSB FIRST MSB LSB MSB LSB SDA SLAVE ADDRESS SCL R/W 1–7 IDLE ACK 8 9 START CONDITION DATA 1–7 ACK 8 REPEATED IF MORE BYTES ARE TRANSFERRED 9 DATA 1–7 ACK/ NACK 8 9 STOP CONDITION REPEATED START Figure 7. I2C Protocol Overview 7-BIT SLAVE ADDRESS A6 A5 A4 A3 A2 A1 A0 0 0 1 1 0 0 0 R/W DETERMINES READ OR WRITE MSB Figure 8.
PAGE 20
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode I2C Definitions The following terminology is commonly used to describe I2C data transfers. See Figure 9 for a timing diagram. Bus Idle or Not Busy: Both SDA and SCL are inactive and in their logic-high states. START Condition: To initiate communication with a slave, the master must generate a START condition. A START condition is defined as a change in state of SDA from high to low while SCL remains high.
PAGE 21
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode Not Acknowledged by Slave: A slave device could be unable to receive or transmit data, e.g., because it is busy performing a real-time function or is in sleep mode. In this case, the slave device does not acknowledge its slave address and leaves the SDA line high. A slave device that is ready to communicate acknowledges at least its slave address. However, some time later the slave can refuse to accept data, e.g.
PAGE 22
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode I2C Communication Examples (continued) Device Reset (After Power-Up) S AD,0 A DRST A Sr AD,1 A A\ P Activities that are underlined denote an optional read access to verify the success of the command. Set Read Pointer (To Read from Another Register) Case A: Valid Read Pointer Code S AD,0 A SRP A C3h A P C3h is the read pointer code for the Device Configuration register.
PAGE 23
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode I2C Communication Examples (continued) Verifying the 1-Wire port configuration The Adjust 1-Wire Port command sets the read pointer to the Port Configuration register. If other commands were issued to the DS2484 since then, use the Set Read Pointer command first to position the read pointer to the Port Configuration register.
PAGE 24
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode I2C Communication Examples (continued) 1-Wire Single Bit (To Generate a Single Time Slot on the 1-Wire Line) Case A: 1-Wire Idle (1WB = 0), No Busy Polling S AD,0 A 1WSB A A P (Idle) S AD,1 A A\ P The idle time is needed for the 1-Wire function to complete. Then access the device in read mode to get the result from the 1-Wire Single Bit command.
PAGE 25
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode I2C Communication Examples (continued) 1-Wire Read Byte (To Read a Byte from the 1-Wire Line) Case A: 1-Wire Idle (1WB = 0), No Busy Polling, Set Read Pointer After Idle Time S AD,0 A 1WRB A P (Idle) S AD,0 A SRP A E1h A Sr AD,1 A A\ P The idle time is needed for the 1-Wire function to complete.
PAGE 26
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode I2C Communication Examples (continued) 1-Wire Triplet (To Perform a Search ROM Function on 1-Wire Line) Case A: 1-Wire Idle (1WB = 0), No Busy Polling S AD,0 A 1WT A A P (Idle) S AD,1 A A\ P The idle time is needed for the 1-Wire function to complete. Then access the device in read mode to get the result from the 1-Wire Triplet command.
PAGE 27
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode Applications Information SDA and SCL Pullup Resistors must not exceed 300ns. Assuming maximum rise time, the maximum resistor value at any given capacitance CB is calculated as: RP(MAX) = 300ns/(CB x ln(7/3)). For a bus capacitance of 400pF, the maximum pullup resistor would be 885I.
PAGE 28
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode Package Information Ordering Information PART TEMP RANGE PIN-PACKAGE DS2484R+T -40NC to +85NC 6 SOT23 (3k pieces) DS2484Q+T -40NC to +85NC 8 TDFN-EP* (2.5k pieces) +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. *EP = Exposed pad. Maxim Integrated For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages.
PAGE 29
DS2484 Single-Channel 1-Wire Master with Adjustable Timing and Sleep Mode Revision History REVISION NUMBER REVISION DATE 0 5/13 DESCRIPTION Initial release PAGES CHANGED — Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time.