DS26303 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26303 is an 8-channel short-haul line interface unit (LIU) that supports E1/T1/J1 from a single 3.3V power supply. A wide variety of applications are supported through internal termination or external termination. A single bill of material can support E1/T1/J1 with minimum external components.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit TABLE OF CONTENTS 1 DETAILED DESCRIPTION ...............................................................................................................6 2 TELECOM SPECIFICATIONS COMPLIANCE.................................................................................7 3 BLOCK DIAGRAMS .........................................................................................................................9 4 PIN DESCRIPTION ...........
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 7.1.5 7.1.6 7.1.7 7.1.8 7.1.9 7.1.10 7.1.11 7.1.12 7.1.13 7.1.14 7.1.15 7.1.16 7.2 INSTRUCTION REGISTER ................................................................................................................76 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.3 Shift-DR............................................................................................................................................... 73 Exit1-DR......................
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit LIST OF FIGURES Figure 3-1. Block Diagram ........................................................................................................................................... 9 Figure 3-2. Receive Logic Detail................................................................................................................................ 10 Figure 3-3. Transmit Logic Detail...................................................................
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit LIST OF TABLES Table 2-1. T1-Related Telecommunications Specifications ........................................................................................ 7 Table 2-2. E1-Related Telecommunications Specifications ........................................................................................ 8 Table 4-1. Pin Descriptions................................................................................................................
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 1 DETAILED DESCRIPTION The DS26303 is a single-chip, 8-channel, short-haul line interface unit (LIU) for T1 (1.544Mbps) and E1 (2.048Mbps) applications. Eight independent receivers and transmitters are provided in an eLQFP package. The LIUs can be individually selected for T1, J1, or E1 operation. The LIU requires a single reference clock called MCLK. MCLK can be either 1.544MHz or 2.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 2 TELECOM SPECIFICATIONS COMPLIANCE The DS26303 LIU meets all the relevant latest telecommunications specifications. Table 2-1 provides the T1 specifications and Table 2-2 provides the E1 specifications for the relevant sections applicable to the DS26303. Table 2-1. T1-Related Telecommunications Specifications ANSI T1.102–Digital Hierarchy Electrical Interface AMI Coding B8ZS Substitution Definition DS1 Electrical Interface.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Table 2-2. E1-Related Telecommunications Specifications ITU-T G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces Defines the 2048kbps bit rate: 2048 ±50ppm. The transmission media are 75Ω coax or 120Ω twisted pair; peak-topeak space voltage is ±0.237V; nominal pulse width is 244ns. Return loss: 51Hz to 102Hz is 6dB, 102Hz to 3072Hz is 8dB, 2048Hz to 3072Hz is 14dB Nominal peak voltage is 2.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 3 BLOCK DIAGRAMS Figure 3-1. Block Diagram TYPICAL OF ALL 8 CHANNELS T1CLK E1CLK MUX Jitter Attenuator MUX 2.048MHz to 1.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit LOS EZDE Figure 3-2. Receive Logic Detail RCLK RCLK Excessive Zero Detect T1.231 IAISEL POS AISEL NEG EN RPOS ENCV RNEG/CV BPV/CV/EXZ MCLK LASCS SRMS AIS Detector G.775, ETSI 300233, T1.231 CVDEB ENCODE LCS CODE ENCODE B8ZS/HDB3/AMI Decoder (G.703, T1.102) BPVs, Code Violatiions (T1.231, O.161) MUX NRZ Data All Ones Insert (AIS) BEIR ENCODE SRMS LCS CODE Figure 3-3. Transmit Logic Detail B8ZS/HDB3/AMI Coder (G.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 4 PIN DESCRIPTION Table 4-1.
DS26303: 3.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit NAME PIN RNEG1/CV1 41 RNEG2/CV2 34 RNEG3/CV3 76 RNEG4/CV4 69 RNEG5/CV5 112 RNEG6/CV6 105 RNEG7/CV7 4 RNEG8/CV8 141 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 39 32 78 71 110 103 6 143 MCLK 10 TYPE FUNCTION Receive Negative-Data Output for Channel 1 to 8/Code Violation for Channel 1 to 8 O, tri-state RNEG[1:8]: In dual-rail mode, this output indicates a negative pulse on RTIPn/RRINGn.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit NAME PIN TYPE FUNCTION CLKA 93 O, tri-state Clock A. This output becomes a programmable clock output when enabled (MC.CLKAE is set). For frequency options, see the CCR register. This option is not available in hardware mode. If this option is not used, the pin should be left unconnected. N.C. 94 I (pulled to VSS) No Connection. Pin should be left unconnected or grounded. HARDWARE AND PORT OPERATION Mode Selection.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit NAME PIN TYPE FUNCTION Serial Clock/Address Latch Enable/Address Strobe Bar/Template Selection 2 SCLK: In the serial host mode, this pin is the serial clock. Data on SDI is clocked on the rising edge of SCLK. The data is clocked on SDO on the rising edge of SCLK if CLKE is high. If CLKE is low the data on SDO is clocked on the falling edge of SCLK.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit NAME PIN TYPE FUNCTION Serial Data Out/Ready Output/Acknowledge Bar/Receive Impedance Off SDO/RDY/ACKB/ RIMPOFF SDO: In serial host mode, the SDO data is output on this pin. If a serial write is in progress this pin is in high impedance. During a read SDO is high impedance when SDI is in command/ address mode. If CLKE is low, SDO is output on the rising edge of SCLK, if CLKE is high, SDO is output on the falling edge.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit NAME PIN A4/RIMPMSB 12 A3/GMC3 13 A2/GMC2 14 A1/GMC1 15 A0/GMC0 OE CLKE TYPE Address Bus 4–0/G.772 Monitoring Control/Rx Impedance Mode Select A[4:0]: These five pins are address pins in parallel host mode. In serial host mode and multiplexed host mode, these pins should be grounded.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit NAME PIN TYPE FUNCTION DVDD DVSS VDDIO VSSIO 19 20 17, 92 18, 91 — — — — 3.3V Digital Power Supply Digital Ground 3.3V I/O Power Supply I/O Ground TVDD1 44 TVDD2 53 TVDD3 56 TVDD4 65 — 3.3V Power Supply for the Transmitter — Analog Ground for Transmitters POWER SUPPLIES TVDD5 116 TVDD6 125 TVDD7 128 TVDD8 137 TVSS1 47 TVSS2 50 TVSS3 59 TVSS4 62 TVSS5 119 TVSS6 122 TVSS7 131 TVSS8 134 AVDD 90 — 3.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Figure 4-1.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 4.1 Hardware and Host Port Operation 4.1.1 Hardware Mode The DS26303 supports a hardware configuration mode that allows the user to configure the device through setting levels on the device’s pins. This mode allows the configuration of the DS26303 without the use of a microprocessor. Not all of the device features are supported in the hardware mode. To see all available options for this hardware mode, see the pin descriptions in Table 4-1.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 4.1.2 Serial Port Operation Setting MODESEL = VDDIO/2 enables the serial bus interface on the DS26303. Port read/write timing is unrelated to the system transmit and receive timing, allowing asynchronous reads or writes by the host. See Section 10.3 for the AC timing of the serial port. All serial port accesses are LSB first. See Figure 4-2 to Figure 4-4. This port is compatible with the SPI interface defined for Motorola processors.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Figure 4-4. Serial Port Operation for Read Access with CLKE = 1 SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CSB SDI 0 SDO A1 A2 A3 A4 A5 X A6 (msb) (lsb) D0 D1 D2 (lsb) 4.1.3 D3 D4 D5 D6 D7 (msb) Parallel Port Operation When using the parallel interface on the DS26303 the user has the option for either multiplexed bus operation or non-multiplexed bus operation.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Figure 4-5.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 5 REGISTERS Five address bits are used to control the settings of the registers. AD[4:0] are used in both the parallel nonmultiplexed mode and in multiplexed mode. In serial mode, the address is input serially on SDI. The register space contains control for channels 1 to 8 from address 00 hex to 1F hex. The ADDP (1F) register is used as a pointer to access the different banks of registers.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Table 5-2.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Table 5-4.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Table 5-5.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Table 5-7.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 5.1 Register Description This section details the register description of each bit. Whenever the variable “n” in italics is used in any of the register descriptions, it represents 1, 2, 3, 4, 5, 6, 7, and 8. 5.1.1 Primary Registers Register Name: Register Description: Register Address: Bit # Name 7 ID7 ID Identification Register 00h 6 ID6 5 ID5 4 ID4 3 ID3 2 ID2 1 ID1 0 ID0 Bit 7: Device CODE ID Bit 7 (ID7).
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default 7 TAOE8 0 TAOE Transmit All-Ones Enable Register 03h 6 TAOE7 0 5 TAOE6 0 4 TAOE5 0 3 TAOE4 0 2 TAOE3 0 1 TAOE2 0 0 TAOE1 0 Bits 7 to 0: Transmit All-Ones Enable Channel n (TAOEn). When this bit is set, a continuous stream of all ones is sent on channel n (TTIPn and TRINGn). MCLK is used as a reference clock for the transmit all-ones signal.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default 7 DFMIE8 0 DFMIE Driver Fault Monitor Interrupt Enable Register 07h 6 DFMIE7 0 5 DFMIE6 0 4 DFMIE5 0 3 DFMIE4 0 2 DFMIE3 0 1 DFMIE2 0 0 DFMIE1 0 Bits 7 to 0: Driver Fault Monitor Interrupt Enable Channel n (DFMIEn). When this bit is set, a change in DFM status can generate an interrupt in monitor n.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default 7 BERTDIR 0 GMC G.772 Monitoring Control Register 0Bh 6 BMCKS 0 5 BTCKS 0 4 — 0 3 GMC3 0 2 GMC2 0 1 GMC1 0 0 GMC0 0 Bit 7: BERT Direction Select (BERTDIR). When set, the internal BERT will output its data on RPOS/RNEG rather than TTIP/TRING. The BERT will use the recovered clock unless BMCKS or BTCKS is set. Bit 6: BERT MCLK Select (BMCKS).
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default 7 DLBC8 0 DLBC Digital Loopback Configuration Register 0Ch 6 DLBC7 0 5 DLBC6 0 4 DLBC5 0 3 DLBC4 0 2 DLBC3 0 1 DLBC2 0 0 DLBC1 0 Bits 7 to 0: Digital Loopback Configuration Channel n (DLBCn). When this bit is set, the LIUn is placed in digital loopback. The data at TPOSn/TNEGn is encoded and looped back to the decoder and output on RPOSn/RNEGn.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default 7 ATAOS8 0 ATAOS Automatic Transmit All-Ones Select Register 0Eh 6 ATAOS7 0 5 ATAOS6 0 4 ATAOS5 0 3 ATAOS4 0 2 ATAOS3 0 1 ATAOS2 0 0 ATAOS1 0 Bit 7 to 0: Automatic Transmit All-Ones Select Channel n (ATAOSn). When this bit is set an all-ones signal is sent if a loss of signal is detected for LIUn. The all-ones signal uses MCLK as the reference clock.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default TST Template Select Transceiver Register 10h 7 — 0 6 — 0 5 — 0 4 — 0 3 — 0 2 TST2 0 1 TST1 0 0 TST0 0 Bits 2 to 0: TST Template Select Transceiver [2:0] (TST [2:0]). TST[2:0] is used to select the transceiver that the transmit template select register (hex 11) applies to. See Table 5-10. Table 5-10.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default 7 OEB8 0 OEB Output-Enable Bar Register 12h 6 OEB7 0 5 OEB6 0 4 OEB5 0 3 OEB4 0 2 OEB3 0 1 OEB2 0 0 OEB1 0 Bits 7 to 0: Output-Enable Bar Channel n (OEBn). When this bit is set the transmitter output for LIUn is placed in high impedance. Note that when the OE pin is low, it overrides the setting of this register.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default 7 AISIE8 0 AISIE AIS Interrupt Enable Register 14h 6 AISIE7 0 5 AISIE6 0 4 AISIE5 0 3 AISIE4 0 2 AISIE3 0 1 AISIE2 0 0 AISIE1 0 Bits 7 to 0: AIS Interrupt Mask Channel n (AISIEn). When this bit is set, interrupts can be generated for LIUn if AIS status transitions.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 5.1.2 Secondary Registers Register Name: Register Description: Register Address: Bit # Name Default 7 SRMS8 0 SRMS Single-Rail Mode Select Register 00h 6 SRMS7 0 5 SRMS6 0 4 SRMS5 0 3 SRMS4 0 2 SRMS3 0 1 SRMS2 0 0 SRMS1 0 Bits 7 to 0: Single-Rail Mode Select Channel n (SRMSn). When this bit is set, single-rail mode is selected for the system transmit and receive n. If this bit is reset, dual-rail mode is selected.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default 7 EZDE8 0 EZDE Excessive Zero Detect Enable Register 05h 6 EZDE7 0 5 EZDE6 0 4 EZDE5 0 3 EZDE4 0 2 EZDE3 0 1 EZDE2 0 0 EZDE1 0 Bits 7 to 0: Excessive Zero Detect Enable Channel n (EZDEn). When this bit is reset, excessive zero detection is disabled for LIUn. When this bit is set, excessive zero detect is enabled.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 5.1.3 Individual LIU Registers Register Name: Register Description: Register Address: Bit # Name Default 7 IJAE8 0 IJAE Individual Jitter Attenuator Enable Register 00h 6 IJAE7 0 5 IJAE6 0 4 IJAE5 0 3 IJAE4 0 2 IJAE3 0 1 IJAE2 0 0 IJAE1 0 Bits 7 to 0: Individual Jitter Attenuator Enable Channel n (IJAEn). When this bit is set, the LIUn jitter attenuator is enabled. Note that if the GC.JAE bit is set, this register is ignored.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default 7 ISCPD8 0 ISCPD Individual Short-Circuit Protection Disabled Register 04h 6 ISCPD7 0 5 ISCPD6 0 4 ISCPD5 0 3 ISCPD4 0 2 ISCPD3 0 1 ISCPD2 0 0 ISCPD1 0 Bits 7 to 0: Individual Short-Circuit Protection Disabled n (ISCPDn). When this bit is set, the short-circuit protection is disabled for the individual transmitter of LIUn. Note that if the GC.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 MC Master Clock Select Register 06h 6 PCLKI 0 5 TECLKE 0 4 CLKAE 0 3 MPS1 0 2 MPS0 0 1 FREQS 0 0 PLLE 0 Bit 6: PLL Clock Input (PCLKI). This bit selects the input into to the PLL. 0 = MCLK is used. 1 = RCLK[1:8] is used based on the selection in register CCR. Bit 5: T1/E1 Clock Enable (TECLKE). When this bit is set the TECLK output is enabled.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 GMR Global Management Register 07h 6 — 0 5 — 0 4 — 0 3 — 0 2 JABWS1 0 1 JABWS0 0 0 RHPMC 0 Bits 2 to 1: Jitter Attenuator Bandwidth Select [1:0] (JABWS[1:0]). These bits JABWS[1:0] select the jitter attenuator bandwidth. See Table 5-14 for details. Table 5-14. Jitter Attenuator Bandwidth Selections JABWS[1:0] 00 01 10 11 BANDWIDTH CORNER 0.625Hz 1.25Hz 2.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default 7 LVDS8 0 LVDS Line Violation Detect Status Register 12h 6 LVDS7 0 5 LVDS6 0 4 LVDS5 0 3 LVDS4 0 2 LVDS3 0 1 LVDS2 0 0 LVDS1 0 Bits 7 to 0: Line Violation Detect Status n (LVDSn). A bipolar violation, code violation, or excessive zeros cause the associated LVDSn bit to latch. This bit is cleared on a read operationif GISC.CWE is reset.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default 7 PCLKS2 0 CCR Clock Control Register 15h 6 PCLKS1 0 5 PCLKS0 0 4 TECLKS 0 3 CLKA3 0 2 CLKA2 0 1 CLKA1 0 0 CLKA0 0 Bits 7 to 5: PLL Clock Select (PCLKS[2:0]). These bits determine the RCLK that is to be used as the input to the PLL. If an LOS is detected for the channel that RCLK is recovered from, the PLL switches to MCLK until the LOS is cleared.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default 7 RDULR8 0 RDULR RCLK Disable Upon LOS Register 16h 6 RDULR7 0 5 RDULR6 0 4 RDULR5 0 3 RDULR4 0 2 RDULR3 0 1 RDULR2 0 0 RDULR1 0 Bits 7 to 0: RCLK Disable Upon LOS Register n (RDULRn). When this bit is set the RCLKn is disabled upon a loss of signal and set as a low output. When reset, RCLKn switches to MCLK within 10ms of a loss of signal.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 5.1.4 BERT Registers Register Name: Register Description: Register Address: Bit # Name Default 7 PMUM 0 BCR BERT Control Register 00h 6 LPMU 0 5 RNPL 0 4 RPIC 0 3 MPR 0 2 APRD 0 1 TNPL 0 0 TPIC 0 Bit 7: Performance-Monitoring Update Mode (PMUM). When 0, a performance-monitoring update is initiated by the LPMU register bit. When 1, a performance-monitoring update is initiated by the receive performance-monitoring update signal (RPMU).
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 BPCR1 BERT Pattern Configuration Register 1 02h 6 QRSS 0 5 PTS 0 4 PLF4 0 3 PLF3 0 2 PLF2 0 1 PLF1 0 0 PLF0 0 Bit 6: QRSS Enable (QRSS). When 0, the pattern generator configuration is controlled by PTS, PLF[4:0], and PTF[4:0], and BSP[31:0]. When 1, the pattern generator configuration is forced to a PRBS pattern with a generating polynomial of x20 + x17 + 1.
DS26303: 3.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TEICR Transmit Error-Insertion Control Register 08h 6 — 0 5 TEIR2 0 4 TEIR1 0 3 TEIR0 0 2 BEI 0 1 TSEI 0 0 MEIMS 0 Bits 5 to 3: Transmit Error-Insertion Rate (TEIR[2:0]). These bits indicate the rate at which errors are inserted in the output data stream. One out of every 10n bits is inverted. TEIR[2:0] is the value n.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 BSRL BERT Status Register Latched Register 0Eh 6 — 0 5 — 0 4 — 0 3 PMSL 0 2 BEL 0 1 BECL 0 0 OOSL 0 Bit 3: Performance-Monitoring Update Status Latched (PMSL). This bit is set when the PMS bit transitions from 0 to 1. A read operation clears this bit. Bit 2: Bit Error Latched (BEL). This bit is set when a bit error is detected.
DS26303: 3.
DS26303: 3.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 6 FUNCTIONAL DESCRIPTION 6.1 Power-Up and Reset Internal power-on-reset circuitry generates a reset during power-up. All registers are reset to the default values. Writing to the software-reset register generates at least a 1μs reset cycle, which has the same effect as the powerup reset. 6.2 Master Clock The receiver uses the MCLK as a reference for clock recovery, jitter attenuation, and generating RCLKn during LOS.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 6.3 Transmitter NRZ data arrives on TPOSn and TNEGn on the transmit system side. The TPOSn and TNEGn data is sampled on the falling edge of TCLKn (Figure 10-12). The data is encoded with HDB3 or B8ZS or AMI encoding when single-rail mode is selected (only TDATn as the data source). When in single-rail mode only, BPV errors can be inserted for test purposes by register BEIR. Encoded data is expected when dual-rail mode is selected.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 6.3.1 Transmit Line Templates The DS26303 the transmitters can be selected individually to meet the pulse masks for E1 and T1/J1 mode. The T1/J1 pulse mask is shown in the transmit pulse template and can be configured on an individual LIU basis. The TIMPRM pin/bit is used to select the internal transmit terminating impedance of 100Ω/110Ω for T1/J1 mode or 75Ω/120Ω for E1 mode.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Figure 6-3. E1 Transmit Pulse Templates 1.2 1.1 269ns SCALED AMPLITUDE (in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 1.0 0.9 0.8 0.7 G.703 Template 194ns 0.6 0.5 219ns 0.4 0.3 0.2 0.1 0 -0.1 -0.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 6.3.2 LIU Transmit Front-End It is recommended to configure the transmitter’s LIU as described in Figure 6-4 and in Table 6-4. No series resistors are required. The transmitter has internal termination for E1, J1, and T1 modes. Figure 6-4. LIU Front-End 3.3V TFt 1:2 Dt TVDDn C1 TTIP Dt C2 Tx Line Ct Dt TVSSn TRING Dt DS26303 (One Channel) 3.3V AVDDn C3 TFr 1:2 RTIP Rt C4 A75 A100 A110 AVSSn 30 C5 Rx Line Rt RRING 3.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 6.3.3 Dual-Rail Mode Dual-rail mode consists of TPOSn, TNEGn, and TCLKn pins on the system side. data is sampled on the falling edge of TCLKn as shown in Figure 10-12. The data that appears on the TPOSn pin is output on TTIPn and data on the TNEGn is output on TRINGn after pulse shaping. The single-rail-select register (SRMS) is used for selection of dual-rail or single-rail mode.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 6.4.3 Loss of Signal The DS26303 uses both the digital and analog loss-detection method in compliance with the latest ANSI T1.231 for T1/J1 and ITU-T G.775 (LASCS.LASCSn reset) or ETS 300 233 (LASCS.LASCSn set) for E1 mode of operation. LOS is detected if the receiver level falls bellow a threshold analog voltage for a certain duration. Alternatively, this can be termed as having received zeros for a certain duration.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Table 6-6. AIS Criteria T1.231, G.775, and ETS 300 233 Specifications CRITERIA STANDARD ETS 300 233 FOR E1 ITU-T G.775 FOR E1 AIS Detection Two or fewer 0s in each of two consecutive 512-bit streams received. Fewer than three 0s detected in 512-bit period. AIS Clearance Three or more 0s in each of two consecutive 512-bit streams received. Three or more 0s in a 512-bit period received. ANSI T1.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 6.4.5 Bipolar Violation and Excessive Zero Detector The DS26303 detects code violations, BPV, and excessive zero errors. The reporting of the errors is done through the pin RNEGn/CVn. Excessive zeros are detected if eight consecutive 0s are detected with B8ZS enabled and four consecutive 0s are detected with HDB3 enabled. Excessive zero detection is selectable when single-rail mode and HDB3/B8ZS encoding/decoding is selected.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Figure 6-5. HPS Logic D SET CLR OEB Q int_oe_off Q OE D SET Rint_imp_off Q RHPMC CLR D SET CLR Q Q RIMPOFF Q hw/sw mode RIMPOFF Figure 6-6.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 6.6 Jitter Attenuator The DS26303 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits by the JADS bit in register GC. It can also be controlled on an individual LIU basis by settings in the IJAFDS register. The 128bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delaysensitive applications.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 6.7 G.772 Monitor In this application, only seven LIUs are functional and one LIU is used for nonintrusive monitoring of input and output of the other seven channels. Channel 1 is used for monitoring channels 2 to 8. G.772 monitoring is configured by the GMC register (see Table 5-9). While monitoring with channel 1, the device can be configured in remote loopback and the monitored signal can be output on TTIP1 and TRING1. 6.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Figure 6-9. Digital Loopback TCLK TPOS TNEG RCLK RPOS RNEG 6.8.3 H D B 3 / B 8 Z S E n c o d e r H D B 3 / B 8 Z S D e c o d e r TPOS O p tio n a l J itt e r A tte n u a to r O p t io n a l J it te r A tte n u a to r T r a n s m it D ig it a l R e c e iv e D ig i ta l T ra n s m it A n a lo g Line Driver TNEG RTIP R e c e iv e A n a lo g RRING Remote Loopback The inputs at RTIPn and RRINGn are looped back to TTIPn and TRINGn.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 6.8.4 Dual Loopback A dual loopback is created by enabling both a remote loopback and a digital loopback. The transmit system data TPOSn, TNEGn, and TCLKn are looped back to output on RCLKn, RPOSn, and RNEGn. The inputs at RTIPn and RRINGn are looped back to TTIPn and TRINGn. This loopback is conceptually shown in Figure 6-11. Figure 6-11.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 6.9 BERT The BERT is a software-programmable test-pattern generator and monitor capable of meeting most errorperformance requirements for digital transmission equipment. It generates and synchronizes to pseudorandom patterns with a generation polynomial of the form xn + xy + 1, where n and y can take on values from 1 to 32 and to repetitive patterns of any length up to 32 bits.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit After configuring these bits, the pattern must be loaded into the BERT. This is accomplished through a 0-to-1 transition on BCR.TNPL and BCR.RNPL Monitoring the BERT requires reading the BSR register that contains the BEC bit and the OOS bit. The BEC bit is 1 when the bit-error counter is 1 or more.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Figure 6-12. PRBS Synchronization State Diagram Sync th wi its wit ho its ut 4b err ors f6 6o 32 b ors err 1 bit error Verify Load 32 bits loaded 6.9.3.2 Receive Repetitive Pattern Synchronization Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Figure 6-13. Repetitive Pattern Synchronization State Diagram Sync th wi its wi tho its ut 4b err ors f6 6o 32 b ors err 1 bit error Verify Match Pattern Matches 6.9.3.3 Receive Pattern Monitoring Receive pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts the incoming bits.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 7 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT The DS26303 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26303 contains the following as required by IEEE 1149.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 7.1 TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of TCLK. The state diagram is shown in Figure 7-2. 7.1.1 Test-Logic-Reset Upon power-up, the TAP controller will be in the Test-Logic-Reset state. The instruction register will contain the IDCODE instruction. All system logic of the device will operate normally.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 7.1.10 Select-IR-Scan All test registers retain their previous state. The instruction register will remain unchanged during this state. With JTMS LOW, a rising edge on TCLK moves the controller into the Capture-IR state and will initiate a scan sequence for the instruction register. JTMS HIGH during a rising edge on TCLK puts the controller back into the Test-LogicReset state. 7.1.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Figure 7-2.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 7.2 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on TCLK with JTMS LOW will shift the data one stage towards the serial output at JTDO.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Table 7-2. ID Code Structure MSB Version Contact Factory 4 bits Device ID JEDEC LSB 1 16 bits 00010100001 1 Table 7-3 Device ID Codes PART DS26303-075 DS26303-125 7.3 DIE REV A1 A1 JTAG REV 0h 0h JTAG ID 0080h 0081h Test Registers IEEE 1149.1 requires a minimum of two test registers: the Bypass Register and the Boundary Scan Register. An optional test register has been included with the DS26303 design.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 8 OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to VSS (except VDD)…………………………………………….-0.3V to +5.5V Supply Voltage (VDD) Range with Respect to VSS………..…………………………………………………-0.3V to +3.63V Operating Temperature Range for DS26303L…………….…...……………………………………………...0°C to +70°C Operating Temperature Range for DS26303LN……………….
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 9 THERMAL CHARACTERISTICS Table 9-1. Thermal Characteristics PARAMETER MIN TYP MAX UNITS Power Dissipation with RIMPMS = 0 (Notes 1, 2) 0.7 1.40 W Power Dissipation with RIMPMS = 1(Notes 1, 2) 0.9 1.65 W +85 °C +125 °C Ambient Temperature (Note 3) -40 Junction Temperature Theta-JA (θJA) in Still Air for 144-Pin LQFP with Exposed Pad +21.3 (Note 4) 29.0 (Note 5) °C/W Note 1: RCLK1-n = TCLK1-n = 1.544MHz.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 10 AC CHARACTERISTICS 10.1 Line Interface Characteristics Table 10-1. Transmitter Characteristics PARAMETER SYMBOL Output Mark Amplitude V Output Zero Amplitude (Note 1) Vs CONDITIONS E1 75Ω E1 120Ω T1 100Ω T1 110Ω MIN TYP MAX UNITS 2.14 2.7 2.4 2.4 2.37 3.0 3.0 3.0 2.6 3.3 3.6 3.6 V -0.3 +0.3 V -1 +1 % Transmit Amplitude Variation with Supply Transmit Path Delay Single-rail 8 Dual-rail 3 UI Table 10-2.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 10.2 Parallel Host Interface Timing Characteristics Table 10-3. Intel Read Mode Characteristics (VDD = 3.3V ±5%, Tj = -40°C to +125°C.) (Note 1) (See Figure 10-1 and Figure 10-2.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Figure 10-1.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Figure 10-2.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Table 10-4. Intel Write Cycle Characteristics (VDD = 3.3V ±5%, Tj = -40°C to +125°C.) (Note 1) (See Figure 10-3 and Figure 10-4.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Figure 10-3.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Figure 10-4.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Table 10-5. Motorola Read Cycle Characteristics (VDD = 3.3V ±5%, Tj = -40°C to +125°C.) (Note 1) (See Figure 10-5 and Figure 10-6.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Figure 10-5.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Figure 10-6.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Table 10-6. Motorola Write Cycle Characteristics (VDD = 3.3V ±5%, Tj = -40°C to +125°C.) (Note 1) (See Figure 10-7 and Figure 10-8.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Figure 10-7.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Figure 10-8.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 10.3 Serial Port Table 10-7. Serial Port Timing Characteristics (See Figure 10-9, Figure 10-10, and Figure 10-11.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 10.4 System Timing Table 10-8. Transmitter System Timing (See Figure 10-12.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX TPOS, TNEG Setup Time with Respect to TCLK Falling Edge t1 40 ns TPOS, TNEG Hold Time with Respect to TCLK Falling Edge t2 40 ns TCLK Pulse-Width High TCLK Pulse-Width Low t3 t4 75 75 ns ns TCLK Period t5 TCLK Rise Time TCLK Fall Time t6 t7 488 648 ns 25 25 Figure 10-12.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit Table 10-9. Receiver System Timing (See Figure 10-13.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Delay RCLK to RPOS, RNEG Valid Delay RCLK to RNEG Valid in SinglePolarity Mode t1 50 ns t2 50 ns RCLK Pulse-Width High t3 75 ns RCLK Pulse-Width Low t4 75 ns RCLK Period t5 488 648 Figure 10-13.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 10.5 JTAG Timing Table 10-10. JTAG Timing Characteristics (See Figure 10-14.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS JTCLK Period t1 100 ns JTMS and JTDI Setup to JTCLK t2 25 ns JTMS and JTDI Hold to JTCLK t3 25 ns JTCLK to JTDO Hold t4 50 Figure 10-14.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 11 PIN CONFIGURATION 11.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 12 PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 12.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 12.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit 13 DOCUMENT REVISION HISTORY REVISION 072205 DESCRIPTION New product release. Removed references to 160-ball PBGA package. 060606 Deleted Special Test Functions and Metal Options sections (formerly Section 6.10 and 6.10.1). Updated Package Drawing in Section 11. 082306 Corrected various typos.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit REVISION DESCRIPTION (Page 30) LOSS: added missing “S” to bit names (from LOS[8:1] to LOSS[8:1]); DFMS: changed bit description for bits 7 to 0. (Page 31) LOSIS: changed bit description for bits 7 to 0; DFMIS: changed bit description for bits 7 to 0. (Page 33) DLBC: changed register description from Digital Loopback Control to Digital Loopback Configuration and added note to bits 7 to 0 description.