DESIGN KIT AVAILABLE DS26504 T1/E1/J1/64KCC BITS Element www.maxim-ic.com GENERAL DESCRIPTION The DS26504 is a building-integrated timing-supply (BITS) clock-recovery element. It also functions as a basic T1/E1 transceiver. The receiver portion can recover a clock from T1, E1, 64kHz composite clock (64KCC), and 6312kHz synchronization timing interfaces. In T1 and E1 modes, the Synchronization Status Message (SSM) can also be recovered.
DS26504 T1/E1/J1/64KCC BITS Element TABLE OF CONTENTS 1. FEATURES .......................................................................................................................7 1.1 1.2 1.3 1.4 1.5 1.6 GENERAL .....................................................................................................................................7 LINE INTERFACE ...........................................................................................................................
DS26504 T1/E1/J1/64KCC BITS Element 8. T1 FRAMER/FORMATTER CONTROL REGISTERS ....................................................40 8.1 9. T1 CONTROL REGISTERS............................................................................................................40 E1 FRAMER/FORMATTER CONTROL REGISTERS....................................................46 9.1 9.2 E1 CONTROL REGISTERS ...........................................................................................................
DS26504 T1/E1/J1/64KCC BITS Element 17.5 18. IDENTIFICATION REGISTER ........................................................................................................108 FUNCTIONAL TIMING DIAGRAMS .............................................................................111 18.1 PROCESSOR INTERFACE ...........................................................................................................111 18.1.1 18.1.2 Parallel Port Mode...................................................
DS26504 T1/E1/J1/64KCC BITS Element LIST OF FIGURES Figure 3-1. Block Diagram ......................................................................................................................................... 11 Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) ......................................................................................... 12 Figure 3-3. Transmit PLL Clock Mux Diagram ........................................................................................................
DS26504 T1/E1/J1/64KCC BITS Element LIST OF TABLES Table 2-1. T1-Related Telecommunications Specifications ........................................................................................ 9 Table 2-2. E1-Related Telecommunications Specifications ...................................................................................... 10 Table 5-1. LQFP Pinout .............................................................................................................................................
DS26504 T1/E1/J1/64KCC BITS Element 1. FEATURES 1.1 General 64-pin, 10mm x 10mm LQFP package 3.3V supply with 5V tolerant inputs and outputs Evaluation kits IEEE 1149.1 JTAG Boundary Scan Driver source code available from the factory 1.2 Line Interface Requires a single master clock (MCLK) for E1, T1, or J1 operation. Master clock can be 2.048MHz, 4.096MHz, 8.192MHz, 12.8MHz (available in CPU-interface mode only), or 16.384MHz. Option to use 1.544MHz, 3.088MHz, 6.176MHz, or 12.
DS26504 T1/E1/J1/64KCC BITS Element 1.4 Framer/Formatter Fully independent transmit and receive functionality Full receive and transmit path transparency T1 framing formats include D4 and ESF Detailed alarm and status reporting with optional interrupt support RCL, RLOS, and RAIS alarms interrupt on change of state Japanese J1 support includes: − Ability to calculate and check CRC6 according to the Japanese standard − Ability to generate yellow alarm according to the Japanese standard 1.
DS26504 T1/E1/J1/64KCC BITS Element 2. SPECIFICATIONS COMPLIANCE The DS26504 meets all applicable sections of the latest telecommunications specifications including those listed in the following tables. Table 2-1. T1-Related Telecommunications Specifications ANSI T1.102: Digital Hierarchy Electrical Interface ANSI T1.231: Digital Hierarchy–Layer 1 In-Service Performance Monitoring ANSI T1.
DS26504 T1/E1/J1/64KCC BITS Element Table 2-2. E1-Related Telecommunications Specifications ITUT G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces ITUT G.736 Characteristics of Synchronous Digital Multiplex Equipment operating at 2048kbps ITUT G.742 Second-Order Digital Multiplex Equipment Operating at 8448kbps ITUT G.772 ITUT G.775 ITUT G.823 The control of jitter and wander within digital networks, which are based on 2.
DS26504 T1/E1/J1/64KCC BITS Element 3. BLOCK DIAGRAMS Figure 3-1.
DS26504 T1/E1/J1/64KCC BITS Element Figure 3-2. Loopback Mux Diagram (T1/E1 Modes Only) CLOCK FROM RX LIU RCLK JITTER ATTENUATOR ENABLED AND IN RX PATH + DATA TO RX FRAMER + DATA - DATA - DATA LOCAL LOOPBACK (LBCR.3) TX CLOCK CLOCK TO TX LIU JITTER ATTENUATOR ENABLED AND IN TX PATH + DATA + DATA FROM TX FORMATTER - DATA - DATA REMOTE LOOPBACK (LBCR.4) Figure 3-3. Transmit PLL Clock Mux Diagram TPCR.3 TPCR.4 TPCR.6 TPCR.7 IN SEL OUT SEL TPCR.5 TPCR.
DS26504 T1/E1/J1/64KCC BITS Element Figure 3-4.
DS26504 T1/E1/J1/64KCC BITS Element 4. PIN FUNCTION DESCRIPTION 4.1 Transmit PLL NAME TYPE PLL_OUT O TCLK I FUNCTION Transmit PLL Output. This pin can be selected to output the 1544kHz, 2048kHz, 64kHz, or 6312kHz output from the internal TX PLL or the internal signal, TX CLOCK. See Figure 3-3 and Figure 3-4. Transmit Clock Input. A 64kHz, 1.544MHz, 2.048MHz, or 6312kHz primary clock.
DS26504 T1/E1/J1/64KCC BITS Element 4.3 Receive Side NAME TYPE RCLK O RS_8K O 400HZ O RSER O RLOF_CCE O RLOS O FUNCTION Receive Clock. Recovered 1.544MHz (T1), 2.048MHz (E1), 6312 kHz (G.703 Synchronization Interface), or 64kHz (Composite Clock) clock. Payload Mode: When payload mode is enabled, this pin outputs a gapped clock based on the internal RCLK. In T1 operation, the clock is gapped during the Fbit position. In E1 mode, the clock is gapped during time slots 0 and 16.
DS26504 T1/E1/J1/64KCC BITS Element NAME TYPE RAIS O FUNCTION Receive Alarm Indication Signal T1 Mode: Toggles high when the receive Blue Alarm is detected. E1 Mode: Toggles high when the receive AIS is detected. 64KCC Mode: This pin is in a high-impedance state. 6312kHz Mode: This pin is in a high-impedance state. 4.
DS26504 T1/E1/J1/64KCC BITS Element NAME TYPE AD[6]/ TITD I/O AD[5]/ RMODE1 AD[4]/ RMODE0 FUNCTION Data Bus D[6] or Address/Data Bus AD[6]/Transmit Internal Termination Disable A[6]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data bus D[6]. AD[6]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the multiplexed address/data bus AD[6]. TITD: In Hardware Mode (BIS[1:0] = 11), internal transmit termination is disabled when TITD = 1.
DS26504 T1/E1/J1/64KCC BITS Element NAME TYPE AD[1]/ RMODE3/ MOSI I/O AD[0]/ TCSS0/ MISO FUNCTION Data Bus D[1] or Address/Data Bus AD[1]/Receive Mode Select 3/Master Out-Slave In A[1]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data bus D[1]. AD[1]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the multiplexed address/data bus AD[1]. RMODE3: In Hardware Mode (BIS[1:0] = 11), this pin selects the receive side operating mode.
DS26504 T1/E1/J1/64KCC BITS Element NAME TYPE A4/CPHA/ L2 I FUNCTION Address Bus Bit A[4]/Serial Port Clock Phase Select/Line Build-Out Select 2 A4: In nonmultiplexed bus operation (BIS[1:0] = 01), this pin serves as A[4]. In multiplexed bus operation (BIS[1:0] = 00), these pins are not used and should be tied low. CPHA: In Serial Port Mode (BIS[1:0] = 10), this pin selects the serial port clock phase. See the functional timing diagrams for the Serial Port Interface.
DS26504 T1/E1/J1/64KCC BITS Element NAME TYPE RD(DS)/ RMODE2 I CS/ RLB I ALE (AS)/ A7/MPS1 I WR (R/W)/ TMODE3 FUNCTION Active-Low Read Input-Data Strobe/Receive Mode Select Bit 2 RD (DS): DS is active high when BIS[1:0] = 01. See the bus timing diagrams. RMODE2: In Hardware Mode (BIS[1:0] = 11), this pin selects the receive side operating mode. Active-Low Chip Select/Remote Loopback Enable CS: This active-low signal must be low to read or write to the device.
DS26504 T1/E1/J1/64KCC BITS Element 4.6 Line Interface NAME TYPE MCLK I RTIP I RRING I TTIP O TRING O THZE I FUNCTION Master Clock Input. A (50ppm) clock source. This clock is used internally for both clock/data recovery and the jitter attenuator for both T1 and E1 modes. A quartz crystal can be applied across MCLK and XTALD rather than the clock source. The clock rate can be 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz. When using the DS26504 in T1-only operation, a 1.
DS26504 T1/E1/J1/64KCC BITS Element 5. PINOUT Table 5-1.
DS26504 T1/E1/J1/64KCC BITS Element O O O I PARALLEL PORT TCLKO TNEGO TPOSO TSER MODE SERIAL PORT TCLKO TNEGO TPOSO TSER 23 I/O TS_8K_4 TS_8K_4 TS_8K_4 25 O RCLK RCLK RCLK 26 O RS_8K RS_8K RS_8K 27 28 29 30 O O O O 400HZ RSER RAIS RLOF_CCE 400HZ RSER RAIS RLOF_CCE 400HZ RSER RAIS RLOF_CCE 31 I — — TCSS1 32 33 34 35 36 37 38 39 40, 43, 45 41 42 44 O I I I I O I I RLOS JTMS JTCLK JTRST JTDI JTDO RVDD TSTRST RLOS JTMS JTCLK JTRST JTDI JTDO RVDD TSTRST RLOS JTMS JTCLK JTRST JTDI
DS26504 T1/E1/J1/64KCC BITS Element MODE SERIAL PORT BIS1 HARDWARE I PARALLEL PORT BIS1 60 I CS CS RLB 61 I RD (DS) — RMODE2 62 I WR (R/W) — TMODE3 63 I/O AD0 MISO TCSS0 64 I/O AD1 MOSI RMODE3 PIN TYPE 59 BIS1 24 of 129 FUNCTION Bus Interface Select Mode 1 Parallel Port Mode: Chip Select (Active Low) Serial Port Mode: Chip Select (Active Low) Hardware Mode: Remote Loopback Enable Parallel Port Mode: Read Input (Data Strobe), Active Low Serial Port Mode: Unused, should be co
DS26504 T1/E1/J1/64KCC BITS Element 6. HARDWARE CONTROLLER INTERFACE In Hardware Controller mode, the parallel and serial port pins are reconfigured to provide direct access to certain functions in the port. Only a subset of the device’s functionality is available in hardware mode. Each register description throughout the data sheet indicates the functions that may be controlled in hardware mode and several alarm indicators that are available in both hardware and processor mode.
DS26504 T1/E1/J1/64KCC BITS Element 6.3 Line Build-Out Table 6-3. E1 Line Build-Out L2 PIN 13 0 0 1 1 L1 PIN 12 0 0 0 0 L0 PIN 11 0 1 0 1 1 1 0 1 1 1 APPLICATION 75Ω normal 120Ω normal 75Ω with high return loss (Note 2) 120Ω with high return loss (Note 2) 75Ω normal + enable transmit and receive gapped clock 120Ω normal + enable transmit and receive gapped clock N (Note 1) 1:2 1:2 1:2 1:2 RETURN LOSS N.M. N.M. 21dB 21dB Rt (Note 1) 0 0 6.2Ω 11.6Ω 1:2 N.M 0 1:2 N.
DS26504 T1/E1/J1/64KCC BITS Element 6.4 Receiver Operating Modes Table 6-5. Receive Path Operating Mode RMODE3 PIN 64 0 0 0 0 0 0 0 0 1 1 RMODE2 PIN 61 0 0 0 0 1 1 1 1 0 0 RMODE1 PIN 4 0 0 1 1 0 0 1 1 0 0 RMODE0 PIN 3 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 RECEIVE PATH OPERATING MODE T1 D4 Framing Mode T1 ESF Framing Mode J1 D4 Framing Mode J1 ESF Framing Mode E1 FAS Framing Mode E1 CAS Framing Mode E1 CRC4 Framing Mode E1 CAS and CRC4 Framing Mode E1 G.
DS26504 T1/E1/J1/64KCC BITS Element 6.6 MCLK Pre-Scaler Table 6-7. MCLK Pre-Scaler for T1 Mode MPS1 PIN 16 0 0 1 1 0 0 1 1 MPS0 PIN 15 0 1 0 1 0 1 0 1 JACKS0 PIN 46 0 0 0 0 1 1 1 1 MCLK (MHz) 1.544 3.088 6.176 12.352 2.048 4.096 8.192 16.384 Table 6-8. MCLK Pre-Scaler for E1 Mode MPS1 PIN 16 0 0 1 1 MPS0 PIN 15 0 1 0 1 JACKS0 PIN 46 0 0 0 0 MCLK (MHz) 2.048 4.096 8.192 16.384 6.
DS26504 T1/E1/J1/64KCC BITS Element 6.8 Other Hardware Controller Mode Features Table 6-9. Other Operational Modes PIN RSM PIN 1 TSM PIN 2 RLB PIN 60 TAIS PIN 10 HBE PIN 55 DESCRIPTION RS_8K Mode Select: Selects frame or multiframe pulse at RS_8K pin. 0 = frame mode 1 = multiframe mode TS_8K_4 Mode Select: In T1 or E1 operation, selects frame or multiframe mode for the TS_8K_4 pin.
DS26504 T1/E1/J1/64KCC BITS Element 7. PROCESSOR INTERFACE The DS26504 is controlled via a nonmultiplexed (BIS[1:0] = 01) or a multiplexed (BIS[1:0] = 00) parallel bus. There is also a serial bus mode option, as well as a hardware mode of operation. The bus interface type is selected by BIS1 and BIS0 as shown in Table 7-1. Table 7-1. Port Mode Select BIS1 0 0 1 1 BIS0 0 1 0 1 PORT MODE Parallel Port Mode (Multiplexed) Parallel Port Mode (Nonmultiplexed) Serial Port Mode (SPI) Hardware Mode 7.
DS26504 T1/E1/J1/64KCC BITS Element are terminated when CS is removed. If CS is removed before all 8 bits of the data are read, the remaining data will be lost. If CS is removed before all 8 bits of data are written to the part, no write access will occur and the target register will not be updated. Note: During a Burst-Read access, data must be fetched internally to the part as the LSB of the previous byte is transmitted out.
DS26504 T1/E1/J1/64KCC BITS Element 7.3 Register Map Table 7-2.
DS26504 T1/E1/J1/64KCC BITS Element ADDRESS TYPE 42 43 44 45 46 47 48 49 4A 4B-4F 50 51 52 53 54-55 56 57 58 59 5A 5B 5C 5D 5E 5F 60-EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF R/W R/W R/W R/W R/W R/W R/W R/W R/W — R R/W R/W R/W — R R R R R R R R R R — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W REGISTER NAME Transmit Si Align Frame Transmit Si Non-Align Frame Transmit Remote Alarm Bits Transmit Sa4 Bits Transmit Sa5 Bits Transmit Sa6 Bits Transmit Sa7 Bits Transmit Sa8 Bits
DS26504 T1/E1/J1/64KCC BITS Element 7.3.1 Power-Up Sequence The DS26504 contains an on-chip power-up reset function that automatically clears the writeable register space immediately after power is supplied to the device. The user can issue a chip reset at any time. Issuing a reset will disrupt signals flowing through the DS26504 until the device is reprogrammed. The reset can be issued through hardware using the TSTRST pin or through software using the SFTRST function in the master mode register.
DS26504 T1/E1/J1/64KCC BITS Element 7.3.3 Mode Configuration Register Register Name: Register Description: Register Address: Bit # Name Default HW Mode 7 TMODE3 0 TMODE3 PIN 62 MCREG Mode Configuration Register 08h 6 TMODE2 0 TMODE2 PIN 48 5 TMODE1 0 TMODE1 PIN 49 4 TMODE0 0 TMODE0 PIN 14 3 RMODE3 0 RMODE3 PIN 64 2 RMODE2 0 RMODE2 PIN 61 1 RMODE1 0 RMODE1 PIN 4 0 RMODE0 0 RMODE0 PIN 3 Bits 0 to 3: Receive Mode Configuration (RMODE[0:3]).
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode TPCR1 Transmit PLL Control Register 1 09h 7 TPLLOFS1 0 6 TPLLOFS0 0 5 PLLOS 0 4 TPLLIFS1 0 3 TPLLIFS0 0 2 TPLLSS 0 0 0 0 0 0 0 1 TCSS1 0 TCSS1 PIN 31 0 TCSS0 0 TCSS0 PIN 63 For more information on all the bits in the Transmit PLL control register, refer to Figure 3-3. Bits 0 and 1: Transmit Clock (TX CLOCK) Source Select (TCSS[0:1]).
DS26504 T1/E1/J1/64KCC BITS Element Register Name: TPCR2 Register Description: Register Address: Transmit PLL Control Register 2 0Ah Bit # Name Default 7 — 6 — 5 — 4 — 3 — 2 — 1 TPLLOFS2 0 0 TPLLIFS2 0 Bit 0: Transmit Clock Source Select (TPLLOFS2). This bit, along with TPLLOFS0 (TPCR1.7) and TPLLOFS1 (TPCR1.6), is used to indicate the reference frequency being input to the TX PLL. See the table in TPCR1 register description. Bit 1: Transmit Clock Source Select (TPLLIFS2).
DS26504 T1/E1/J1/64KCC BITS Element individually poll certain bits without disturbing the other bits in the register. This operation is key in controlling the DS26504 with higher-order languages. Status register bits are divided into two groups: condition bits and event bits. Condition bits are typically network conditions such as loss of frame or all-ones detect. Event bits are typically markers such as the one-second timer. Each status register bit is labeled as a condition or event bit.
DS26504 T1/E1/J1/64KCC BITS Element 7.7 Interrupt Information Registers The Interrupt Information Registers (IIRs) provide an indication of which Status Registers (SR1 to SR4) are generating an interrupt. When an interrupt occurs, the host can read IIR to quickly identify which of the four status registers are causing the interrupt.
DS26504 T1/E1/J1/64KCC BITS Element 8. T1 FRAMER/FORMATTER CONTROL REGISTERS The T1 framer portion of the DS26504 is configured via a set of five control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS26504 has been initialized, the control registers only need to be accessed when there is a change in the system configuration.
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: T1RCR2 T1 Receive Control Register 2 04h Bit # Name Default HW Mode 7 — 0 6 — 0 0 0 5 RB8ZS 0 HBE PIN 55 4 — 0 3 — 0 2 — 0 1 RJC 0 0 RD4YM 0 0 0 0 0 0 Bit 0: Receive Side D4 Yellow Alarm Select (RD4YM) 0 = zeros in bit 2 of all channels 1 = a one in the S-bit position of frame 12 (J1 Yellow Alarm Mode) Bit 1: Receive Japanese CRC6 Enable (RJC) 0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode 7 TJC 0 RMODEx PINS T1TCR1 T1 Transmit Control Register 1 05h 6 TFPT 0 5 TCPT 0 4 — 0 3 — 0 2 — 0 1 — 0 0 TYEL 0 0 0 0 0 0 0 0 Bit 0:Transmit Yellow Alarm (TYEL) 0 = do not transmit yellow alarm 1 = transmit yellow alarm Bits 1 to 4: Unused, must be set = 0 for proper operation.
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode 7 TB8ZS 0 HBE PIN 55 T1TCR2 T1 Transmit Control Register 2 06h 6 TFSE 1 5 — 0 4 FBCT2 0 3 FBCT1 0 2 TD4YM 0 1 — 0 0 TB7ZS 0 1 0 0 0 0 0 0 Bit 0: Transmit-Side Bit 7 Zero-Suppression Enable (TB7ZS) 0 = no stuffing occurs 1 = bit 7 forced to a 1 in channels with all 0s Bits 1 and 5: Unused, must be set = 0 for proper operation.
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode T1CCR T1 Common Control Register 07h 7 — 0 6 — 0 5 — 0 4 TRAI-CI 0 3 TAIS-CI 0 2 — 0 1 PDE 0 0 — 0 0 0 0 0 0 0 0 0 Bits 0, 2, 5, 6, 7: Unused, must be set = 0 for proper operation. Bit 1: Pulse-Density Enforcer Enable (PDE). The framer always examines the transmit and receive data streams for violations of these, which are required by ANSI T1.403.
DS26504 T1/E1/J1/64KCC BITS Element Table 8-1. T1 Alarm Criterion ALARM SET CRITERION CLEAR CRITERION Blue Alarm (AIS) (Note 1) Over a 3ms window, five or fewer zeros are received Over a 3ms window, six or more zeros are received D4 Yellow Alarm (RAI) (T1RCR2.0 = 0) Bit 2 of 256 consecutive channels is set to zero for at least 254 occurrences Bit 2 of 256 consecutive channels is set to zero for less than 254 occurrences Japanese Yellow Alarm (T1RCR2.
DS26504 T1/E1/J1/64KCC BITS Element 9. E1 FRAMER/FORMATTER CONTROL REGISTERS The E1 framer portion of the DS26504 is configured via a set of two control registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS26504 has been initialized, the control registers only need to be accessed when there is a change in the system configuration. There is one receive control register (E1RCR) and one transmit control register (E1TCR).
DS26504 T1/E1/J1/64KCC BITS Element Table 9-1. E1 Sync/Resync Criterion FRAME OR MULTIFRAME LEVEL FAS CRC4 CAS SYNC CRITERION RESYNC CRITERION FAS present in frame N and N + 2, and FAS not present in frame N + 1 Two valid MF alignment words found within 8ms Valid MF alignment word found and previous time slot 16 contains code other than all zeros Three consecutive incorrect FAS received Alternate: (E1RCR.
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: E1TCR E1 Transmit Control Register 1Eh Bit # Name Default HW Mode 7 TFPT 0 6 — 0 5 ARA 0 4 TsiS 0 3 AEBE 0 2 TUA1 0 0 0 0 0 0 0 1 THDB3 0 HBE PIN 55 0 AAIS 0 Bit 0: Automatic AIS Generation (AAIS) 0 = disabled 1 = enabled Bit 1: Transmit HDB3 Enable (THDB3) 0 = HDB3 disabled 1 = HDB3 enabled Bit 2: Transmit Unframed All Ones (TUA1) 0 = transmit data normally 1 = transmit an unframed all-ones code to L
DS26504 T1/E1/J1/64KCC BITS Element 9.2 E1 Information Registers Register Name: Register Description: Register Address: INFO2 Information Register 2 12h Bit # Name Default HW Mode 7 — 0 6 — 0 5 — 0 4 — 0 3 — 0 2 CRCRC 0 1 FASRC 0 0 CASRC 0 X X X X X X X X Bit 0: CAS Resync Criterion Met Event (CASRC). Set when two consecutive CAS MF alignment words are received in error. Bit 1: FAS Resync Criterion Met Event (FASRC). Set when three consecutive FAS words are received in error.
DS26504 T1/E1/J1/64KCC BITS Element Table 9-2. E1 Alarm Criterion ALARM SET CRITERION RLOF An RLOF condition exists on power-up prior to initial synchronization, when a resync criterion has been met, or when a manual resync has been initiated via E1RCR.0 255 or 2048 consecutive zeros received as determined by E1RCR.
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode SR2 Status Register 2 16h 7 RYELC 0 6 RAISC 0 5 RLOSC 0 4 RLOFC 0 3 RYEL 0 X X X X X 2 RAIS 0 RAIS PIN 29 1 RLOS 0 RLOS PIN 32 0 RLOF 0 LOF PIN 30 Bit 0: Receive Loss-of-Frame Condition (RLOF). Set when the DS26504 is not synchronized to the received data stream. Bit 1: Receive Loss-of-Signal Condition (RLOS). Set when 255 (or 2048 if E1RCR.
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode IMR2 Interrupt Mask Register 2 17h 7 RYELC 0 6 RAISC 0 5 RLOSC 0 4 RLOFC 0 3 RYEL 0 2 RAIS 0 1 RLOS 0 0 RLOF 0 X X X X X X X X Bit 0: Receive Loss-of-Frame Condition (RLOF) 0 = interrupt masked 1 = interrupt enabled–interrupts on rising edge only Bit 1: Receive Loss-of-Signal Condition (RLOS) 0 = interrupt masked 1 = interrupt enabled–interrupts on rising edge only Bit 2: R
DS26504 T1/E1/J1/64KCC BITS Element 10. I/O PIN CONFIGURATION OPTIONS Register Name: Register Description: Register Address: IOCR1 I/O Configuration Register 1 01h Bit # Name Default HW Mode 7 G703TE 0 6 RSMS2 0 0 0 5 RSMS1 0 RSM PIN 1 4 RLOFF 0 CSM_TSDW 3 0 0 0 2 TSM 0 TSM PIN 2 1 TSIO 0 0 ODF 0 0 0 Bit 0: Output Data Format (ODF) 0 = bipolar data at TPOS and TNEG 1 = NRZ data at TPOS; TNEG = 0 Bit 1: TS_8K_4 I/O Select (TSIO).
DS26504 T1/E1/J1/64KCC BITS Element Table 10-1. TS_8K_4 Pin Functions TRANSMIT MODE T1/E1 T1/E1 T1/E1 T1/E1 64KCC 64KCC 64KCC 64KCC IOCR1.3 IOCR1.2 IOCR1.1 TS_8K_4 FUNCTION 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 0 1 0 1 0 1 Frame sync input Frame sync output Multiframe sync input Multiframe sync output 8kHz input reference 8kHz output reference 400Hz input reference 400Hz output reference Table 10-2. RLOF_CCE Pin Functions RECEIVE MODE T1/E1 T1/E1 64KCC IOCR1.
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode IOCR2 I/O Configuration Register 2 02h 7 RCLKINV 6 TCLKINV 5 RS_8KINV 0 0 0 0 4 TS_8K_4INV 3 — 2 — 1 TPCOE 0 RPCOE 0 0 0 0 0 0 0 0 0 0 0 0 Bit 0: Receive Payload Clock Output Enable (RPCOE). Setting this bit enables a gapped receive clock at the RCLK pin. In E1 mode, the clock is gapped during TS0 and TS16. In T1 mode, the clock is gapped during the F-Bit.
DS26504 T1/E1/J1/64KCC BITS Element 11. T1 SYNCHRONIZATION STATUS MESSAGE The DS26504 has a BOC controller to handle SSM services in T1 mode. Table 11-1.
DS26504 T1/E1/J1/64KCC BITS Element 11.3 Receive BOC The receive BOC function is enabled by setting BOCC.4 = 1. The RFDL register will now operate as the receive BOC message and information register. The lower six bits of the RFDL register (BOC message bits) are preset to all ones. When the BOC bits change state, the BOC change of state indicator, SR3.0, alerts the host. The host then reads the RFDL register to get the BOC message.
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: BOCC BOC Control Register 1Fh Bit # Name Default HW Mode 7 — 0 6 — 0 5 — 0 4 RBOCE 0 3 RBR 0 2 RBF1 0 1 RBF0 0 0 SBOC 0 0 0 0 0 0 0 0 0 Bit 0: Send BOC (SBOC). Set = 1 to transmit the BOC code placed in bits 0 to 5 of the TFDL register. Bits 1 and 2: Receive BOC Filter Bits (RBF0, RBF1).
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: RFDL (RFDL register bit usage when BOCC.4 = 1) Receive FDL Register 50h Bit # Name Default HW Mode 7 — 0 6 — 0 5 RBOC5 0 4 RBOC4 0 3 RBOC3 0 2 RBOC2 0 1 RBOC1 0 0 RBOC0 0 0 0 0 0 0 0 0 0 Bit 0: BOC Bit 0 (RBOC0) Bit 1: BOC Bit 1 (RBOC1) Bit 2: BOC Bit 2 (RBOC2) Bit 3: BOC Bit 3 (RBOC3) Bit 4: BOC Bit 4 (RBOC4) Bit 5: BOC Bit 5 (RBOC5) Bits 6 and 7: This bit position is unused when BOCC.4 = 1.
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode SR3 Status Register 3 18h 7 — 0 6 LOTC 0 5 BOCC 0 4 RFDLAD 0 3 RFDLF 0 2 TFDLE 0 1 RMTCH 0 0 RBOC 0 X X X X X X X X Bit 0: Receive BOC Detector Change-of-State Event (RBOC). Set whenever the BOC detector sees a change of state to a valid BOC. The setting of this bit prompts the user to read the RFDL register. Bit 1: Receive FDL Match Event (RMTCH).
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode IMR3 Interrupt Mask Register 3 19h 7 — 0 6 LOTC 0 5 BOCC 0 4 RFDLAD 0 3 RFDLF 0 2 TFDLE 0 1 RMTCH 0 0 RBOC 0 X X X X X X X X Bit 0: Receive BOC Detector Change-of-State Event (RBOC) 0 = interrupt masked 1 = interrupt enabled Bit 1: Receive FDL Match Event (RMTCH) 0 = interrupt masked 1 = interrupt enabled Bit 2: TFDL Register Empty Event (TFDLE) 0 = interrupt masked 1 = int
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode SR4 Status Register 4 1Ah 7 — 0 6 RSA1 0 5 RSA0 0 4 TMF 0 3 TAF 0 2 RMF 0 1 RCMF 0 0 RAF 0 X X X X X X X X Bit 0: Receive Align Frame Event (RAF). (E1 only) Set every 250µs at the beginning of align frames. Used to alert the host that Si and Sa bits are available in the RAF and RNAF registers. Bit 1: Receive CRC4 Multiframe Event (RCMF).
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode IMR4 Interrupt Mask Register 4 1Bh 7 — 0 6 RSA1 0 5 RSA0 0 4 TMF 0 3 TAF 0 2 RMF 0 1 RCMF 0 0 RAF 0 X X X X X X X X Bit 0: Receive Align Frame Event (RAF) 0 = interrupt masked 1 = interrupt enabled Bit 1: Receive CRC4 Multiframe Event (RCMF) 0 = interrupt masked 1 = interrupt enabled Bit 2: Receive Multiframe Event (RMF) 0 = interrupt masked 1 = interrupt enabled Bit 3: Tra
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode TFDL Transmit FDL Register 51h 7 TFDL7 0 6 TFDL6 0 5 TFDL5 0 4 TFDL4 0 3 TFDL3 0 2 TFDL2 0 1 TFDL1 0 0 TFDL0 0 0 0 0 1 1 1 0 0 Note: Also used to insert Fs framing pattern in D4 framing mode. The transmit FDL register (TFDL) contains the FDL information that is to be inserted on a byte-basis into the outgoing T1 data stream. The LSB is transmitted first.
DS26504 T1/E1/J1/64KCC BITS Element 12. E1 SYNCHRONIZATION STATUS MESSAGE The DS26504 provides access to both the transmit and receive Sa/Si bits. In E1, the Sa bits are used to transmit and receive the SSM. The primary method to access the Sa (and Si) bits is based on CRC4 multiframe access. An alternate method is based on double-frame access. The DS26504 provides an interrupt on a change of state for the Sa-bit-based messages. Table 12-1.
DS26504 T1/E1/J1/64KCC BITS Element 12.1.1 Sa Bit Change of State The DS26504 can provide an interrupt whenever one of the multiframe based Sa bit patterns changes. Using the SR5 and IMR5 registers, the user can enable interrupts on a change of state for Sa4, Sa5, Sa6, Sa7 and Sa8 multiframe bit patterns. This function is useful for monitoring the Sa6-based SSM message.
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: IMR5 Interrupt Mask Register 5 22h Bit # Name Default HW Mode 7 — 0 6 — 0 5 — 0 4 Sa8COS 0 3 Sa7COS 0 2 Sa6COS 0 1 Sa5COS 0 0 Sa4COS 0 X X X X X X X X Bit 0: Sa4 Change of State (Sa4COS) 0 = interrupt masked 1 = interrupt enabled Bit 1: Sa5 Change of State (Sa5COS) 0 = interrupt masked 1 = interrupt enabled Bit 2: Sa6 Change of State (Sa6COS) 0 = interrupt masked 1 = interrupt enabled Bit 3: Sa7 Ch
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode RsiAF Receive Si Bits of the Align Frame 58h 7 SiF0 0 6 SiF2 0 5 SiF4 0 4 SiF6 0 3 SiF8 0 2 SiF10 0 1 SiF12 0 0 SiF14 0 X X X X X X X X Bit 0: Si Bit of Frame 14(SiF14) Bit 1: Si Bit of Frame 12(SiF12) Bit 2: Si Bit of Frame 10(SiF10) Bit 3: Si Bit of Frame 8(SiF8) Bit 4: Si Bit of Frame 6(SiF6) Bit 5: Si Bit of Frame 4(SiF4) Bit 6: Si Bit of Frame 2(SiF2) Bit 7: Si Bit of
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode RRA Receive Remote Alarm 5Ah 7 RRAF1 0 6 RRAF3 0 5 RRAF5 0 4 RRAF7 0 3 RRAF9 0 2 RRAF11 0 1 RRAF13 0 0 RRAF15 0 X X X X X X X X Bit 0: Remote Alarm Bit of Frame 15(RRAF15) Bit 1: Remote Alarm Bit of Frame 13(RRAF13) Bit 2: Remote Alarm Bit of Frame 11(RRAF11) Bit 3: Remote Alarm Bit of Frame 9(RRAF9) Bit 4: Remote Alarm Bit of Frame 7(RRAF7) Bit 5: Remote Alarm Bit of Frame
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode Rsa5 Receive Sa5 Bits 5Ch 7 Rsa5F1 0 6 Rsa5F3 0 5 Rsa5F5 0 4 Rsa5F7 0 3 Rsa5F9 0 2 Rsa5F11 0 1 Rsa5F13 0 0 Rsa5F15 0 X X X X X X X X Bit 0: Sa5 Bit of Frame 15(Rsa5F15) Bit 1: Sa5 Bit of Frame 13(Rsa5F13) Bit 2: Sa5 Bit of Frame 11(Rsa5F11) Bit 3: Sa5 Bit of Frame 9(Rsa5F9) Bit 4: Sa5 Bit of Frame 7(Rsa5F7) Bit 5: Sa5 Bit of Frame 5(Rsa5F5) Bit 6: Sa5 Bit of Frame 3(Rsa5F3
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode Rsa7 Receive Sa7 Bits 5Eh 7 Rsa7F1 0 6 Rsa7F3 0 5 Rsa7F5 0 4 Rsa7F7 0 3 Rsa7F9 0 2 Rsa7F11 0 1 Rsa7F13 0 0 Rsa7F15 0 X X X X X X X X Bit 0: Sa7 Bit of Frame 15(Rsa7F15) Bit 1: Sa7 Bit of Frame 13(Rsa7F13) Bit 2: Sa7 Bit of Frame 11(Rsa7F11) Bit 3: Sa7 Bit of Frame 9(Rsa7F9) Bit 4: Sa7 Bit of Frame 7(Rsa7F7) Bit 5: Sa7 Bit of Frame 5(Rsa7F5) Bit 6: Sa7 Bit of Frame 3(Rsa7F3)
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode TsiAF Transmit Si Bits of the Align Frame 42h 7 TsiF0 0 6 TsiF2 0 5 TsiF4 0 4 TsiF6 0 3 TsiF8 0 2 TsiF10 0 1 TsiF12 0 0 TsiF14 0 0 0 0 0 0 0 0 0 Bit 0: Si Bit of Frame 14(TsiF14) Bit 1: Si Bit of Frame 12(TsiF12) Bit 2: Si Bit of Frame 10(TsiF10) Bit 3: Si Bit of Frame 8(TsiF8) Bit 4: Si Bit of Frame 6(TsiF6) Bit 5: Si Bit of Frame 4(TsiF4) Bit 6: Si Bit of Frame 2(TsiF2) B
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode TRA Transmit Remote Alarm 44h 7 TRAF1 0 6 TRAF3 0 5 TRAF5 0 4 TRAF7 0 3 TRAF9 0 2 TRAF11 0 1 TRAF13 0 0 TRAF15 0 0 0 0 0 0 0 0 0 Bit 0: Remote Alarm Bit of Frame 15(TRAF15) Bit 1: Remote Alarm Bit of Frame 13(TRAF13) Bit 2: Remote Alarm Bit of Frame 11(TRAF11) Bit 3: Remote Alarm Bit of Frame 9(TRAF9) Bit 4: Remote Alarm Bit of Frame 7(TRAF7) Bit 5: Remote Alarm Bit of Fram
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode Tsa5 Transmit Sa5 Bits 46h 7 Tsa5F1 0 6 Tsa5F3 0 5 Tsa5F5 0 4 Tsa5F7 0 3 Tsa5F9 0 2 Tsa5F11 0 1 Tsa5F13 0 0 Tsa5F15 0 0 0 0 0 0 0 0 0 Bit 0: Sa5 Bit of Frame 15(Tsa5F15) Bit 1: Sa5 Bit of Frame 13(Tsa5F13) Bit 2: Sa5 Bit of Frame 11(Tsa5F11) Bit 3: Sa5 Bit of Frame 9(Tsa5F9) Bit 4: Sa5 Bit of Frame 7(Tsa5F7) Bit 5: Sa5 Bit of Frame 5(Tsa5F5) Bit 6: Sa5 Bit of Frame 3(Tsa5F3
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode Tsa7 Transmit Sa7 Bits 48h 7 Tsa7F1 0 6 Tsa7F3 0 5 Tsa7F5 0 4 Tsa7F7 0 3 Tsa7F9 0 2 Tsa7F11 0 1 Tsa7F13 0 0 Tsa7F15 0 0 0 0 0 0 0 0 0 Bit 0: Sa7 Bit of Frame 15(Tsa7F15) Bit 1: Sa7 Bit of Frame 13(Tsa7F13) Bit 2: Sa7 Bit of Frame 11(Tsa7F11) Bit 3: Sa7 Bit of Frame 9(Tsa7F9) Bit 4: Sa7 Bit of Frame 7(Tsa7F7) Bit 5: Sa7 Bit of Frame 5(Tsa7F5) Bit 6: Sa7 Bit of Frame 3(Tsa7F3
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode TSACR Transmit Sa Bit Control Register 4Ah 7 SiAF 0 6 SiNAF 0 5 RA 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 0 0 0 0 0 0 0 0 Bit 0: Additional Bit 8 Insertion Control Bit (Sa8) 0 = do not insert data from the Tsa8 register into the transmit data stream 1 = insert data from the Tsa8 register into the transmit data stream Bit 1: Additional Bit 7 Insertion Control Bit (Sa7) 0
DS26504 T1/E1/J1/64KCC BITS Element 12.2 Alternate Sa/Si Bit Access Based on Double-Frame On the receive side, the RAF and RNAF registers will always report the data as it received in the Sa and Si bit locations. The RAF and RNAF registers are updated on align frame boundaries. The setting of the receive align frame bit in status register 4 (SR4.0) will indicate that the contents of the RAF and RNAF have been updated. The host can use the SR4.0 bit to know when to read the RAF and RNAF registers.
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: RNAF Receive Non-Align Frame Register 57h Bit # Name Default HW Mode 7 Si 0 6 1 0 5 A 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 X X X X X X X X Bit 0: Additional Bit 8 (Sa8) Bit 1: Additional Bit 7 (Sa7) Bit 2: Additional Bit 6 (Sa6) Bit 3: Additional Bit 5 (Sa5) Bit 4: Additional Bit 4 (Sa4) Bit 5: Remote Alarm (A) Bit 6: Frame Nonalignment Signal Bit (1). In normal operation this bit will be = 1.
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: TNAF Transmit Non-Align Frame Register 41h Bit # Name Default 6 1 1 7 Si 0 5 A 0 4 Sa4 0 3 Sa5 0 Bit 0: Additional Bit 8 (Sa8) Bit 1: Additional Bit 7 (Sa7) Bit 2: Additional Bit 6 (Sa6) Bit 3: Additional Bit 5 (Sa5) Bit 4: Additional Bit 4 (Sa4) Bit 5: Remote Alarm (used to transmit the alarm A) Bit 6: Frame Nonalignment Signal Bit (1) Bit 7: International Bit (Si) 79 of 129 2 Sa6 0 1 Sa7 0 0 Sa8 0
DS26504 T1/E1/J1/64KCC BITS Element 13. LINE INTERFACE UNIT (LIU) The LIU in the DS26504 contains three sections: the receiver, which handles clock and data recovery; the transmitter, which generates waveshapes and drives the network line; and the jitter attenuator. These three sections are controlled by the line interface control registers (LIC1–LIC4), which are described below. The DS26504 can switch among T1, J1, E1, and 6312kHz without changing any external circuits.
DS26504 T1/E1/J1/64KCC BITS Element 13.1 LIU Operation The LIU interfaces the T1, E1, 64KCC, and 6312kHz signals to the various types of network media through coupling transformers. The LIU transmit and receive functions are independent. For example, the receiver can be in T1 mode while the transmitter is in E1 mode. The 6312kHz transmission is an exception to the other modes. For transmission, 6312kHz is only available as a 0 to 3.3V signal on the TCLKO pin.
DS26504 T1/E1/J1/64KCC BITS Element 13.2.2 Receive G.703 Section 13 Synchronization Signal The DS26504 can receive a 2.048MHz square-wave synchronization clock as specified in Section 13 of ITU G.703. To use the DS26504 in this mode, set the mode configuration bits in the Mode Configuration Register (MCREG). 13.2.3 Monitor Mode Monitor applications in both E1 and T1 require various flat-gain settings for the receive-side circuitry.
DS26504 T1/E1/J1/64KCC BITS Element The transmit line drive has two modes of operation: fixed gain or automatic gain. In the fixed gain mode, the transmitter outputs a fixed current into the network load to achieve a nominal pulse amplitude. In the automatic gain mode, the transmitter adjusts its output level to compensate for slight variances in the network load. See the Transmit Line Build-Out Control (TLBC) register for details. 13.3.
DS26504 T1/E1/J1/64KCC BITS Element clock/data recovery block or the clock applied at the TCLK pin is adjusted to create a smooth jitter-free clock that is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If the incoming jitter exceeds either 120UIP-P (buffer depth is 128 bits) or 28UIP-P (buffer depth is 32 bits), then the DS26504 will divide the internal nominal 32.
DS26504 T1/E1/J1/64KCC BITS Element 13.
DS26504 T1/E1/J1/64KCC BITS Element T1 Mode L2 L1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 L0 0 1 0 1 0 1 0 1 APPLICATION DSX-1 (0 to 133 feet)/0dB CSU DSX-1 (133 to 266 feet) DSX-1 (266 to 399 feet) DSX-1 (399 to 533 feet) DSX-1 (533 to 655 feet) Reserved Reserved Reserved N (Note 1) 1:2 1:2 1:2 1:2 1:2 — — — RETURN LOSS N.M. N.M. N.M. N.M. N.M. — — — Rt (Note 1) 0 0 0 0 0 — — — N.M. = Not meaningful Note 1: Transformer turns ratio.
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode LIC2 Line Interface Control 2 31h 7 JACKS1 0 6 LIRST 0 5 IBPV 0 0 0 0 4 TAIS 0 TAIS PIN 10 3 JACKS0 0 JACKS0 PIN 46 2 RCCFE 0 1 SCLD 0 0 CLDS 0 0 0 0 Bit 0: Custom Line-Driver Select (CLDS). Setting this bit to a one redefines the operation of the transmit line driver. When this bit is set to a one and LIC1.5 = LIC1.6 = LIC1.
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode LIC3 Line Interface Control 3 32h 7 CMIE 0 6 CMII 0 5 EX133 0 4 MM1 0 3 MM0 0 2 — 0 1 — 0 0 TAOZ 0 0 0 0 0 0 0 0 0 Bit 0: Transmit Alternate Ones and Zeros (TAOZ). Transmit a …101010… pattern at TTIP and TRING. 0 = disabled 1 = enabled Bits 1 and 2: Unused, must be set = 0 for proper operation. Bits 3 and 4: Monitor Mode (MM0 and MM1).
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: Bit # Name Default HW Mode 7 MPS1 0 MPS1 PIN 16 LIC4 Line Interface Control 4 33h 6 MPS0 0 MPS0 PIN 15 5 TT2 0 4 TT1 0 3 TT0 0 2 RT2 0 1 RT1 0 0 RT0 0 — — — — — — Bits 0 to 2: Receive Termination Select (RT0 to RT2) EX133 EXTERNAL RT2 RT1 RT0 (LIC3.
DS26504 T1/E1/J1/64KCC BITS Element Bits 6 and 7: MCLK Prescaler (MPS0 and MPS1) (E1 Mode) MCLK JACKS0 MPS1 MPS0 (MHz) (LIC2.3) 2.048 0 0 0 4.096 0 1 0 8.192 1 0 0 12.8 0 0 0 16.384 1 1 0 JACKS1 (LIC2.7) 0 0 0 1 0 Register Name: Register Description: Register Address: INFO1 Information Register 1 11h Bit # Name Default HW Mode 7 — 0 6 — 0 5 — 0 4 — 0 3 RL3 0 2 RL2 0 1 RL1 0 0 RL0 0 X X X X X X X X Bits 0 to 3: Receive Level Bits (RL0 to RL3). Real-time bits.
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: SR1 Status Register 1 14h Bit # Name Default HW Mode 7 — 0 6 — 0 5 — 0 4 JALT 0 3 — 0 2 TCLE 0 1 TOCD 0 0 — 0 X X X X X X X X Bits 0, 3, 5, 6, 7: Unused, must be set = 0 for proper operation. Bit 1: Transmit Open-Circuit-Detect Condition (TOCD). Set when the device detects that the TTIP and TRING outputs are open-circuited.
DS26504 T1/E1/J1/64KCC BITS Element Register Name: Register Description: Register Address: IMR1 Interrupt Mask Register 1 15h Bit # Name Default HW Mode 7 — 0 6 — 0 5 — 0 4 JALT 0 3 — 0 2 TCLE 0 1 TOCD 0 0 — 0 X X X X X X X X Bits 0, 3, 5, 6, 7: Unused, must be set = 0 for proper operation.
DS26504 T1/E1/J1/64KCC BITS Element 13.8 Recommended Circuits Figure 13-4. Software-Selected Termination, Metallic Protection 3.3 V 10uF T1 F1 TX TIP T3 DVDD TTIP 0.01 uF S1 S3 TRING TX RING 2:1 DS26504 68 uF 3.3 V T2 F2 RX TIP RTIP T4 TVDD 0.1 uF TVSS S2 S4 RVDD RX RING RRING 1:1 60 0.1 uF RVSS 60 0.1 uF Table 13-1. Component List (Software-Selected Termination, Metallic Protection) NAME F1 and F2 S1 and S2 S3 andS4 T1 and T2 T3 and T4 Note 1: Note 2: Note 3: Note 4: 0.
DS26504 T1/E1/J1/64KCC BITS Element Figure 13-5. Software-Selected Termination, Longitudinal Protection F1 TX TIP 3.3 V 10uF T1 T3 DVDD TTIP S3 0.01 uF S1 0.1 uF DVSS S7 S4 TX RING TRING 2:1 F2 DS26504 68 uF 3.3 V F3 RX TIP T2 RTIP T4 S5 RVDD S6 RX RING RRING F4 0.1 uF TVSS S2 S8 TVDD 1:1 60 0.1 uF RVSS 60 0.1 uF Table 13-2.
DS26504 T1/E1/J1/64KCC BITS Element 13.9 Component Specifications Table 13-3. Transformer Specifications SPECIFICATION Turns Ratio 3.3V Applications Primary Inductance Leakage Inductance Intertwining Capacitance Transmit Transformer DC Resistance Primary (Device Side) Secondary Receive Transformer DC Resistance Primary (Device Side) Secondary RECOMMENDED VALUE 1:1 (receive) and 1:2 (transmit) ±2% 600μH minimum 1.0μH maximum 40pF maximum 1.0Ω maximum 2.0Ω maximum 1.2Ω maximum 1.
DS26504 T1/E1/J1/64KCC BITS Element Figure 13-6. E1 Transmit Pulse Template 1.2 1.1 269ns SCALED AMPLITUDE (in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 1.0 0.9 0.8 0.7 G.703 Template 194ns 0.6 0.5 219ns 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 -200 -150 -100 -50 0 50 100 150 200 250 TIME (ns) Figure 13-7. T1 Transmit Pulse Template 1.2 1.0 -0.77 -0.39 -0.27 -0.27 -0.12 0.00 0.27 0.35 0.93 1.16 0.9 0.8 0.
DS26504 T1/E1/J1/64KCC BITS Element Figure 13-8. Jitter Tolerance (T1 Mode) 1K UNIT INTERVALS (UIpp) DS26504 DS26502 TOLERANCE Tolerance 100 TR 62411 (Dec. 90) 10 ITU-T G.823 1 0.1 1 10 100 1K 10K 100K FREQUENCY (Hz) Figure 13-9. Jitter Tolerance (E1 Mode) UNIT INTERVALS (UIpp) 1k DS26504 DS26502 TOLERANCE Tolerance 100 40 10 1.5 1 0.1 Minimum Tolerance Level as per ITU G.823 1 10 20 100 1k FREQUENCY (Hz) 97 of 129 0.2 2.
DS26504 T1/E1/J1/64KCC BITS Element Figure 13-10. Jitter Attenuation (T1 Mode) -20dB C ve ur A TR 62411 (Dec. 90) Prohibited Area -40dB rve Cu JITTER ATTENUATION (dB) 0dB B DS26502 DS26504 T1 T1MODE MODE -60dB 1 10 100 1K FREQUENCY (Hz) 10K 100K JITTER ATTENUATION (dB) Figure 13-11. Jitter Attenuation (E1 Mode) 0dB ITU G.
DS26504 T1/E1/J1/64KCC BITS Element 14. LOOPBACK CONFIGURATION Register Name: Register Description: Register Address: LBCR Loopback Control Register 20h Bit # Name Default HW Mode 7 — 0 6 — 0 5 — 0 4 — 0 3 LLB 0 0 0 0 0 0 2 RLB 0 RLB PIN 60 1 — 0 0 — 0 0 0 Bits 0, 1, 4 to 7: Unused, must be set = 0 for proper operation. Bit 2: Remote Loopback (RLB). In this loopback, data received at RTIP and RRING will be looped back to the transmit LIU.
DS26504 T1/E1/J1/64KCC BITS Element 15. 64KHZ SYNCHRONIZATION INTERFACE The 64kHz synchronization interface conforms to Appendix II of G.703. It consists of a composite clock, where a 64kHz clock signal is generated or decoded, along with embedded frequencies of 8kHz and 400Hz. Those signals consist of AMI code with an 8kHz bipolar violation removed at every 400Hz.
DS26504 T1/E1/J1/64KCC BITS Element 15.2 Transmit 64kHz Synchronization Interface Operation In the transmit path, the framer generateS the appropriate AMI waveform with the correct bipolar violations as described by G.703 and GR.378. If an 8kHz signal is present on the TS_8K_4 pin, the bipolar violations are generated synchronously with this signal. If it is absent, the part arbitrarily generates the bipolar violation at an 8kHz frequency. Table 15-2.
DS26504 T1/E1/J1/64KCC BITS Element 16. 6312KHZ SYNCHRONIZATION INTERFACE The DS26504 has a 6312kHz Synchronization Interface mode of operation that conforms with Appendix II.2 of G.703, with the exception that the DS26504 transmits a square wave as opposed to the sine wave that is defined in the G.703 specification. 16.1 Receive 6312kHz Synchronization Interface Operation On the receive interface, a 6312kHz sine wave is accepted conforming to the input port requirements of G.703 Appendix II.
DS26504 T1/E1/J1/64KCC BITS Element 17. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT The DS26504 supports the standard IEEE 1149.1 instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26504 contains the following as required by IEEE 1149.
DS26504 T1/E1/J1/64KCC BITS Element TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 17-2. Test-Logic-Reset Upon power-up, the TAP controller is in the Test-Logic-Reset state. The instruction register contains the IDCODE instruction. All system logic of the device operates normally. Run-Test-Idle The Run-Test-Idle is used between scan operations or during specific tests.
DS26504 T1/E1/J1/64KCC BITS Element Select-IR-Scan All test registers retain their previous state. The instruction register remains unchanged during this state. With JTMS LOW, a rising edge on JTCLK moves the controller into the Capture-IR state and initiates a scan sequence for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the Test-Logic-Reset state.
DS26504 T1/E1/J1/64KCC BITS Element Figure 17-2.
DS26504 T1/E1/J1/64KCC BITS Element 17.1 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW shifts the data one stage toward the serial output at JTDO.
DS26504 T1/E1/J1/64KCC BITS Element IDCODE When the IDCODE instruction is latched into the parallel instruction register, the identification test register is selected. The device identification code will be loaded into the identification register on the rising edge of JTCLK following entry into the capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output.
DS26504 T1/E1/J1/64KCC BITS Element Table 17-4.
DS26504 T1/E1/J1/64KCC BITS Element CONTROL CELL CELL # NAME TYPE 29 TNEGO observe_only 30 TCLKO observe_only 31 TCLK observe_only 32 ALE_A7 observe_only 33 A6 observe_only 34 A5 observe_only 35 A4 observe_only 36 A3 observe_only 37 A2 observe_only 38 A1 observe_only 39 A0 observe_only 40 AD7 Output3 1 41 AD6 Output3 1 42 AD5 Output3 1 43 AD4 Output3 1 44 AD3 Output3 1 45 AD2 Output3 1 110 of 129
DS26504 T1/E1/J1/64KCC BITS Element 18. FUNCTIONAL TIMING DIAGRAMS 18.1 Processor Interface 18.1.1 Parallel Port Mode See the AC Timing section. 18.1.2 SPI Serial Port Mode Figure 18-1. SPI Serial Port Access, Read Mode, CPOL = 0, CPHA = 0 SCK CS MOSI 1 0 0 0 0 0 0 MSB A7 A6 LSB MSB A5 A4 A3 A2 A1 A0 B LSB MISO D7 D6 D5 D4 D3 D2 D1 MSB D0 LSB Figure 18-2.
DS26504 T1/E1/J1/64KCC BITS Element Figure 18-4. SPI Serial Port Access, Read Mode, CPOL = 1, CPHA = 1 SCK CS MOSI 1 0 0 0 0 0 0 MSB A7 A6 LSB MSB A5 A4 A3 A2 A1 A0 B LSB MISO D7 D6 D5 D4 D3 D2 D1 MSB D0 LSB Figure 18-5. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 0 SCK CS MOSI 0 0 0 0 0 0 0 MSB A7 A6 LSB MSB A5 A4 A3 A2 A1 A0 B D7 LSB MSB D6 D5 D4 D3 D2 D1 MISO Figure 18-6.
DS26504 T1/E1/J1/64KCC BITS Element Figure 18-7. SPI Serial Port Access, Write Mode, CPOL = 0, CPHA = 1 SCK CS MOSI 0 0 0 0 0 0 0 A7 MSB A6 A5 A4 A3 A2 A1 A0 D7 B D6 D5 D4 D3 D2 D1 LSB MSB LSB MSB D0 LSB MISO Figure 18-8.
DS26504 T1/E1/J1/64KCC BITS Element 19. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground………………………………………………………-1.0V to +6.0V Operating Temperature Range for DS26504L…………………………………………………………0°C to +70°C Operating Temperature Range for DS26504LN……………………………………………-40°C to +85°C (Note 1) Storage Temperature Range………………………………………………………………………...-55°C to +125°C Soldering Temperature………………………………………………….….
DS26504 T1/E1/J1/64KCC BITS Element Table 19-5. DC Characteristics (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26504L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS26504LN.) PARAMETER SYMBOL MIN TYP MAX UNITS 150 mA +1.0 μA 6 1.0 μA 7 Supply Current IDD Input Leakage IIL Output Leakage ILO Output Current (2.4V) IOH -1.0 mA Output Current (0.4V) IOL +4.0 mA Note 6: Note 7: -1.0 0.0V < VIN < VDD Applied to INT when three-stated.
DS26504 T1/E1/J1/64KCC BITS Element 20. AC TIMING PARAMETERS AND DIAGRAMS Capacitive test loads are 40pF for bus signals and 20pF for all others. 20.1 Multiplexed Bus Table 20-1. AC Characteristics, Multiplexed Parallel Port (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26504L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS26504LN.
DS26504 T1/E1/J1/64KCC BITS Element Figure 20-1. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 00) t CYC ALE WR PWASH t ASD t ASD t ASED RD PWEL PWEH t CH t CS CS t ASL t DHR t DDR AD0-AD7 t AHL Figure 20-2.
DS26504 T1/E1/J1/64KCC BITS Element Figure 20-3.
DS26504 T1/E1/J1/64KCC BITS Element 20.2 Nonmultiplexed Bus Table 20-2. AC Characteristics, Nonmultiplexed Parallel Port (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26504L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS26504LN.
DS26504 T1/E1/J1/64KCC BITS Element Figure 20-4. Intel Bus Read Timing (BTS = 0 / BIS[1:0] = 01) A0 to A7 Address Valid D0 to D7 Data Valid t5 5ns min/20ns max WR t1 0ns min 0ns min t2 CS t3 t4 75ns max RD 0ns min Figure 20-5.
DS26504 T1/E1/J1/64KCC BITS Element Figure 20-6. Motorola Bus Read Timing (BTS = 1 / BIS[1:0] = 01) A0 to A7 Address Valid D0 to D7 Data Valid 5ns min. / 20ns max. t5 R/W t1 CS 0ns min. 0ns min. t2 t3 t4 0ns min. 75ns max. DS Figure 20-7. Motorola Bus Write Timing (BTS = 1 / BIS[1:0] = 01) A0 to A7 Address Valid D0 to D7 10ns min. R/W t1 t7 t8 10ns min. 0ns min. CS 0ns min. DS t2 t6 75ns min. 121 of 129 t4 0ns min.
DS26504 T1/E1/J1/64KCC BITS Element 20.3 Serial Bus Table 20-3. AC Characteristics, Serial Bus (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26504L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS26504LN.
DS26504 T1/E1/J1/64KCC BITS Element Figure 20-8. SPI Interface Timing Diagram, CPHA = 0, BIS[1:0] = 10 CS INPUT 1 3 5 CLK INPUT CPOL = 0 4 2 CLK INPUT CPOL = 1 5 4 8 9 MISO INPUT SLAVE MSB 6 MOSI OUTPUT BITS 6-1 BITS 6-1 MSB NOTE 11 10 7 SLAVE LSB 11 LSB NOTE: NOT DEFINED, BUT USUALLY MSB OF CHARACTER JUST RECEIVED. Figure 20-9.
DS26504 T1/E1/J1/64KCC BITS Element 20.4 Receive Side AC Characteristics Table 20-4. Receive Side AC Characteristics (VDD = 3.3V ±5%, TA = 0°C to +70°C for DS26504L; VDD = 3.3V ±5%, TA = -40°C to +85°C for DS26504LN.) (Note 1) (Figure 20-10) PARAMETER RCLK Period SYMBOL RCLK to RSER Delay RCLK to RS_8K, 400Hz Delay tD2 RCLK Pulse Width UNITS NOTES TYP MAX 200 200 ns ns μs ns ns ns 150 150 ns ns 2 3 4 5 6 6 4 4 7 7 4 4 488 648 15.6 158.
DS26504 T1/E1/J1/64KCC BITS Element Figure 20-10. Receive Timing—T1, E1, 64KCC Mode RCLK t D1 RSER t D2 E1 = MSB of Channel 1 T1 = F-Bit RS_8K1 t D2 RS_8K2 t D2 400HZ3 NOTES: 1) RS_8K OUTPUT IN T1 OR E1 MODE. 2) RS_8K OUTPUT IN 64KCC MODE. 3) 400Hz OUTPUT ACTIVE ONLY IN 64KCC MODE, HIGH IMPEDANCE IN ALL OTHER MODES.
DS26504 T1/E1/J1/64KCC BITS Element 20.5 Transmit Side AC Characteristics Table 20-5. Transmit Side AC Characteristics (VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Note 1) (Figure 20-11) PARAMETER SYMBOL TCLK Period tCP TCLK Pulse Width tCH tCL TCLK Rise and Fall Times tR, tF TX CLOCK Setup to TSER, TS_8K_4 tSU Delay TX CLOCK to TS_8K_4 tD2 Delay TCLK to PLL_OUT, TX CLOCK Delay TCLKO to TPOSO and TNEGO MIN TYP MAX UNITS NOTES ns ns μs ns ns ns 2 3 4 5 488 648 15.6 158.
DS26504 T1/E1/J1/64KCC BITS Element Figure 20-11. Transmit Timing—T1, E1, 64KCC Mode t CP t CL tF tR t CH TCLK RCLK, JA CLOCK4 PLL_OUT t D3 TX CLOCK3 t SU TSER t HD t D2 TS_8K_41 t SU TS_8K_42 (REFER TO THE TRANSMIT PLL BLOCK DIAGRAM, 3-3.) NOTE 1: TS_8K_4 IN OUTPUT MODE. NOTE 2: TS_8K_4 IN INPUT MODE. NOTE 3: TX CLOCK IS THE INTERNAL CLOCK THAT DRIVES THE TRANSMIT SECTION. THE SOURCE OF THIS SIGNAL DEPENDS ON THE CONFIGURATION OF THE TRANSMIT PLL.
DS26504 T1/E1/J1/64KCC BITS Element 21. REVISION HISTORY REVISION DATE DESCRIPTION 070105 New product release. 081105 Corrected the polarity of the TAIS pin when operating in Hardware mode. 101805 020906 053107 100507 121707 042208 072308 PAGES CHANGED — 19, 29 N Changed Section 13.4 to read “2.048 x 2 (where N = 1 to 3)” instead of “2.048 x N (where N = 1 to 4).” Section 13.3.1, Section 13.3.2, SR1 Bits 1 and 2: Clarified the open circuit and short circuit wording.
DS26504 T1/E1/J1/64KCC BITS Element 22. PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 22.1 64-Pin LQFP (56-G4019-001) 129 of 129 Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied.
