Datasheet

DS26514 4-Port T1/E1/J1 Transceiver
19-5856; Rev 4; 5/11 25 of 305
NAME PIN TYPE FUNCTION
D[5]/SPI_SWAP M9
Input/
Output
Data [5]/SPI Bit Order Swap
D[5]: Bit 5 of the 16-bit or 8-bit data bus used to input data during register writes
and data outputs during register reads. Not driven when CSB = 1.
SPI_SWAP: This signal is active when SPI_SEL = 1. The address and data bit
order is swapped when SPI_SWAP is high. The R/W and B bit positions are
never changed in the control word.
0 = LSB is transmitted and received first.
1 = MSB is transmitted and received first.
D[4] R8
Input/
Output
Data [4]. Bit 4 of the 8-bit data bus used to input data during register writes and
data outputs during register reads. Not driven when CSB = 1.
D[3] T8
Input/
Output
Data [3]. Bit 3 of the 8-bit data bus used to input data during register writes and
data outputs during register reads. Not driven when
CSB
= 1.
D[2]/SPI_SCLK P8
Input/
Output
Data [2]/SPI Serial Interface Clock
D[2]: Bit 2 of the 8-bit data bus used to input data during register writes and data
outputs during register reads. Not driven when CSB = 1.
SPI_SCLK: SPI Serial Clock Input when SPI_SEL = 1.
D[1]/SPI_MOSI L9
Input/
Ouput
Data [1]/SPI Serial Interface Data Master Out-Slave In
D[1]: Bit 1 of the 8-bit data bus used to input data during register writes, and data
outputs during register reads. Not driven when CSB = 1.
SPI_MOSI: SPI Serial Data Input (Master Out-Slave In) when SPI_SEL = 1.
D[0]/SPI_MISO N8
Input/
Output
Data [0]/SPI Serial Interface Data Master In-Slave Out
D[0]: Bit 0 of the 8-bit data bus used to input data during register writes and data
outputs during register reads. Not driven when CSB = 1.
SPI_MISO:
SPI Serial Data Output (Master In-Slave Out) when SPI_SEL = 1.
CSB
T7 Input
Chip-Select Bar. This active-low signal is used to qualify register read/write
accesses. The RDB/DSB and WRB signals are qualified with CSB.
RDB/
DSB
M8 Input
Read Bar/Data-Strobe Bar. This active-low signal along with CSB qualifies read
access to one of the DS26514 registers. The DS26514 drives the data bus with
the contents of the addressed register while RDB and CSB are low. Note: If SPI
mode is selected by the SPI_SEL pin, this pin must be connected through a 10K
ohm resistor to the I/O Supply.
WRB/
RWB
R7 Input
Write Bar/Read-Write Bar. This active-low signal along with CSB qualifies write
access to one of the DS26514 registers. Data at D[7:0] is written into the
addressed register at the rising edge of WRB while CSB is low. Note: If SPI mode
is selected by the SPI_SEL pin, this pin must be connected through a 10K ohm
resistor to the I/O Supply.
INTB
R9
Output,
Three-
Stateable
Interrupt Bar. This active-low output is asserted when an unmasked interrupt
event is detected. INTB will be deasserted (and three-stated) when all interrupts
have been acknowledged and serviced. Extensive mask bits are provided at the
global level, framer, LIU, and BERT level.
SPI_SEL/
AL/RSIGF/FLOS1
C3
Input with
internal
pulldown/
Output
SPI Serial Bus Mode Select/Analog Loss/Receive Signaling Freeze/Framer
LOS
SPI_SEL: 0 = Parallel Bus Mode, 1 = SPI Serial Bus Mode
AL/RSIGF/FLOS1: Analog LOS reflects the loss of signal detected by the LIU
front-end; framer LOS is LOS detection by the corresponding framer. The same
pins can reflect receive-signaling freeze indications. This selection can be made
by settings in Global Transceiver Control Register (
GTCR1). AL/RSIGF/FLOS1
are available by setting the GTCR1.528MD bit to 1.
BTS M13 Input
Bus Type Select. Set high to select Motorola bus timing, low to select Intel bus
timing. This pin controls the function of the RDB/DSB and WRB pins. Note: If SPI
mode is selected by the SPI_SEL pin, this pin must be tied low.
SYSTEM INTERFACE