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DS26518

8-Port T1/E1/J1 Transceiver

______________ General Description

The DS26518 is an 8-port framer and line interface

unit (LIU) combination for T1, E1, J1 applications.

Each port is independently configurable, supporting

both long-haul and short-haul lines. The DS26518

Single-Chip Transceiver (SCT) is software and pinout

compatible with the 4-port DS26514. It is nearly

software compatible with the DS26528 and its

derivatives.

___________________ Applications

Routers

Channel Service Units (CSUs)

Data Service Units (DSUs)

Muxes

Switches

Channel Banks

T1/E1 Test Equipment

______________ Functional Diagram

DS26518

T1/J1/E1

Transceiver

T1/E1/J1

NETWORK

BACKPLANE

TDM

_____________ Ordering Information

PART TEMP RANGE PIN-PACKAGE

DS26518GN

-40°C to +85°C

256 TE-CSBGA

DS26518GN+

-40°C to +85°C

256 TE-CSBGA

+ Denotes a lead-free/RoHS compliant device.

________________________Features

 Eight Complete T1, E1, or J1 Long-Haul/

Short-Haul Transceivers (LIU Plus Framer)

 Independent T1, E1, or J1 Selections for Each

Transceiver

 Fully Internal Impedance Match, No External

Resistor

 Software-Selectable Transmit- and Receive-

Side Termination for 100Ω T1 Twisted Pair,

110Ω J1 Twisted Pair, 120Ω E1 Twisted Pair,

and 75Ω E1 Coaxial Applications

 Hitless Protection Switching

 Crystal-Less Jitter Attenuators Can Be

Selected for Transmit or Receive Path; Jitter

Attenuator Meets ETS CTR 12/13, ITU-T

G.736, G.742, G.823, and AT&T Pub 62411

 External Master Clock Can Be Multiple of

2.048MHz or 1.544MHz for T1/J1 or E1

Operation; This Clock is Internally Adapted

for T1 or E1 Usage in the Host Mode

 Receive-Signal Level Indication from -2.5dB

to -36dB in T1 Mode and -2.5dB to -44dB in E1

Mode in Approximate 2.5dB Increments

 Transmit Open- and Short-Circuit Detection

 LIU LOS in Accordance with G.775, ETS 300

233, and T1.231

 Transmit Synchronizer

 Flexible Signaling Extraction and Insertion

Using Either the System Interface or

Microprocessor Port

 Alarm Detection and Insertion

 T1 Framing Formats of D4, SLC-96, and ESF

 J1 Support

 E1 G.704 and CRC-4 Multiframe

 T1-to-E1 Conversion

Features continued in Section 2

Rev: 103008

Summary of content (312 pages)

PAGE 1
Rev: 103008 DS26518 8-Port T1/E1/J1 Transceiver ______________ General Description ________________________ Features The DS26518 is an 8-port framer and line interface unit (LIU) combination for T1, E1, J1 applications. Each port is independently configurable, supporting both long-haul and short-haul lines. The DS26518 Single-Chip Transceiver (SCT) is software and pinout compatible with the 4-port DS26514. It is nearly software compatible with the DS26528 and its derivatives.
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DS26518 8-Port T1/E1/J1 Transceiver TABLE OF CONTENTS 1. DETAILED DESCRIPTION.................................................................................................9 2. FEATURE HIGHLIGHTS ..................................................................................................10 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 GENERAL ......................................................................................................................................10 LINE INTERFACE .......
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.8 9.9.9 9.9.10 9.9.11 9.9.12 9.9.13 9.9.14 9.9.15 9.9.16 9.9.17 9.10 9.10.1 9.10.2 9.10.3 9.11 9.12 9.12.1 9.12.2 9.12.3 9.12.4 9.12.5 9.12.6 9.13 9.13.1 9.13.2 10. 10.1.1 10.1.2 10.1.3 10.1.4 10.1.5 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 10.3 10.4 10.4.1 10.4.2 10.5 10.6 10.6.1 10.7 10.7.1 10.7.2 HDLC-64 Controller..............................................................................................................................
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DS26518 8-Port T1/E1/J1 Transceiver 12.1 12.2 13. THERMAL CHARACTERISTICS ....................................................................................................292 LINE INTERFACE CHARACTERISTICS ..........................................................................................292 AC TIMING CHARACTERISTICS ..................................................................................293 13.1 MICROPROCESSOR BUS AC CHARACTERISTICS ................................................
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DS26518 8-Port T1/E1/J1 Transceiver LIST OF FIGURES Figure 7-1. Block Diagram ......................................................................................................................................... 18 Figure 7-2. Detailed Block Diagram........................................................................................................................... 19 Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0 ...............................................
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DS26518 8-Port T1/E1/J1 Transceiver Figure 11-16. T1 Transmit-Side TCHCLKn Gapped Mode During F-Bit ................................................................. 281 Figure 11-17. E1 Receive-Side Timing.................................................................................................................... 282 Figure 11-18. E1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 282 Figure 11-19. E1 Receive-Side 1.
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DS26518 8-Port T1/E1/J1 Transceiver LIST OF TABLES Table 4-1. T1-Related Telecommunications Specifications ...................................................................................... 14 Table 4-2. E1-Related Telecommunications Specifications ...................................................................................... 15 Table 5-1. Time Slot Numbering Schemes................................................................................................................ 16 Table 8-1.
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DS26518 8-Port T1/E1/J1 Transceiver Table 10-1. Register Address Ranges (in Hex)....................................................................................................... 102 Table 10-2. Global Register List .............................................................................................................................. 103 Table 10-3. Framer Register List .............................................................................................................................
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DS26518 8-Port T1/E1/J1 Transceiver 1. DETAILED DESCRIPTION The DS26518 is an 8-port monolithic device featuring independent transceivers that can be software configured for T1, E1, or J1 operation. Each transceiver is composed of a line interface unit, framer, two HDLC controllers, elastic store, and a TDM backplane interface. The DS26518 is controlled via an 8-bit parallel port or the SPI port.
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DS26518 8-Port T1/E1/J1 Transceiver 2. FEATURE HIGHLIGHTS 2.1 General 17mm x 17mm, 256-pin TE-CSBGA (1.00mm pitch) 3.3V supply with 5V tolerant inputs and outputs IEEE 1149.1 JTAG boundary scan Development support includes evaluation kit, driver source code, and reference designs 2.2 Line Interface Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be 1.544MHz, 2.048MHz, 3.088MHz, 4.096MHz, 6.176MHz, 8.192MHz, 12.352MHz, or 16.384MHz.
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DS26518 8-Port T1/E1/J1 Transceiver 2.5 Framer/Formatter Fully independent transmit and receive functionality Full receive and transmit path transparency T1 framing formats D4 and ESF per T1.403 and expanded SLC-96 support (TR-TSY-008) E1 FAS framing and CRC-4 multiframe per G.704/G.706, and G.
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DS26518 8-Port T1/E1/J1 Transceiver Signaling freezing Ability to pass the T1 F-bit position through the elastic stores in the 2.048MHz backplane mode User-selectable synthesized clock output 2.
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DS26518 8-Port T1/E1/J1 Transceiver 3.
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DS26518 8-Port T1/E1/J1 Transceiver 4. SPECIFICATIONS COMPLIANCE The DS26518 meets all the latest relevant telecommunications specifications. Table 4-1 provides the T1 specifications and Table 4-2 provides the E1 specifications and relevant sections that are applicable to the DS26518. Table 4-1. T1-Related Telecommunications Specifications ANSI T1.102: Digital Hierarchy Electrical Interface AMI Coding B8ZS Substitution Definition DS1 Electrical Interface. Line rate ±32ppm; Pulse Amplitude between 2.
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DS26518 8-Port T1/E1/J1 Transceiver Table 4-2. E1-Related Telecommunications Specifications ITU-T G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces Defines the 2048kbps bit rate—2048 ±50ppm; the transmission media are 75Ω coax or 120Ω twisted pair; peak-topeak space voltage is ±0.237V; nominal pulse width is 244ns. Return loss 51Hz to 102Hz is 6dB, 102Hz to 3072Hz is 8dB, 2048Hz to 3072Hz is 14dB. Nominal peak voltage is 2.37V for coax and 3V for twisted pair.
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DS26518 8-Port T1/E1/J1 Transceiver 5. ACRONYMS AND GLOSSARY This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125μs T1 frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1. For T1 and E1 each channel is made up of 8 bits, which are numbered 1 to 8. Bit 1, the MSB, is transmitted first. Bit 8, the LSB, is transmitted last.
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DS26518 8-Port T1/E1/J1 Transceiver 6. MAJOR OPERATING MODES The DS26518 has two major modes of operation: T1 mode and E1 mode. The mode of operation for each LIU is configured in the LTRCR register. The mode of operation for each framer is configured in the TMMR register. J1 operation is a special case of T1 operating mode.
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DS26518 8-Port T1/E1/J1 Transceiver 7. BLOCK DIAGRAMS Figure 7-1. Block Diagram DS26518 LIU #8 LIU #7 LIU #6 ... LIU #4 LIU #3 LIU #2 RTIP RRING TTIP FRAMER #8 FRAMER #7 FRAMER #6 ... FRAMER #4 FRAMER #3 FRAMER #2 T1/E1 FRAMER LINE INTERFACE UNIT INTERFACE #6 ...
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DS26518 8-Port T1/E1/J1 Transceiver Figure 7-2.
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DS26518 8-Port T1/E1/J1 Transceiver 8. PIN DESCRIPTIONS 8.1 Pin Functional Description Table 8-1.
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DS26518 8-Port T1/E1/J1 Transceiver NAME PIN TSER1 TSER2 TSER3 TSER4 TSER5 TSER6 TSER7 TSER8 F6 E7 R4 N7 M10 L11 F10 D12 TCLK1 C5 TCLK2 D7 TCLK3 P5 TCLK4 L8 TCLK5 L10 TCLK6 N11 TCLK7 E10 TCLK8 B13 TYPE FUNCTION TRANSMIT FRAMER TSYSCLK1 TSYSCLK2/ AL/RSIGF/FLOS2 TSYSCLK3/ AL/RSIGF/FLOS3 TSYSCLK4/ AL/RSIGF/FLOS4 TSYSCLK5/ AL/RSIGF/FLOS5 TSYSCLK6/ AL/RSIGF/FLOS6 TSYSCLK7/ AL/RSIGF/FLOS7 TSYSCLK8/ AL/RSIGF/FLOS8 TSYNC1/ TSSYNCIO1 TSYNC2/ TSSYNCIO2 TSYNC3/ TSSYNCIO3 TSYNC4/ TSSYNCIO4 TSYNC5
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DS26518 8-Port T1/E1/J1 Transceiver NAME PIN TSYNC8/ TSSYNCIO8 A13 TSSYNCIO N13 TYPE Input/ Output FUNCTION be generated. This pulse in combination with BPCLK1 can be used as an IBO master. TSSYNCIOn can be used as a source to RSYNCn and TSSYNCIOn of another DS26518 or RSYNC and TSSYNC of other Maxim parts. Note: TSSYNCIO[8:1] are not used when GTCR1.528MD is set. When GTCR1.528MD is set, the TSSYNCIO pin (N13) is used. Note: In default operation, this pin is not used. When GTCR1.
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DS26518 8-Port T1/E1/J1 Transceiver NAME PIN RSER1 RSER2 RSER3 RSER4 RSER5 RSER6 RSER7 RSER8 RCLK1 RCLK2 RCLK3 RCLK4 RCLK5 RCLK6 RCLK7 RCLK8 E5 D6 N4 N6 M11 M12 B12 F11 F4 G4 L4 M4 K13 J13 F13 E13 TYPE FUNCTION RECEIVE FRAMER RSYSCLK1 RSYSCLK2/ RLF/LTC2 RSYSCLK3/ RLF/LTC3 RSYSCLK4/ RLF/LTC4 RSYSCLK5/ RLF/LTC5 RSYSCLK6/ RLF/LTC6 RSYSCLK7/ RLF/LTC7 RSYSCLK8/ RLF/LTC8 RSYNC1 RSYNC2 RSYNC2 RSYNC2 RSYNC5 RSYNC6 RSYNC7 RSYNC8 L12 Output Output Input E3 M3 N3 N14 M14 Input with internal pulldown/ Outp
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DS26518 8-Port T1/E1/J1 Transceiver NAME RMSYNC1/ RFSYNC1 RMSYNC2/ RFSYNC2 RMSYNC3/ RFSYNC3 RMSYNC4/ RFSYNC4 RMSYNC5/ RFSYNC5 RMSYNC6/ RFSYNC6 RMSYNC7/ RFSYNC7 RMSYNC8/ RFSYNC8 RSIG1 RSIG2 RSIG3 RSIG4 RSIG5 RSIG6 RSIG7 RSIG8 RCHBLK1/ RCHCLK1 RCHBLK2/ RCHCLK2 RCHBLK3/ RCHCLK3 RCHBLK4/ RCHCLK4 RCHBLK5/ RCHCLK5 RCHBLK6/ RCHCLK6 RCHBLK7/ RCHCLK7 RCHBLK8/ RCHCLK8 BPCLK1 PIN TYPE FUNCTION Output Receive Multiframe/Frame Synchronization 1 to 8.
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DS26518 8-Port T1/E1/J1 Transceiver NAME PIN A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 C8 A8 B8 F8 B9 A9 C9 D9 E9 F9 B10 A10 C10 TYPE FUNCTION MICROPROCESSOR INTERFACE D7/SPI_CPOL D6/SPI_CPHA T9 N9 Input Input/ Output Input/ Output Address [12:0]. This bus selects a specific register in the DS26518 during read/write access. A12 is the MSB and A0 is the LSB.
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DS26518 8-Port T1/E1/J1 Transceiver NAME PIN TYPE WRB/ RWB R7 Input INTB R9 Output, TriStateable SPI_SEL/ AL/RSIGF/FLOS1 C3 Input with internal pulldown/ Output BTS M13 Input FUNCTION Write Bar/Read-Write Bar. This active-low signal along with CSB qualifies write access to one of the DS26518 registers.
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DS26518 8-Port T1/E1/J1 Transceiver NAME PIN TYPE SCANMODE H13 Input FUNCTION Scan Mode. When low, normal operational clocks are used to clock the flip flops. User should tie low. POWER SUPPLIES ATVDD ATVSS ARVDD ARVSS B1, B16, G1, G16, K1, K16, R1, R16 B2, B15, G2, G15, K2, K15, R2, R15 D1, D16, E1, E16, M1, M16, N1, N16 D2, D15, E2, E15, M2, M15, N2, N15 — 3.3V ±5% Analog Transmit Power Supply. These VDD inputs are used for the transmit LIU sections of the DS26518. — Analog Transmit VSS.
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DS26518 8-Port T1/E1/J1 Transceiver 9. FUNCTIONAL DESCRIPTION 9.1 Processor Interface Microprocessor control of the DS26518 is accomplished through the 28 hardware pins of the microprocessor port. The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the bus type select (BTS) pin. When the BTS pin is a logic 0, bus timing is in Intel mode, as shown in Figure 13-2 and Figure 13-3.
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DS26518 8-Port T1/E1/J1 Transceiver user must configure the SPI_CPOL and SPI_CPHA pins to describe which type of clock that the master device is providing. Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0 SPI_SCLK CSB SPI_MOSI 1 A13 A12 A11 A10 A9 A8 MSB A7 A6 LSB MSB A5 A4 A3 A2 A1 A0 B LSB SPI_MISO D7 D6 D5 D4 D3 D2 D1 MSB D0 LSB Figure 9-2.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 9-5. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 0 SPI_SCLK CSB SPI_MOSI 0 A13 A12 A11 A10 A9 A8 MSB A7 A6 LSB MSB A5 A4 A3 A2 A1 A0 B D7 LSB MSB D6 D5 D4 D3 D2 D1 D0 LSB SPI_MISO Figure 9-6.
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DS26518 8-Port T1/E1/J1 Transceiver 9.2 Clock Structure The user should provide a system clock to the MCLK input of 2.048MHz, 1.544MHz, or a multiple of up to 8x the T1 and E1 frequencies. To meet many specifications, the MCLK source should have ±50ppm accuracy. 9.2.1 Backplane Clock Generation The DS26518 provides facility for provision of BPCLK1 at 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz (see Figure 9-9).
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DS26518 8-Port T1/E1/J1 Transceiver 9.2.2 CLKO Output Clock Generation This clock output is derived from MCLK based upon the setting of the CLKOSEL[2:0] bits in the GTCCR3 register.The reference for the PLL is not the input clock on MCLK, but the scaled version of MCLK (1.544MHz or 2.048MHz). The LTRCR.T1J1E1S bit also selects the proper PLL for use in generating the appropriate frequency. This clock output pin is provided as an additional feature to eliminate the need for another board oscillator.
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DS26518 8-Port T1/E1/J1 Transceiver 9.3 Resets and Power-Down Modes A hardware reset is issued by forcing the RESETB pin to logic low. The RESETB input pin resets all framers, LIUs, and BERTs. Note that not all registers are cleared to 00h on a reset condition. The register space must be reinitialized to appropriate values after a hardware or software reset has occurred. This includes writing reserved locations to 00h. Table 9-2.
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DS26518 8-Port T1/E1/J1 Transceiver 9.4 Initialization and Configuration 9.4.1 Example Device Initialization and Sequence STEP 1: Reset the device by pulling the RESETB pin low, applying power to the device, or by using the software reset bits outlined in Section 9.3. Clear all reset bits. Allow time for the reset recovery. STEP 2: Check the Device ID in the IDR register. STEP 3: Write the GTCCR1 register to correctly configure the system clocks. If supplying a 1.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 9-10. Device Interrupt Information Flow Diagram 0 1 Interrupt Status Registers Register Name Interrupt Mask Registers Register Name 2 RIIR RIM2 RIM3 RIM4 RIM1 RLS 2 RLS3 RLS4 RLS1 Drawing Legend: RIM5 RLS5 3 35 of 312 Interrupt Pin GTCR1.
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DS26518 8-Port T1/E1/J1 Transceiver 9.8 System Backplane Interface The DS26518 provides a versatile backplane interface that can be configured to: • Transmit and receive two-frame elastic stores • Mapping of T1 channels into a 2.
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DS26518 8-Port T1/E1/J1 Transceiver 9.8.1.1 Elastic Stores Initialization There are two elastic store initializations that may be used to improve performance in certain applications: elastic store reset and elastic store align. Both of these involve the manipulation of the elastic store’s read and write pointers and are useful primarily in synchronous applications (RSYSCLKn/TSYSCLKn are locked to RCLKn/TCLKn, respectively). The elastic store reset is used to minimize the delay through the elastic store.
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DS26518 8-Port T1/E1/J1 Transceiver 9.8.1.4 Receiving Mapped T1 Channels from a 2.048MHz Backplane Setting the TSCLKM bit in TIOCR.4 enables the transmit elastic store to operate with a 2.048MHz backplane (32 time slots / frame). In this mode the user can choose which of the backplane channels on TSERn will be mapped into the T1 data stream by programming the Transmit Blank Channel Select registers (TBCS1–4).
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DS26518 8-Port T1/E1/J1 Transceiver 9.8.1.7 Mapping E1 Channels onto a 1.544MHz Backplane The user can use the RSCLKM bit in RIOCR.4 to enable the receive elastic store to operate with a 1.544MHz backplane (24 channels / frame + F-bit). In this mode the user can choose which of the E1 time slots will be ignored (not transmitted onto RSERn) by programming the Receive Blank Channel Select registers (RBCS1–4).
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DS26518 8-Port T1/E1/J1 Transceiver Figure 9-11. IBO Multiplexer Equivalent Circuit—4.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 9-12. IBO Multiplexer Equivalent Circuit—8.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 9-13. IBO Multiplexer Equivalent Circuit—16.
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DS26518 8-Port T1/E1/J1 Transceiver Table 9-6. RSERn Output Pin Definitions (GTCR1.GIBO = 0) PIN NORMAL USE 4.096MHz IBO 8.192MHz IBO 16.
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DS26518 8-Port T1/E1/J1 Transceiver Table 9-8. TSERn Input Pin Definitions (GTCR1.GIBO = 0) PIN NORMAL USE 4.096MHz IBO 8.192MHz IBO 16.
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DS26518 8-Port T1/E1/J1 Transceiver Table 9-10. RSYNCn Input Pin Definitions (GTCR1.GIBO = 0) PIN NORMAL USE 4.096MHz IBO 8.192MHz IBO 16.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 9-14. RSYNCn Input in H.100 (CT Bus) Mode RSYNCn1 RSYNCn2 RSYSCLKn RSERn BIT 8 BIT 1 BIT 2 3 tBC NOTE 1: RSYNCn INPUT MODE IN NORMAL OPERATION. NOTE 2: RSYNCn INPUT MODE, H100EN = 1 AND RSYNCINV = 1. NOTE 3: tBC (BIT CELL TIME) = 122ns (typ). tBC = 244ns or 488ns ALSO ACCEPTABLE. Figure 9-15. TSSYNCIOn (Input Mode) Input in H.100 (CT Bus) Mode TSSYNCIOn1 TSSYNCIOn2 TSYSCLKn TSERn BIT 8 BIT 1 BIT 2 tBC3 NOTE 1: TSSYNCIOn IN NORMAL OPERATION.
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DS26518 8-Port T1/E1/J1 Transceiver 9.8.4 Transmit and Receive Channel Blocking Registers The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLKn and TCHBLKn pins, respectively. The RCHBLKn and TCHBLKn pins are user-programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN-PRI applications.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9 Framers The DS26518 framer cores are software selectable for T1, J1, or E1. The receive framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling data, T1 FDL data, and E1 Si- and Sa-bit information.
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DS26518 8-Port T1/E1/J1 Transceiver Table 9-12. ESF Framing Mode FRAME NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FRAMING FDL CRC SIGNALING √ CRC1 √ 0 √ CRC2 √ √ 0 √ CRC3 √ √ √ CRC4 √ 0 √ √ CRC5 √ 1 √ CRC6 √ √ 1 Table 9-13.
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DS26518 8-Port T1/E1/J1 Transceiver FRAME NUMBER 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Ft Fs SIGNALING C3 (Concentrator Bit) 1 C4 (Concentrator Bit) A 0 C5 (Concentrator Bit) 1 C6 (Concentrator Bit) 0 C7 (Concentrator Bit) B 1 C8 (Concentrator Bit) 0 C9 (Concentrator Bit) 1 C10 (Concentrator Bit) C 0 C11 (Concentrator Bit) 1 0 (Spoiler Bit) 0 D 1 (Spoiler Bit) 1 0 (Spoiler Bit) 0 M1 (Maintenance Bit)
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.2 E1 Framing The E1 framing consists of FAS, NFAS detection as shown in Table 9-14. Table 9-14.
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DS26518 8-Port T1/E1/J1 Transceiver Table 9-15 shows the registers that are related to setting up the framing. Table 9-15. Registers Related to Setting Up the Framer REGISTER FRAMER 1 ADDRESSES FUNCTION Transmit Master Mode Register (TMMR) 180h T1/E1 mode. Transmit Control Register 1 (TCR1) 181h Source of the F-bit. Transmit Control Register 2 (T1.TCR2) 182h F-bit corruption, selection of SLC-96. Transmit Control Register 3 (TCR3) 183h ESF or D4 mode selection.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.3 T1 Transmit Synchronizer The DS26518 transmitter can identify the D4 or ESF frame boundary, as well as the CRC multiframe boundaries within the incoming NRZ data stream at TSERn. The TFM (TCR3.2) control bit determines whether the transmit synchronizer searches for the D4 or ESF multiframe. Additional control signals for the transmit synchronizer are located in the TSYNCC register. The latched status bit TLS3.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.4 Signaling The DS26518 supports both software and hardware-based signaling. Interrupts can be generated on changes of signaling data. The DS26518 is also equipped with receive-signaling freeze on loss of synchronization (OOF), carrier loss or change of frame alignment. The DS26518 also has hardware pins to indicate signaling freeze.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.4.1 Transmit-Signaling Operation There are two methods to provide transmit-signaling data. These are processor based (i.e., software based) or hardware based. Processor-based refers to access through the transmit signaling registers, TS1–TS16, while hardware based refers to using the TSIGn pins. Both methods can be used simultaneously. 9.9.4.1.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.4.2 Receive-Signaling Operation There are two methods to access receive-signaling data and provide transmit-signaling data: processor based (i.e., software based) or hardware based. Processor-based refers to access through the transmit- and receive-signaling registers, RS1–RS16. Hardware based refers to the RSIGn pin. Both methods can be used simultaneously. 9.9.4.2.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.4.2.6 Receive-Signaling Freeze The signaling data in the four multiframe signaling buffers will be frozen in a known good state upon either a loss of synchronization (OOF event), carrier loss, or change of frame alignment. In T1 mode, this action meets the requirements of BellCore TR-TSY-000170 for signaling freezing. To allow this freeze action to occur, the RSFE control bit (RSIGC.1) should be set high.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.4.4 Receive SLC-96 Operation (T1 Mode Only) In an SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of message fields. The SLC-96 multiframe is made up of six D4 superframes, hence it is 72 frames long. In the 72frame SLC-96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36-bits are divided into alarm, maintenance, spoiler, and concentrator bits as well as 12-bits of the normal Fs pattern.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.5 T1 Data Link 9.9.5.1 T1 Transmit Bit-Oriented Code (BOC) Transmit Controller The DS26518 contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1 mode. Table 9-19 shows the registers related to the transmit bit-oriented code. Table 9-19. Registers Related to T1 Transmit BOC FRAMER 1 ADDRESSES FUNCTION Transmit BOC Register (T1TBOC) 163h Transmit bit-oriented message code register.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.5.3 Legacy T1 Transmit FDL It is recommended that the DS26518’s built-in BOC or HDLC controllers be used for most applications requiring access to the FDL. Table 9-21 shows the registers related to control of the transmit FDL. Table 9-21. Registers Related to T1 Transmit FDL REGISTER Transmit FDL Register (T1TFDL) FRAMER 1 ADDRESSES 162h FUNCTION FDL code used to insert transmit FDL. Transmit Control Register 2 (T1.TCR2) 182h Defines the source of the FDL.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.6 E1 Data Link Table 9-23 shows the registers related to E1 data link. Table 9-23.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.6.1 Additional E1 Receive Sa- and Si-Bit Receive Operation (E1 Mode) The DS26518, when operated in the E1 mode, provides for access to both the Sa and the Si bits via two methods. The first involves using the internal E1RAF/E1RNAF and E1TAF/E1TNAF registers. The second method involves an expanded version of the first method. 9.9.6.1.
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DS26518 8-Port T1/E1/J1 Transceiver Table 9-24 shows some of the registers related to maintenance and alarms. Table 9-24. Registers Related to Maintenance and Alarms REGISTER FRAMER 1 ADDRESSES Receive Real-Time Status Register 1 (RRTS1) 0B0h Real-time receive status 1. Receive Interrupt Mask Register 1(RIM1) 0A0h Real-time interrupt mask 1. Receive Latched Status Register 2 (RLS2) 091h Real-time latched status 2. Receive Real-Time Status Register 3 (RRTS3) 0B2h Real-time receive status 2.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.7.1 Status and Information Bit Operation When a particular event has occurred (or is occurring), the appropriate bit in one of these registers will be set to a one. Status bits may operate in either a latched or real-time fashion. Some latched bits may be enabled to generate a hardware interrupt via the INTB signal. 9.9.7.1.1 Real-Time Bits Some status bits operate in a real-time fashion.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.8 Alarms Table 9-25. T1 Alarm Criteria ALARM AIS (Blue Alarm) (See Note 1) 1) D4 Bit 2 Mode (T1RCR2.0 = 0) RAI (Yellow Alarm) 2) D4 12th F-Bit Mode (T1RCR2.0 = 1) (Note: This mode is also referred to as the “Japanese Yellow Alarm.”) 3) ESF Mode 4) J1 ESF Mode (J1 LFA) LOS (Loss of Signal) (Note: This alarm is also referred to as receive carrier loss (RCL).) SET CRITERIA CLEAR CRITERIA When over a 3ms window, 4 or fewer zeros are received.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.8.2 Receive RAI Table 9-27 shows the registers related to the receive RAI (Yellow Alarm). Table 9-27. Registers Related to Receive RAI (Yellow Alarm) REGISTER FRAMER 1 ADDRESSES FUNCTION Receive Control Register 2 (T1RCR2.RRAIS) 014h Select RAI to be T1 or J1. Receive Control Register 2 (T1RCR2.RAIIE) 014h Integration Enable for T1 ESF Note: The addresses shown above are for Framer 1.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.9 Error Count Registers The DS26518 contains four counters that are used to accumulate line coding errors, path errors, and synchronization errors. Counter update options include one second boundaries, 42ms (T1 mode only), 62.5ms (E1 mode only) or manually. See the Error Counter Configuration Register (ERCNT). When updated automatically, the user can use the interrupt from the timer to determine when to read these registers.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.9.2 Path Code Violation Count Register (PCVCR) In T1 operation, the Path Code Violation Count Register records either Ft, Fs, or CRC-6 errors. When the receive side of a framer is set to operate in the T1 ESF framing mode, PCVCR will record errors in the CRC-6 codewords. When set to operate in the T1 D4 framing mode, PCVCR will count errors in the Ft framing bit position. Via the ERCNT.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.10 DS0 Monitoring Function The DS26518 can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive direction at the same time. Table 9-32 shows the registers related to the control of transmit and receive DS0. Table 9-32. Registers Related to DS0 Monitoring REGISTER FRAMER 1 ADDRESSES FUNCTION Transmit DS0 Channel Monitor Select Register (TDS0SEL) 189h Transmit channel to be monitored.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.11 Transmit Per-Channel Idle Code Generation Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. The Transmit Idle Code Definition Registers (TIDR1–32) are provided to set the 8-bit idle code for each channel. The Transmit Channel Idle Code Enable registers (TCICE1–4) are used to enable idle code replacement on a perchannel basis. 9.9.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.15 T1 Programmable In-Band Loop Code Generator The DS26518 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. Table 9-33. Registers Related to T1 In-Band Loop Code Generator REGISTER Transmit Code Definition Register 1 (T1TCD1) Transmit Code Definition Register 2 (T1TCD2) FRAMER 1 ADDRESSES FUNCTION 1ACh Pattern to be sent for loop code. 1ADh Length of the pattern to be sent.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.16 T1 Programmable In-Band Loop Code Detection The DS26518 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. Table 9-34. Registers Related to T1 In-Band Loop Code Detection REGISTER FRAMER 1 ADDRESSES FUNCTION Receive In-Band Code Control Register (T1RIBCC) 082h Used for selecting length of receive inband loop code register.
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DS26518 8-Port T1/E1/J1 Transceiver 9.9.17 Framer Payload Loopbacks The framer, payload, and remote loopbacks are controlled by RCR3. Table 9-35. Register Related to Framer Payload Loopbacks FRAMER 1 ADDRESSES FUNCTION Framer Loopback 083h Transmit data output from the framer is looped back to the receiver. Payload Loopback 083h The 192-bit payload data is looped back to the transmitter. Remote Loopback 083h Data recovered by the receiver is looped back to the transmitter.
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DS26518 8-Port T1/E1/J1 Transceiver 9.10 HDLC Controllers There are two HDLC controllers available for each port of the DS26518. HDLC-64 is the default HDLC controller, which is software compatible to the entire TEX series of SCTs. The HDLC-256 controller is available on the DS26518 beginning with die revision B1. (Note: Older DS26518 die revisions do not have this feature, so check the device errata.) Table 9-36 describes the features available for each controller. Table 9-36.
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DS26518 8-Port T1/E1/J1 Transceiver Table 9-37. Registers Related to the HDLC-64 REGISTER Receive HDLC-64 Control Register (RHC) Receive HDLC-64 Bit Suppress Register (RHBSE) Receive HDLC-64 FIFO Control Register (RHFC) Receive HDLC-64 Packet Bytes Available Register (RHPBA) Receive HDLC-64 FIFO Register (RHF) FRAMER 1 ADDRESSES FUNCTION 010h Mapping of the HDLC-64 to DS0 or FDL, Sa bits. 011h Receive HDLC-64 bit suppression register. 087h 0B5h Determines the watermark of the receive HDLC-64 FIFO.
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DS26518 8-Port T1/E1/J1 Transceiver 9.10.1.2 Receive Packet Bytes Available The lower 7 bits of the Receive HDLC-64 Packet Bytes Available Register (RHPBA) indicates the number of bytes (0 to 64) that can be read from the receive FIFO. The value indicated by this register informs the host as to how many bytes can be read from the receive FIFO without going past the end of a message.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 9-17. Receive HDLC-64 Message Example Configure Receive HDLC Controller (RHC, RHBSE, RHFC) Reset Receive HDLC Controller (RHC.6) Start New Message Buffer Enable Interrupts RPE and RHWM NO Interrupt? No Action Required Work Another Process. YES Read Register RHPBA Start New Message Buffer NO MS = 1? YES (MS = RHPBA[7]) Read N Bytes From Rx HDLC FIFO (RHF) N = RHPBA[5..0] Read N Bytes From Rx HDLC FIFO (RHF) N = RHPBA[5..
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DS26518 8-Port T1/E1/J1 Transceiver 9.10.2 9.10.2.1 Transmit HDLC-64 Controller FIFO Information The Transmit HDLC-64 FIFO Buffer Available Register (TFBA) indicates the number of bytes that can be written into the transmit FIFO. The count from this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer. This is a real-time register. The count remains valid and stable during the read cycle. 9.10.2.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 9-18. Transmit HDLC-64 Message Example Configure Transmit HDLC Controller (THC1,THC2,THBSE,THFC) Reset Transmit HDLC Controller (THC.5) Enable TLWM Interrupt and Verify TLWM Clear Set TEOM (THC1.2) Read TFBA N = TFBA[6..
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DS26518 8-Port T1/E1/J1 Transceiver 9.10.3 HDLC-256 Controller This device has an enhanced HDLC controller that can be mapped into up to 32 time slots, or Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). This HDLC controller has a 256-byte FIFO buffer in both the transmit and receive paths. The user can select any specific bits within the time slot(s) to assign to the HDLC-256 controller as well as specific Sa bits (E1 mode).
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DS26518 8-Port T1/E1/J1 Transceiver 9.10.3.1 HDLC-256 FIFO Control Control of the transmit and receive FIFOs is accomplished via the Receive HDLC-256 Control Register 2 (RH256CR2) and Transmit HDLC-256 Control Register 2 (TH256CR2). The FIFO control registers set the watermarks for the FIFO. When the receive FIFO fills above the data available level, the RHDA bit (RH256SR.0) is set. RHDA and THDA are real-time bits and remain set as long as the FIFO’s write pointer is above the data available level.
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DS26518 8-Port T1/E1/J1 Transceiver 9.10.3.3 Receive HDLC-256 Example The HDLC-256 status registers in the DS26518 allow for flexible software interface to meet the user’s preferences. When receiving HDLC-256 messages, the host can choose to be interrupt driven or to poll to desired status registers, or a combination of polling and interrupt processes can be used. Figure 9-19 shows an example routine for using the DS26518 HDLC-256 receiver. Figure 9-19.
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DS26518 8-Port T1/E1/J1 Transceiver 9.10.3.4 Transmit HDLC-256 Example The HDLC-256 status registers in the DS26518 allow for flexible software interface to meet the user’s preferences. When transmitting HDLC-256 messages, the host can choose to be interrupt driven or to poll to desired status registers, or a combination of polling and interrupt processes can be used. Figure 9-20 shows an example routine for using the DS26518 HDLC-256 receiver. Figure 9-20.
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DS26518 8-Port T1/E1/J1 Transceiver 9.11 Power-Supply Decoupling Table 9-39. Recommended Supply Decoupling SUPPLY PINS DECOUPLING CAPACITANCE DVDD33/DVSS 0.01μF + 0.1μF + 1μF + 10μF — DVDD18/DVSS 0.01μF + 0.1μF + 1μF + 10μF — ATVDD/ATVSS 0.1μF (x8) + 1μF (x4) + 10μF (x2) ARVDD/ARVSS 0.1μF (x8) + 1μF (x4) + 10μF (x2) ACVDD/ACVSS 0.1μF + 1μF + 10μF NOTES It is recommended to use one 0.
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DS26518 8-Port T1/E1/J1 Transceiver 9.12 Line Interface Units (LIUs) The DS26518 has eight identical LIU transmit and receive front-ends for each of the eight framers. Each LIU contains three sections: the transmitter, which waveshapes and drives the network line; the receiver, which handles clock and data recovery; and the jitter attenuator. The DS26518 LIUs can switch between T1 or E1 networks without changing any external components on either the transmit or receive side.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 9-21. Network Connection—Longitudinal Protection TX TIP F1 T1 1 uF T3 TTIPn S3 S1 S7 560 pF S4 TX RING TRINGn 2:1 F2 DS26518 RX TIP F3 T2 T4 RTIPn S5 S2 S8 RRINGn 1:1 F4 NAME DESCRIPTION F1 to F4 S1, S2 S3, S4, S5, S6 S7, S8 T1 and T2 T3 and T4 RT RT S6 RX RING PART MANUFACTURER NOTES 1.25A Slow Blow Fuse 1.25A Slow Blow Fuse 25V (max) Transient Suppressor SMP 1.
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DS26518 8-Port T1/E1/J1 Transceiver 9.12.1 LIU Operation The analog AMI/HDB3 waveforms off of the E1 lines or the AMI/B8ZS waveform off of the T1 lines are transformer coupled into the RTIPn and RRINGn pins of the DS26518. The user has the option to use internal termination, software selectable for 75Ω/100Ω/110Ω/120Ω applications, or external termination. The LIU recovers clock and data from the analog signal and passes it through the jitter attenuation mux.
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DS26518 8-Port T1/E1/J1 Transceiver 9.12.2 Transmitter NRZ data arrives from the framer transmitter; the data is encoded with HDB3 or B8ZS or AMI. The encoded data passes through a jitter attenuator if it is enabled for the transmit path. A digital sequencer and DAC are used to generate transmit waveforms compliant with T1.102 and G.703 pulse templates. A line driver is used to drive an internal matched impedance circuit for provision of 75Ω, 100Ω, 110Ω, and 120Ω terminations.
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DS26518 8-Port T1/E1/J1 Transceiver 9.12.2.1 Transmit-Line Pulse Shapes The DS26518 transmitters can be selected individually to meet the pulse templates for E1 and T1/J1 modes. The T1/J1 pulse template is shown in Figure 9-22. The E1 pulse template is shown in Figure 9-23. The transmit pulse shape can be configured for each LIU on an individual basis.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 9-23. E1 Transmit Pulse Templates 1.2 1.1 269ns SCALED AMPLITUDE (in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 1.0 0.9 0.8 0.7 G.703 Template 194ns 0.6 0.5 219ns 0.4 0.3 0.2 0.1 0 -0.1 -0.
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DS26518 8-Port T1/E1/J1 Transceiver 9.12.2.2 Transmit G.703 Section 10 Synchronization Signal The DS26518 can transmit a 2.048MHz square-wave synchronization clock as specified in Section 10 of ITU-T G.703. To use this mode, set the transmit G.703 synchronization clock bit (TG703) found in the LIU Transmit Impedance and Pulse Shape Selection Register (LTIPSR). This mode also requires a 1μF blocking capacitor between TTIPn and the transformer.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 9-24. Receive LIU Termination Options LRISMR.RIMPON RECEIVE LIU TFR RTIPn 1:1 Rx LINE RT RT RRINGn The device couples to the receive E1 or T1 twisted pair (or coaxial cable in 75Ω E1 applications) via a 1:1 or 2:1 transformer. See Table 9-42 for transformer details. Receive sensitivity is configurable by setting the appropriate RSMS[1:0] bits (LRCR). The DS26518 uses a digital clock recovery system.
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DS26518 8-Port T1/E1/J1 Transceiver 9.12.3.4 Receiver Monitor Mode The receive equalizer is equipped with a monitor mode function that is used to overcome the signal attenuation caused by the resistive bridge used in monitoring applications. This function allows for a resistive gain of up to 32dB along with cable attenuation of 12dB to 30dB as shown in the LIU Receive Control Register (LRCR). Figure 9-25.
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DS26518 8-Port T1/E1/J1 Transceiver Table 9-43. T1.231, G.775, and ETS 300 233 Loss Criteria Specifications CRITERIA Loss Detection Loss Reset 9.12.3.6 T1.231 No pulses are detected for 175 ±75 bits. Loss is terminated if a duration of 12.5% ones are detected over duration of 175 ±75 bits. Loss is not terminated if 8 consecutive zeros are found if B8ZS encoding is used. If B8ZS is not used, loss is not terminated if 100 consecutive pulses are zero. STANDARD ITU-T G.
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DS26518 8-Port T1/E1/J1 Transceiver 9.12.4 Hitless Protection Switching (HPS) Many current redundancy protection implementations use mechanical relays to switch between primary and backup boards. The switching time in relays is typically in the milliseconds, making T1/E1 HPS impossible. The switching event will likely cause frame-synchronization loss in any equipment downstream, affecting the quality of service.
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DS26518 8-Port T1/E1/J1 Transceiver 9.12.5 Jitter Attenuator Each LIU contains a jitter attenuator that can be set to a depth of 32 or 128 bits via the JADS bits in the LIU Transmit and Receive Control Register (LTRCR). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay sensitive applications. The characteristics of the attenuation are shown in Figure 9-27.
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DS26518 8-Port T1/E1/J1 Transceiver 9.12.6 LIU Loopbacks The DS26518 provides four LIU loopbacks for diagnostic purposes: Analog Loopback, Local Loopback, Remote Loopback 1, and Remote Loopback 2. Dual Loopback is a combination of Local Loopback and Remote Loopback 1. In the loopback diagrams that follow, TSERn, TCLKn, RSERn, and RCLKn are inputs/outputs from the framer. Figure 9-28.
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DS26518 8-Port T1/E1/J1 Transceiver 9.12.6.2 Local Loopback The transmit system data is looped back to the receive framer. This data is also encoded and output on TTIPn and TRINGn. Signals at RTIPn and RRINGn are ignored. This loopback is conceptually shown in Figure 9-30. Figure 9-30. Local Loopback TCLK TSER TTIP Transmit Framer Optional Jitter Attenuator Transmit Analog Transmit Digital Line Driver RCLK RSER 9.12.6.
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DS26518 8-Port T1/E1/J1 Transceiver 9.12.6.5 Dual Loopback The inputs decoded from the receive LIU are looped back to the transmit LIU. The inputs from the transmit framer are looped back to the receiver with the optional jitter attenuator. Dual Loopback is a combination of Local Loopback and Remote Loopback 1. This loopback is invoked by setting the correct bits in the LIU Maintenance Control Register (LMCR). This loopback is conceptually shown in Figure 9-32. Figure 9-32.
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DS26518 8-Port T1/E1/J1 Transceiver 9.13 Bit Error-Rate Test Function (BERT) The BERT (Bit Error Rate Tester) block can generate and detect both pseudorandom and repeating bit patterns. It is used to test and stress data-communication links. BERT functionality is dedicated for each of the transceivers. The registers related to the configure, control, and status of the BERT are shown in Table 9-45. Table 9-45.
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DS26518 8-Port T1/E1/J1 Transceiver The BERT block can generate and detect the following patterns: • The pseudorandom patterns 2E7-1, 2E9-1, 2E11-1, 2E15-1, and QRSS. • A repetitive pattern from 1 to 32 bits in length. • Alternating (16-bit) words that flip every 1 to 256 words. • Daly pattern (modified 55 Octet pattern), 55 Octet pattern. The BERT function must be enabled and configured in the TXPC and RXPC registers for each port.
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DS26518 8-Port T1/E1/J1 Transceiver 10. DEVICE REGISTERS Thirteen address bits are used to control the settings of the registers. The registers control functions of the framers, LIUs, and BERTs within the DS26518. The map is divided into eight framers, followed by eight LIUs and eight BERTs. Global registers (applicable to all eight transceivers and BERTs) are located within the address space of Framer 1. The register details are provided in the following tables.
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DS26518 8-Port T1/E1/J1 Transceiver 10.1.1 Global Register List Table 10-2.
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DS26518 8-Port T1/E1/J1 Transceiver 10.1.2 Framer Register List Table 10-3. Framer Register List Note that only Framer 1 address is presented here. The same set of registers definitions applies for transceivers 2 to 8 in accordance with the DS26518 map offsets. Transceiver offset is [(n - 1) x 200 hex], where n designates the transceiver in question.
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DS26518 8-Port T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS 03Eh 03Fh 040h 041h 042h 043h 044h 045h 046h 047h 048h 049h 04Ah 04Bh 04Ch 04Dh 04Eh 04Fh 050h 051h 052h 053h 054h 055h 056h 057h 058h 059h 05Ah 05Bh 060h 061h 062h 063h 064h 065h 066h 067h 068h 069h 06Ah 06Bh 06Ch 06Dh 06Eh 06Fh 070h–07Fh NAME RIDR30 T1RDMWE3 RIDR31 RIDR32 RS1 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16 LCVCR1 LCVCR2 PCVCR1 PCVCR2 FOSCR1 FOSCR2 E1EBCR1 E1EBCR2 FEACR1 FEACR2 FEBCR1 FEBCR2 RDS0M — T1RFDL
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DS26518 8-Port T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS NAME DESCRIPTION R/W 080h RMMR RCR1 RCR1 T1RIBCC E1RCR2 RCR3 RIOCR RESCR ERCNT RHFC RIBOC T1RSCC RXPC RBPBS — RHBS — RLS1 RLS2 RLS2 RLS3 RLS3 RLS4 RLS5 — RLS7 RLS7 — RSS1 RSS2 RSS3 RSS4 T1RSCD1 T1RSCD2 — RIIR RIM1 RIM2 RIM3 RIM3 RIM4 RIM5 — RIM7 RIM7 — RSCSE1 RSCSE2 RSCSE3 RSCSE4 T1RUPCD1 T1RUPCD2 T1RDNCD1 Receive Master Mode Register Receive Control Register 1 (T1 Mode) Receive Control Register 1 (E1 Mode) Receive In-Band Code Control R
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DS26518 8-Port T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS NAME 0AFh 0B0h 0B1h T1RDNCD2 RRTS1 — RRTS3 RRTS3 — RRTS5 RHPBA RHF — RBCS1 RBCS2 RBCS3 RBCS4 RCBR1 RCBR2 RCBR3 RCBR4 RSI1 RSI2 RSI3 RSI4 RGCCS1 RGCCS2 RGCCS3 RGCCS4 RCICE1 RCICE2 RCICE3 RCICE4 RBPCS1 RBPCS2 RBPCS3 RBPCS4 — RHCS1 RHCS2 RHCS3 RHCS4 — Global Registers (Section 10.
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DS26518 8-Port T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS NAME 10Ah 110h 111h 112h 113h 114h 115h–117h 118h 119h 11Ah 11Bh 11Ch–11Fh 120h 121h 122h 123h 124h 125h 126h 127h 128h 129h 12Ah 12Bh 12Ch 12Dh 12Eh 12Fh 130h 131h 132h 133h 134h 135h 136h 137h 138h 139h 13Ah 13Bh 13Ch 13Dh 13Eh 13Fh 140h 141h 142h 143h 144h 145h 146h 147h 148h TDDS3 THC1 THBSE — THC2 E1TSACR — SSIE1 SSIE2 SSIE3 SSIE4 — TIDR1 TIDR2 TIDR3 TIDR4 TIDR5 TIDR6 TIDR7 TIDR8 TIDR9 TIDR10 TIDR11 TIDR12 TIDR13 TIDR14 TIDR15 TIDR16 T
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DS26518 8-Port T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS NAME 149h 14Ah 14Bh 14Ch 14Dh 14Eh 14Fh 150h 151h 152h 153h 154h–161h 162h 163h TS10 TS11 TS12 TS13 TS14 TS15 TS16 TCICE1 TCICE2 TCICE3 TCICE4 — T1TFDL T1TBOC T1TSLC1 E1TAF T1TSLC2 E1TNAF T1TSLC3 E1TSiAF E1TSiNAF E1TRA E1TSa4 E1TSa5 E1TSa6 E1TSa7 E1TSa8 — TMMR TCR1 TCR1 T1.TCR2 E1.
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DS26518 8-Port T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS NAME 1A2h 1A3h–1ABh 1ACh 1ADh 1AEh–1B0h 1B1h 1B2h 1B3h 1B4h 1B5h–1BAh 1BBh 1BCh–1BFh 1C0h 1C1h 1C2h 1C3h 1C4h 1C5h 1C6h 1C7h 1C8h 1C9h 1CAh TIM3 — T1TCD1 T1TCD2 — TRTS2 — TFBA THF — TDS0M — TBCS1 TBCS2 TBCS3 TBCS4 TCBR1 TCBR2 TCBR3 TCBR4 THSCS1 THSCS2 THSCS3 1CBh THSCS4 1CCh 1CDh 1CEh 1CFh 1D0h 1D1h 1D2h 1D3h 1D4h 1D5h 1D6h 1D7h 1DCh 1DDh 1DEh 1DFh 1E0h–1FFh TGCCS1 TGCCS2 TGCCS3 TGCCS4 PCL1 PCL2 PCL3 PCL4 TBPCS1 TBPCS2 TBPCS3 TBPCS4 THC
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DS26518 8-Port T1/E1/J1 Transceiver 10.1.3 LIU Register List Table 10-4. LIU Register List Note that only the LIU 1 address is presented here. The same set of registers definitions applies for LIUs 2 to 8 in accordance with the DS26518 map offsets. LIU offset is [1000+ (n - 1) x 20 hex], where n designates the LIU in question.
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DS26518 8-Port T1/E1/J1 Transceiver 10.1.4 BERT Register List Table 10-5. BERT Register List Note that only the BERT 1 address is presented here. The same set of registers definitions applies for BERTs 2 to 8 in accordance with the DS26518 map offsets. BERT offset is [1100+ (n - 1) x 10 hex], where n designates the BERT channel in question.
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DS26518 8-Port T1/E1/J1 Transceiver 10.1.5 HDLC-256 Register List Table 10-6. HDLC-256 Register List Note that only the HDLC-256 1 address is presented here. The same set of registers definitions applies for HDLC-256s 2 to 8 in accordance with the DS26518 map offsets. HDLC-256 offset is {1500+ (n - 1) x 20 hex}, where n designates the HDLC-256 in question.
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DS26518 8-Port T1/E1/J1 Transceiver 10.2 Register Bit Maps 10.2.1 Global Register Bit Map Table 10-7.
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DS26518 8-Port T1/E1/J1 Transceiver 10.2.2 Framer Register Bit Map Table 10-8 contains the framer registers of the DS26518. Some registers have dual functionality based on the selection of T1/J1 or E1 operating mode in the RMMR and TMMR registers. These dual-function registers are shown below using two lines of text. The first line of text is the bit functionality for T1/J1 mode. The second line is the bit functionality in E1 mode, in italics.
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DS26518 8-Port T1/E1/J1 Transceiver ADDR 038h 039h 03Ah 03Bh 03Ch 03Dh 03Eh NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 T1RSAOI1 RIDR25 T1RSAOI2 RIDR26 T1RSAOI3 RIDR27 CH8 C7 CH16 C7 CH24 C7 CH7 C6 CH15 C6 CH23 C6 CH6 C5 CH14 C5 CH22 C5 CH5 C4 CH13 C4 CH21 C4 CH4 C3 CH12 C3 CH20 C3 CH3 C2 CH11 C2 CH19 C2 CH2 C1 CH10 C1 CH18 C1 CH1 C0 CH9 C0 CH17 C0 — — — — — — — — C7 C6 C5 C4 C3 C2 C1 C0 CH8 C7 CH16 C7 CH24 C7 — C7 CH1-A 0 CH2-A CH7 C6 CH15 C6 CH23 C6 — C6 CH1-B
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DS26518 8-Port T1/E1/J1 Transceiver ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 050h 051h 052h 053h 054h 055h 056h 057h 058h 059h 05Ah 05Bh 060h 061h LCVCR1 LCVCR2 PCVCR1 PCVCR2 FOSCR1 FOSCR2 E1EBCR1 E1EBCR2 FEACR1 FEACR2 FEBCR1 FEBCR2 RDS0M — LCVC15 LCVC7 PCVC15 PCVC7 FOS15 FOS7 EB15 EB7 FEACR15 FEACR7 FEBCR15 FEBCR7 B1 — LCVC14 LCVC6 PCVC14 PCVC6 FOS14 FOS6 EB14 EB6 FEACR14 FEACR6 FEBCR14 FEBCR6 B2 — LCVC13 LCVC5 PCVC13 PCVC5 FOS13 FOS5 EB13 EB5 FEACR13 FEACR5 FEBCR13 FEBCR5 B3
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DS26518 8-Port T1/E1/J1 Transceiver ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 08Bh RBPBS BPBSE8 BPBSE7 BPBSE6 BPBSE5 BPBSE4 BPBSE3 BPBSE2 BPBSE1 08Ch — — — — — — — — — 08Dh 08Eh– 08Fh 090h RHBS RHBSE8 RHBSE7 RHBSE6 RHBSE5 RHBSE4 RHBSE3 RHBSE2 RHBSE1 — — — — — — — — — RLS1 RRAIC RAISC RLOSC RLOFC RRAID RAISD RLOSD RLOFD RLS2 (T1) — — COFA 8ZD 16ZD SEFE B8ZS FBE RLS2 (E1) — CRCRC CASRC FASRC RSA1 RSA0 RCMF RAF 091h RL
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DS26518 8-Port T1/E1/J1 Transceiver ADDR 0B2h 0B3h 0B4h 0B5h 0B6h 0B7h– 0BFh 0C0h 0C1h 0C2h NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RRTS3 (T1) RRTS3 (E1) — RRTS5 RHPBA RHF — — — — MS RHD7 — — — PS2 RPBA6 RHD6 — — — PS1 RPBA5 RHD5 — — — PS0 RPBA4 RHD4 LORC LORC — — RPBA3 RHD3 LSP — — — RPBA2 RHD2 LDN V52LNK — RHWM RPBA1 RHD1 LUP RDMA — RNE RPBA0 RHD0 — — — — — — — — — RBCS1 RBCS2 RBCS3 CH8 CH16 CH24 — CH32 CH8 CH16 CH24 — CH32 CH8 CH16 CH24 — CH32 CH8 CH16 CH24 — CH
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DS26518 8-Port T1/E1/J1 Transceiver ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 104h 105h 106h 107h 108h 109h 10Ah 110h 111h 112h TJBE1 TJBE2 TJBE3 TJBE4 TDDS1 TDDS2 TDDS3 THC1 THBSE — 113h THC2 CH8 CH16 CH24 CH32 CH8 CH16 CH24 NOFS TBSE8 — TABT CH7 CH15 CH23 CH31 CH7 CH15 CH23 TEOML TBSE7 — SBOC CH6 CH14 CH22 CH30 CH6 CH14 CH22 THR TBSE6 — THCEN CH5 CH13 CH21 CH29 CH5 CH13 CH21 THMS TBSE5 — THCS4 CH4 CH12 CH20 CH28 CH4 CH12 CH20 TFS TBSE4 — THCS3 CH3 CH11 CH19 CH27 CH3 CH11
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DS26518 8-Port T1/E1/J1 Transceiver ADDR NAME 13Ah TIDR27 13Bh TIDR28 13Ch TIDR29 13Dh TIDR30 13Eh TIDR31 13Fh TIDR32 140h TS1 141h TS2 142h TS3 143h TS4 144h TS5 145h TS6 146h TS7 147h TS8 148h TS9 149h TS10 14Ah TS11 14Bh TS12 14Ch TS13 14Dh TS14 14Eh TS15 14Fh TS16 150h 151h 152h TCICE1 TCICE2 TCICE3 153h TCICE4 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 — — — — — — — — C7 — C6 — C5 — C4 — C3 — C2 — C1 — C0 — C7 — C7 — C6 — C
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DS26518 8-Port T1/E1/J1 Transceiver ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 154h– 161h — — — — — — — — — 162h T1TFDL 163h T1TBOC TFDL7 — — TFDL6 — — TFDL5 — TBOC5 TFDL4 — TBOC4 TFDL3 — TBOC3 TFDL2 — TBOC2 TFDL1 — TBOC1 TFDL0 — TBOC0 T1TSLC1 — C8 — C7 — C6 — C5 — C4 — C3 — C2 — C1 E1TAF T1TSLC2 Si M2 0 M1 0 S=0 1 S=1 1 S=0 0 C11 1 C10 1 C9 E1TNAF T1TSLC3 E1TSiAF Si S=1 TSiF14 — 1 S4 TSiF12 — A S3 TSiF10 — Sa4 S2 TSiF8 — Sa5 S1 TSiF6 —
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DS26518 8-Port T1/E1/J1 Transceiver ADDR NAME 18Eh TSYNCC 18Fh — 190h TLS1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 — — — — — TSEN SYNCE RESYNC — — — — CRC4 TSEN SYNCE RESYNC — TESF — TESEM — TSLIP — TSLC96 — — — TMF — LOTCC — LOTC TESF TESEM TSLIP — TAF TMF LOTCC LOTC — — — TFDLE TUDR TMEND TLWMS TNFS 191h TLS2 — — — — TUDR TMEND TLWMS TNFS 192h 193h– 19Eh 19Fh TLS3 — — — — — — LOF LOFD — — — — — — — — — TIIR 1A0h
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DS26518 8-Port T1/E1/J1 Transceiver ADDR NAME 1CFh TGCCS4 1D0h 1D1h 1D2h PCL1 PCL2 PCL3 1D3h PCL4 1D4h 1D5h 1D6h TBPCS1 TBPCS2 TBPCS3 1D7h TBPCS4 1DCh 1DDh 1DEh THCS1 THCS2 THCS3 1DFh THCS4 1E0h– 1FFh — BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 — — — — — — — — CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25(F-bit) CH8 CH16 CH24 — CH7 CH15 CH23 — CH6 CH14 CH22 — CH5 CH13 CH21 — CH4 CH12 CH20 — CH3 CH11 CH19 — CH2 CH10 CH18 — CH1 CH9 CH17 — CH32 CH31 CH30 CH2
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DS26518 8-Port T1/E1/J1 Transceiver 10.2.3 LIU Register Bit Map Table 10-9.
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DS26518 8-Port T1/E1/J1 Transceiver 10.2.4 BERT Register Bit Map Table 10-10.
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DS26518 8-Port T1/E1/J1 Transceiver 10.2.5 HDLC-256 Register Bit Map Table 10-11.
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DS26518 8-Port T1/E1/J1 Transceiver 10.3 Global Register Definitions Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status, framer interrupt status, IBO configuration, MCLK configuration, and BPCLK1 configuration. The global registers bit descriptions are presented below. Table 10-12.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name Register Description: Register Address: Bit # Name Default 7 GPSEL3 0 GTCR1 Global Transceiver Control Register 1 00F0h 6 GPSEL2 0 5 GPSEL1 0 4 — 0 3 528MD 0 2 GIBO 0 1 GCLE 0 0 GIPI 0 Bits 7 to 5: General-Purpose I/O Pins Select (GPSEL[3:1]) Table 10-13.
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DS26518 8-Port T1/E1/J1 Transceiver GFCR1 Global Framer Control Register 1 00F1h Register Name: Description: Register Address: Bit # Name Default 7 IBOMS1 0 6 IBOMS0 0 5 BPCLK1 0 4 BPCLK0 0 3 — 0 2 RFMSS 0 1 TCBCS 0 0 RCBCS 0 Bits 7 and 6: Interleave Bus Operation Mode Select 1 and 0 (IBOMS[1:0]). These bits determine configuration of the IBO (interleaved bus) multiplexer and inform the framers of the IBO configuration.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 GTCR3 Global Transceiver Control Register 3 00F2h 6 — 0 5 — 0 4 — 0 3 — 0 2 — 0 1 TSSYNCIOSEL 0 0 TSYNCSEL 0 Bit 1: Transmit System Synchronization I/O Select (TSSYNCIOSEL) 0 = TSSYNCIO[8:1] are inputs on TSYNC/TSSYNCIO[8:1] pins 1 = TSSYNCIO[8:1] are outputs synchronous to BPCLK1.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: GTCCR1 Global Transceiver Clock Control Register 1 00F3h Register Description: Register Address: Bit # Name Default 7 6 5 4 3 2 1 0 BPREFSEL3 BPREFSEL2 BPREFSEL1 BPREFSEL0 BFREQSEL FREQSEL MPS1 MPS0 0 0 0 0 0 0 0 0 Bits 7 to 4: Backplane Clock Reference Selects (BPREFSEL[3:0]). These bits select which reference clock source will be used for BPCLK1 generation.
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DS26518 8-Port T1/E1/J1 Transceiver Table 10-15. Backplane Reference Clock Select BPREFSEL3 BPREFSEL2 BPREFSEL1 BPREFSEL0 BFREQSEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 133 of 312 REFERENCE CLOCK SOURCE 2.048MHz RCLK1 1.544MHz RCLK1 2.048MHz RCLK2 1.544MHz RCLK2 2.048MHz RCLK3 1.544MHz RCLK3 2.048MHz RCLK4 1.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default GTCCR3 Global Transceiver Clock Control Register 3 00F4h 7 6 5 — RSYSCLKSEL TSYSCLKSEL 0 0 0 4 TCLKSEL 0 3 CLKOSEL3 0 2 CLKOSEL2 0 1 CLKOSEL1 0 0 CLKOSEL0 0 Bit 6: RSYSCLKn Select (RSYSCLKSEL) 0 = Use RSYSCLKn pins for each receive system clock (Channels 1–8). 1 = Use BPCLK1 as the master clock for all eight receive system clocks (Channels 1–8).
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 HIS8 0 GHISR Global HDLC-256 Interrupt Status Register 00F5h 6 HIS7 0 5 HIS6 0 4 HIS5 0 3 HIS4 0 2 HIS3 0 1 HIS2 0 0 HIS1 0 The GHISR register reports the HDLC-256 interrupt status for Channels 1 through 8. A logic one in the associated bit location indicates an HDLC-256 has set its interrupt signal. Bit 7: HDLC-256 Interrupt Status 8 (HIS8) 0 = HDLC-256 8 has not issued an interrupt.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default GSRR1 Global Software Reset Register 1 00F6h 7 6 5 4 3 — — — — H256RST 0 0 0 0 0 2 LRST 0 1 BRST 0 0 FRST 0 Bit 3: HDLC-256 Software Reset (H256RST). HDLC-256 Channels 1–8 logic and registers are reset with a 0-to-1 transition in this bit. The reset is released when a zero is written to this bit. 0 = Normal operation. 1 = Reset HDLC-256 channels 1–8.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 HIM8 0 GHIMR Global HDLC-256 Interrupt Mask Register 00F7h 6 HIM7 0 5 HIM6 0 4 HIM5 0 Bit 7: HDLC-256 Interrupt Mask 8 (HIM8) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6: HDLC-256 Interrupt Mask 7 (HIM7) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5: HDLC-256 Interrupt Mask 6 (HIM6) 0 = Interrupt masked. 1 = Interrupt enabled.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: IDR Device Identification Register 00F8h Register Description: Register Address: Bit # Name Default 7 ID7 1 6 ID6 1 5 ID5 0 4 ID4 1 3 ID3 0 2 ID2 0 1 ID1 0 0 ID0 0 Bits 7 to 3: Device ID (ID[7:3]). The upper five bits of the IDR are used to display the DS26518 ID. Table 10-16.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 FIS8 0 GFISR1 Global Framer Interrupt Status Register 1 00F9h 6 FIS7 0 5 FIS6 0 4 FIS5 0 3 FIS4 0 2 FIS3 0 1 FIS2 0 0 FIS1 0 The GFISR1 register reports the framer interrupt status for the T1/E1 framers of Channels 1 to 8. A logic one in the associated bit location indicates a framer has set its interrupt signal.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 BIS8 0 GBISR1 Global BERT Interrupt Status Register 1 00FAh 6 BIS7 0 5 BIS6 0 4 BIS5 0 3 BIS4 0 2 BIS3 0 1 BIS2 0 0 BIS1 0 The GBISR1 register reports the interrupt status for the T1/E1 bit error rate testers (BERT) of Channels 1 to 8. A logic one in the associated bit location indicates a BERT has set its interrupt signal.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 LIS8 0 GLISR1 Global LIU Interrupt Status Register 1 00FBh 6 LIS7 0 5 LIS6 0 4 LIS5 0 3 LIS4 0 2 LIS3 0 1 LIS2 0 0 LIS1 0 The GLISR1 register reports the LIU interrupt status for the T1/E1 LIUs of Channels 1 to 8. A logic one in the associated bit location indicates a LIU has set its interrupt signal. Bit 7: LIU Interrupt Status 8 (LIS8) 0 = LIU 8 has not issued an interrupt.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 FIM8 0 GFIMR1 Global Framer Interrupt Mask Register 1 00FCh 6 FIM7 0 5 FIM6 0 4 FIM5 0 Bit 7: Framer 8 Interrupt Mask (FIM8) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6: Framer 7 Interrupt Mask (FIM7) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5: Framer 6 Interrupt Mask (FIM6) 0 = Interrupt masked. 1 = Interrupt enabled.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 BIM8 0 GBIMR1 Global BERT Interrupt Mask Register 1 00FDh 6 BIM7 0 5 BIM6 0 4 BIM5 0 Bit 7: BERT Interrupt Mask 8 (BIM8) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6: BERT Interrupt Mask 7 (BIM7) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5: BERT Interrupt Mask 6 (BIM6) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4: BERT Interrupt Mask 5 (BIM5) 0 = Interrupt masked.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 LIM8 0 GLIMR1 Global LIU Interrupt Mask Register 1 00FEh 6 LIM7 0 5 LIM6 0 4 LIM5 0 Bit 7: LIU Interrupt Mask 8 (LIM8) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6: LIU Interrupt Mask 7 (LIM7) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5: LIU Interrupt Mask 6 (LIM6) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4: LIU Interrupt Mask 5 (LIM5) 0 = Interrupt masked.
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DS26518 8-Port T1/E1/J1 Transceiver 10.4 Framer Register Descriptions 10.4.1 Receive Register Descriptions See Table 10-3 for the complete framer register list. Register Name: Register Description: Register Address: Bit # Name Default 7 RCRCD 0 RHC Receive HDLC-64 Control Register 010h + (200h x (n - 1)) : where n = 1 to 8 6 RHR 0 5 RHMS 0 4 RHCS4 0 3 RHCS3 0 2 RHCS2 0 1 RHCS1 0 0 RHCS0 0 Bit 7: Receive CRC-16 Display (RCRCD) 0 = Do not write received CRC-16 code to FIFO (default).
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 BSE8 0 RHBSE Receive HDLC-64 Bit Suppress Register 011h + (200h x (n - 1)) : where n = 1 to 8 6 BSE7 0 5 BSE6 0 4 BSE5 0 3 BSE4 0 2 BSE3 0 1 BSE2 0 0 BSE1 0 Bit 7: Receive Channel Bit 8 Suppress (BSE8). MSB of the channel. Set to one to stop this bit from being used. Bit 6: Receive Channel Bit 7 Suppress (BSE7). Set to one to stop this bit from being used.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RDS0SEL Receive Channel Monitor Select Register 012h + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 RCM4 0 3 RCM3 0 2 RCM2 0 1 RCM1 0 0 RCM0 0 Bits 4 to 0: Receive Channel Monitor Bits (RCM[4:0]). RCM0 is the LSB of a 5-bit channel select that determines which receive DS0 channel data will appear in the RDS0M register.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 T1RCR2 (T1 Mode) Receive Control Register 2 014h + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 RSLC96 0 3 OOF2 0 2 OOF1 0 1 RAIIE 0 0 RRAIS 0 Bit 4: Receive SLC-96 Synchronizer Enable (RSLC96). See Section 9.9.4.4 for SLC-96 details. 0 = The SLC-96 synchronizer is disabled. 1 = The SLC-96 synchronizer is enabled.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 E1RSAIMR (E1 Mode Only) Receive Sa Bit Interrupt Mask Register 014h + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 RSa4IM 0 3 RSa5IM 0 2 RSa6IM 0 1 RSa7IM 0 0 RSa8IM 0 Bit 4: Sa4 Change Detect Interrupt Mask (RSa4IM). This bit will enable the change detect interrupt for the Sa4 bits. Any change of state of the Sa4 bit will then generate an interrupt in RLS7.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RBR 0 T1RBOCC (T1 Mode Only) Receive BOC Control Register 015h + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 RBD1 0 4 RBD0 0 3 — 0 2 RBF1 0 1 RBF0 0 0 — 0 Bit 7: Receive BOC Reset (RBR). The host should set this bit to force a reset of the BOC circuitry.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name (MSB) 7 CH8 CH16 CH24 T1RSAOI1, T1RSAOI2, T1RSAOI3 (T1 Mode Only) Receive-Signaling All-Ones Insertion Registers 1 to 3 038h, 039h, 03Ah + (200h x (n - 1)) : where n = 1 to 8 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 (LSB) 0 CH1 CH9 CH17 T1RSAOI1 T1RSAOI2 T1RSAOI3 Setting any of the CH[1:24] bits in the T1RSAOI1 to T1RSAOI3 registers will cau
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RS1 to RS16 Receive-Signaling Registers 1 to 16 040h to 04Fh + (200h x (n - 1)) : where n = 1 to 8 T1 Mode: Bit # Name (MSB) 7 CH1-A CH2-A CH3-A CH4-A CH5-A CH6-A CH7-A CH8-A CH9-A CH10-A CH11-A CH12-A 6 CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B 5 CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C 4 CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH1
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: LCVCR1 Line Code Violation Count Register 1 050h + (200h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 LCVC14 0 7 LCVC15 0 5 LCVC13 0 4 LCVC12 0 3 LCVC11 0 2 LCVC10 0 1 LCVC9 0 0 LCVC8 0 Bits 7 to 0: Line Code Violation Counter Bits 15 to 8 (LCVC[15:8]). LCV15 is the MSB of the 16-bit code violation count.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: FOSCR1 Frames Out of Sync Count Register 1 054h + (200h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 FOS14 0 7 FOS15 0 5 FOS13 0 4 FOS12 0 3 FOS11 0 2 FOS10 0 1 FOS9 0 0 FOS8 0 Bits 7 to 0: Frames Out of Sync Counter Bits 15 to 8 (FOS[15:8]). FOS15 is the MSB of the 16-bit frames out of sync count.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 FEACR15 0 FEACR1 Error Count A Register 1 058h + (200h x (n - 1)) : where n = 1 to 8 6 FEACR14 0 5 FEACR13 0 4 FEACR12 0 3 FEACR11 0 2 FEACR10 0 1 FEACR9 0 0 FEACR8 0 Bits 7 to 0: Error Count A Register 1 Bits 15 to 8 (FEACR[15:8]). FEACR15 is the MSB of the 16-bit Far End A Counter.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 B1 0 RDS0M Receive DS0 Monitor Register 060h + (200h x (n - 1)) : where n = 1 to 8 6 B2 0 5 B3 0 4 B4 0 3 B5 0 2 B6 0 1 B7 0 0 B8 0 Bits 7 to 0: Receive DS0 Channel Bits (B[1:8]). Receive channel data that has been selected by the Receive Channel Monitor Select Register (RDS0SEL). B8 is the LSB of the DS0 channel (last bit to be received).
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1RFDL (T1 Mode) Receive FDL Register 062h + (200h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 RFDL6 0 7 RFDL7 0 5 RFDL5 0 4 RFDL4 0 3 RFDL3 0 2 RFDL2 0 1 RFDL1 0 0 RFDL0 0 2 CRC4SA 0 1 CASSA 0 0 FASSA 0 Note: This register has an alternate definition for E1 mode. See E1RRTS7. Bit 7: Receive FDL Bit 7 (RFDL7). MSB of the received FDL code.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default T1RBOC (T1 Mode) Receive BOC Register 63h + (200h x (n - 1)) : where n = 1 to 8 7 — 0 6 — 0 5 RBOC5 0 4 RBOC4 0 3 RBOC3 0 2 RBOC2 0 1 RBOC1 0 0 RBOC0 0 Bit 5: BOC Bit 5 (RBOC5) Bit 4: BOC Bit 4 (RBOC4) Bit 3: BOC Bit 3 (RBOC3) Bit 2: BOC Bit 2 (RBOC2) Bit 1: BOC Bit 1 (RBOC1) Bit 0: BOC Bit 0 (RBOC0) The T1RBOC register always contains the last valid BOC received.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name (MSB) 7 C8 M2 S=1 T1RSLC1, T1RSLC2, T1RSLC3 (T1 Mode) Receive SLC96 Data Link Registers 064h, 065h, 066h + (200h x (n - 1)) : where n = 1 to 8 6 C7 M1 S4 5 C6 S=0 S3 4 C5 S=1 S2 3 C4 S=0 S1 2 C3 C11 A2 1 C2 C10 A1 (LSB) 0 C1 C9 M3 T1RSLC1 T1RSLC2 T1RSLC3 Note: These registers have an alternate definition for E1 mode. See E1RAF, E1RNAF, and E1RsiAF.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 Si 0 E1RNAF (E1 Mode) E1 Receive Non-Align Frame Register 065h + (200h x (n - 1)) : where n = 1 to 8 6 1 0 5 A 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 2 SiF4 0 1 SiF2 0 0 SiF0 0 Note: This register has an alternate definition for T1 mode. See T1RSLC2.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 SiF15 0 E1RSiNAF (E1 Mode Only) Receive Si Bits of the Non-Align Frame Register 067h + (200h x (n - 1)) : where n = 1 to 8 6 SiF13 0 5 SiF11 0 4 SiF9 0 3 SiF7 0 2 SiF5 0 1 SiF3 0 0 SiF1 0 2 RRAF5 0 1 RRAF3 0 0 RRAF1 0 Bit 7: Si Bit of Frame 15 (SiF15) Bit 6: Si Bit of Frame 13 (SiF13) Bit 5: Si Bit of Frame 11 (SiF11) Bit 4: Si Bit of Frame 9 (SiF9) Bit 3: Si Bit of Frame 7 (SiF7) Bit
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RSa4F15 0 E1RSa4 (E1 Mode Only) Received Sa4 Bits Register 069h + (200h x (n - 1)) : where n = 1 to 8 6 RSa4F13 0 5 RSa4F11 0 4 RSa4F9 0 3 RSa4F7 0 2 RSa4F5 0 1 RSa4F3 0 0 RSa4F1 0 2 RSa5F5 0 1 RSa5F3 0 0 RSa5F1 0 Bit 7: Sa4 Bit of Frame 15 (RSa4F15) Bit 6: Sa4 Bit of Frame 13 (RSa4F13) Bit 5: Sa4 Bit of Frame 11 (RSa4F11) Bit 4: Sa4 Bit of Frame 9 (RSa4F9) Bit 3: Sa4 Bit of Frame 7 (
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RSa6F15 0 E1RSa6 (E1 Mode Only) Received Sa6 Bits Register 06Bh + (200h x (n - 1)) : where n = 1 to 8 6 RSa6F13 0 5 RSa6F11 0 4 RSa6F9 0 3 RSa6F7 0 2 RSa6F5 0 1 RSa6F3 0 0 RSa6F1 0 2 RSa7F5 0 1 RSa7F3 0 0 RSa7F1 0 Bit 7: Sa6 Bit of Frame 15 (RSa6F15) Bit 6: Sa6 Bit of Frame 13 (RSa6F13) Bit 5: Sa6 Bit of Frame 11 (RSa6F11) Bit 4: Sa6 Bit of Frame 9 (RSa6F9) Bit 3: Sa6 Bit of Frame 7 (
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RSa8F15 0 E1RSa8 (E1 Mode Only) Received Sa8 Bits Register 06Dh + (200h x (n - 1)) : where n = 1 to 8 6 RSa8F13 0 5 RSa8F11 0 4 RSa8F9 0 3 RSa8F7 0 2 RSa8F5 0 1 RSa8F3 0 0 RSa8F1 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 Bit 7: Sa8 Bit of Frame 15 (RSa8F15) Bit 6: Sa8 Bit of Frame 13 (RSa8F13) Bit 5: Sa8 Bit of Frame 11 (RSa8F11) Bit 4: Sa8 Bit of Frame 9 (RSa8F9) Bit 3: Sa8 Bit of Frame 7 (RSa8F7) B
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 Sa6CODE Received Sa6 Codeword Register 06Fh + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 — 0 3 Sa6n 0 2 Sa6n 0 1 Sa6n 0 0 Sa6n 0 This register will report the received Sa6 codeword per ETS 300 233. The bits are monitored on a submultiframe asynchronous basis, so the pattern reported could be one of multiple patterns that would represent a valid codeword.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RCR1 (T1 Mode) Receive Control Register 1 081h + (200h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 RB8ZS 0 7 SYNCT 0 5 RFM 0 4 ARC 0 3 SYNCC 0 2 RJC 0 1 SYNCE 0 0 RESYNC 0 Note: This register has an alternate definition for E1 mode. See RCR1. Bit 7: Sync Time (SYNCT) 0 = Qualify 10 bits. 1 = Qualify 24 bits. Bit 6: Receive B8ZS Enable (RB8ZS) 0 = B8ZS disabled. 1 = B8ZS enabled.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RCR1 (E1 Mode) Receive Control Register 1 081h + (200h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 RHDB3 0 7 — 0 5 RSIGM 0 4 RG802 0 3 RCRC4 0 2 FRC 0 1 SYNCE 0 0 RESYNC 0 Note: This register has an alternate definition for T1 mode. See RCR1. Bit 6: Receive HDB3 Enable (RHDB3) 0 = HDB3 disabled. 1 = HDB3 enabled (decoded per O.162).
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 T1RIBCC (T1 Mode) Receive In-Band Code Control Register 082h + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 RUP2 0 4 RUP1 0 3 RUP0 0 2 RDN2 0 1 RDN1 0 0 RDN0 0 2 — 0 1 — 0 0 RLOSA 0 Note: This register has an alternate definition for E1 mode. See E1RCR2.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RCR3 Receive Control Register 3 083h + (200h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 uALAW 0 7 — 0 5 RSERC 0 4 BINV1 0 3 BINV0 0 2 — 0 1 PLB 0 0 FLB 0 Bit 6: u-Law or A-Law Digital Milliwatt Code Select (uALAW) 0 = u-law code is inserted based on T1RDMWE1–3 or E1RDMWE1–4 registers. 1 = A-law code is inserted based on T1RDMWE1–3 or E1RDMWE1–4 registers.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name (MSB) 7 CH8 CH16 CH24 CH32 E1RDMWE1, E1RDMWE2, E1RDMWE3, E1RDMWE4 E1 Receive Digital Milliwatt Enable Registers 1 to 4 000h, 001h, 002h, 003h + (200h x (n - 1)) : where n = 1 to 8 6 CH7 CH15 CH23 CH31 5 CH6 CH14 CH22 CH30 4 CH5 CH13 CH21 CH29 3 CH4 CH12 CH20 CH28 2 CH3 CH11 CH19 CH27 1 CH2 CH10 CH18 CH26 (LSB) 0 CH1 CH9 CH17 CH25 E1RDMWE1 E1RDMWE2 E1RDMWE3 E1RDMWE4 Bits 7 to 0: E1 Receive Digital
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default RIOCR Receive I/O Configuration Register 084h + (200h x (n - 1)) : where n = 1 to 8 7 6 5 4 RCLKINV RCLKINV RSYNCINV RSYNCINV H100EN H100EN RSCLKM RSCLKM 0 0 0 0 3 RSMS — 0 2 RSIO RSIO 1 1 RSMS2 RSMS2 0 0 RSMS1 RSMS1 0 Bit 7: RCLKn Invert (RCLKINV) 0 = No inversion. 1 = Invert RCLKn. Bit 6: RSYNCn Invert (RSYNCINV) 0 = No inversion. 1 = Invert RSYNCn as either input or output.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default RESCR Receive Elastic Store Control Register 085h + (200h x (n - 1)) : where n = 1 to 8 7 6 RDATFMT RGCLKEN 0 0 5 — 0 4 RSZS 0 3 RESALGN 0 2 RESR 0 1 RESMDM 0 0 RESE 0 Bit 7: Receive Channel Data Format (RDATFMT) 0 = 64kbps (data contained in all 8 bits). 1 = 56kbps (data contained in 7 out of the 8 bits). Bit 6: Receive Gapped Clock Enable (RGCLKEN) 0 = RCHCLKn functions normally.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 1SECS 1SECS 0 ERCNT Error Counter Configuration Register 086h + (200h x (n - 1)) : where n = 1 to 8 6 MCUS MCUS 0 5 MECU MECU 0 4 ECUS ECUS 0 3 EAMS EAMS 0 2 FSBE — 0 1 MOSCRF — 0 0 LCVCRF LCVCRF 0 Bit 7: One-Second Select (1SECS). This bit allows for synchronization of the error counter updates between multiple ports. When ERCNT.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RHFC Receive HDLC-64 FIFO Control Register 087h + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 — 0 3 — 0 2 — 0 1 RFHWM1 0 0 RFHWM0 0 2 — 0 1 — 0 0 — 0 Bits 1 and 0 : Receive FIFO High Watermark Select (RFHWM[1:0] RFHWM1 0 0 1 1 RFHWM0 0 1 0 1 Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 Receive FIFO Watermark 4 bytes 16 bytes 32 bytes 4
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 T1RSCC (T1 Mode Only) In-Band Receive Spare Control Register 089h + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 — 0 3 — 0 2 RSC2 0 1 RSC1 0 0 RSC0 0 1 RBPFUS — 0 0 RBPEN RBPEN 0 Bits 2 to 0: Receive Spare Code Length Definition Bits (RSC[2:0]) RSC2 0 0 0 0 1 1 1 1 RSC1 0 0 1 1 0 0 1 1 RSC0 0 1 0 1 0 1 0 1 Register Name: Register Description: Register Address: Bit # Name D
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RBPBS Receive BERT Port Bit Suppress Register 08Bh + (200h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 BPBSE7 0 7 BPBSE8 0 5 BPBSE6 0 4 BPBSE5 0 3 BPBSE4 0 2 BPBSE3 0 1 BPBSE2 0 0 BPBSE1 0 Bit 7: Receive Channel Bit 8 Suppress (BPBSE8). MSB of the channel. Set to one to stop this bit from being used. Bit 6: Receive Channel Bit 7 Suppress (BPBSE7). Set to one to stop this bit from being used.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RHBS Receive HDLC-256 Bit Suppress Register 08Dh Bit # Name Default 6 RHBSE7 0 7 RHBSE8 0 5 RHBSE6 0 4 RHBSE5 0 3 RHBSE4 0 2 RHBSE3 0 1 RHBSE2 0 0 RHBSE1 0 Bit 7: Receive Channel Bit 8 Suppress (RHBSE8). MSB of the channel. Set to one to stop this bit from being used. Bit 6: Receive Channel Bit 7 Suppress (RHBSE7). Set to one to stop this bit from being used. Bit 5: Receive Channel Bit 6 Suppress (RHBSE6).
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RRAIC 0 RLS1 Receive Latched Status Register 1 090h + (200h x (n - 1)) : where n = 1 to 8 6 RAISC 0 5 RLOSC 0 4 RLOFC 0 3 RRAID 0 2 RAISD 0 1 RLOSD 0 0 RLOFD 0 Note: All bits in this register are latched and can create interrupts. Bit 7: Receive Remote Alarm Indication Condition Clear (RRAIC). Falling edge detect of RRAI. Set when a RRAI condition has cleared.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 —0 RLS2 (T1 Mode) Receive Latched Status Register 2 091h + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 COFA 0 4 8ZD 0 3 16ZD 0 2 SEFE 0 1 B8ZS 0 0 FBE 0 Note: All bits in these register are latched. This register does not create interrupts. See RLS2 for E1 Mode. Bit 5: Change of Frame Alignment Event (COFA). Set when the last resync resulted in a change of frame or multiframe alignment.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 LORCC 0 RLS3 (T1 Mode) Receive Latched Status Register 3 092h + (200h x (n - 1)) : where n = 1 to 8 6 LSPC 0 5 LDNC 0 4 LUPC 0 3 LORCD 0 2 LSPD 0 1 LDND 0 0 LUPD 0 Note: All bits in this register are latched and can create interrupts. See RLS3 for E1 Mode. Bit 7: Loss of Receive Clock Condition Clear (LORCC). Falling edge detect of LORC.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 LORCC 0 RLS3 (E1 Mode) Receive Latched Status Register 3 092h + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 V52LNKC 0 4 RDMAC 0 3 LORCD 0 2 — 0 1 V52LNKD 0 0 RDMAD 0 Note: All bits in this register are latched and can create interrupts. See RLS3 for T1 Mode. Bit 7: Loss of Receive Clock Clear (LORCC). Change of state indication.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RLS4 Receive Latched Status Register 4 093h + (200h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 RESEM 0 7 RESF 0 5 RSLIP 0 4 — 0 3 RSCOS 0 2 1SEC 0 1 TIMER 0 0 RMF 0 Note: All bits in this register are latched and can create interrupts. Bit 7: Receive Elastic Store Full Event (RESF). Set when the receive elastic store buffer fills and a frame is deleted.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RLS5 Receive Latched Status Register 5 (HDLC-64) 094h + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 ROVR 0 4 RHOBT 0 3 RPE 0 2 RPS 0 1 RHWMS 0 0 RNES 0 Note: All bits in this register are latched and can cause interrupts. Bit 5: Receive FIFO Overrun (ROVR). Set when the receive HDLC-64 controller has terminated packet reception because the FIFO buffer is full.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RLS7 (T1 Mode) Receive Latched Status Register 7 096h + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 RRAI-CI 0 4 RAIS-CI 0 3 RSLC96 0 2 RFDLF 0 1 BC 0 0 BD 0 Note: All bits in this register are latched and can create interrupts. See RLS7 for E1 Mode. Bit 5: Receive RAI-CI Detect (RRAI-CI). Set when an RAI-CI pattern has been detected by the receiver.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name RSS1, RSS2, RSS3, RSS4 Receive-Signaling Status Registers 1 to 4 098h, 099h, 09Ah, 09Bh + (200h x (n - 1)) : where n = 1 to 8 (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 (LSB) 0 CH1* CH9 CH17* CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 RSS1 RSS2 RSS3 RSS4 (E1 Mode Only) Note: Status bits in this register are latched.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 T1RSCD1 (T1 Mode Only) Receive Spare Code Definition Register 1 09Ch + (200h x (n - 1)) : where n = 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Note: Writing this register resets the detector’s integration period. Bit 7: Receive Spare Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6: Receive Spare Code Definition Bit 6 (C6).
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RIIR Receive Interrupt Information Register 9Fh + (200h x (n - 1)) : where n = 1 to 8 6 RLS7 0 5 RLS6* 0 4 RLS5 0 3 RLS4 0 2 RLS3 0 1 RLS2** 0 0 RLS1 0 * RLS6 is reserved for future use. ** Currently RLS2 does not create an interrupt, therefore this bit is not used in T1 mode.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RIM2 (E1 Mode Only) E1 Receive Interrupt Mask Register 2 0A1h + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 — 0 Bit 3: Receive-Signaling All Ones Event (RSA1) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 2: Receive-Signaling All Zeros Event (RSA0) 0 = Interrupt masked. 1 = interrupt enabled. Bit 1: Receive CRC-4 Multiframe Event (RCMF) 0 = Interrupt masked.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 LORCC 0 RIM3 (T1 Mode) Receive Interrupt Mask Register 3 0A2h + (200h x (n - 1)) : where n = 1 to 8 6 LSPC 0 5 LDNC 0 4 LUPC 0 Note: See RIM3 for E1 Mode. Bit 7: Loss of Receive Clock Condition Clear (LORCC) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6: Spare Code Detected Condition Clear (LSPC) 0 = Interrupt masked. 1 = Interrupt enabled.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default RIM3 (E1 Mode) E1 Receive Interrupt Mask Register 3 0A2h + (200h x (n - 1)) : where n = 1 to 8 7 LORCC 0 6 — 0 5 V52LNKC 0 4 RDMAC 0 Note: See RIM3 for T1 Mode. Bit 7: Loss of Receive Clock Clear (LORCC) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5: V5.2 Link Detected Clear (V52LNKC) 0 = Interrupt masked. 1 = Interrupt enabled.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RIM4 Receive Interrupt Mask Register 4 0A3h + (200h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 RESEM 0 7 RESF 0 5 RSLIP 0 4 — 0 Bit 7: Receive Elastic Store Full Event (RESF) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6: Receive Elastic Store Empty Event (RESEM) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5: Receive Elastic Store Slip Occurrence Event (RSLIP) 0 = Interrupt masked.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RIM5 Receive Interrupt Mask 5 (HDLC-64) 0A4h + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 ROVR 0 4 RHOBT 0 3 RPE 0 Bit 5: Receive FIFO Overrun (ROVR) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4: Receive HDLC-64 Opening Byte Event (RHOBT) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3: Receive Packet End Event (RPE) 0 = Interrupt masked. 1 = Interrupt enabled.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default RIM7 (T1 Mode) Receive Interrupt Mask Register 7 (BOC:FDL) 0A6h + (200h x (n - 1)) : where n = 1 to 8 7 — 0 6 — 0 5 RRAI-CI 0 4 RAIS-CI 0 3 RSLC96 0 2 RFDLF 0 1 BC 0 0 BD 0 2 — 0 1 Sa6CD 0 0 SaXCD 0 Note: See RIM7 for E1 Mode. Bit 5: Receive RAI-CI (RRAI-CI) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 4: Receive AIS-CI (RAIS-CI) 0 = Interrupt masked. 1 = Interrupt enabled.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name RSCSE1, RSCSE2, RSCSE3, RSCSE4 Receive-Signaling Change of State Enable Registers 1 to 4 0A8h, 0A9h, 0AAh, 0ABh + (200h x (n - 1)) : where n = 1 to 8 (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 (LSB) 0 CH1 CH9 CH17 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 RSCSE1 RSCSE2 RSCSE3 RSCSE4 (E1 Mode Only) Setting any of the
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 T1RUPCD1 (T1 Mode Only) Receive Up Code Definition Register 1 0ACh + (200h x (n - 1)) : where n = 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 1 C1 0 0 C0 0 Note: Writing this register resets the detector’s integration period. Bit 7: Receive Up Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6: Receive Up Code Definition Bit 6 (C6).
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 T1RDNCD1 (T1 Mode Only) Receive Down Code Definition Register 1 0AEh + (200h x (n - 1)) : where n = 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Note: Writing this register resets the detector’s integration period. Bit 7: Receive Down Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6: Receive Down Code Definition Bit 6 (C6).
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RRTS1 Receive Real-Time Status Register 1 0B0h + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 — 0 3 RRAI 0 2 RAIS 0 1 RLOS 0 0 RLOF 0 Note: All bits in this register are real-time (not latched). Bit 3: Receive Remote Alarm Indication Condition (RRAI). Set when a remote alarm is received at RRINGn and RTIPn. Bit 2: Receive Alarm Indication Signal Condition (RAIS).
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RRTS3 (T1 Mode) Receive Real-Time Status Register 3 0B2h + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 — 0 3 LORC 0 2 LSP 0 1 LDN 0 0 LUP 0 Note: All bits in this register are real-time (not latched). See RRTS3 for E1 Mode. Bit 3: Loss of Receive Clock Condition (LORC). Set when the RCLKn pin has not transitioned for one channel time.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RRTS5 Receive Real-Time Status Register 5 (HDLC-64) 0B4h + (200h x (n - 1)) : where n = 1 to 8 6 PS2 0 5 PS1 0 4 PS0 0 3 — 0 2 — 0 1 RHWM 0 0 RNE 0 Note: All bits in this register are real time. Bits 6 to 4: Receive Packet Status (PS[2:0]). These are real-time bits indicating the status as of the last read of the receive FIFO.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RHD7 0 RHF Receive HDLC-64 FIFO Register 0B6h + (200h x (n - 1)) : where n = 1 to 8 6 RHD6 0 5 RHD5 0 4 RHD4 0 3 RHD3 0 2 RHD2 0 1 RHD1 0 0 RHD0 0 Bit 7: Receive HDLC-64 Data Bit 7 (RHD7). MSB of an HDLC packet data byte.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name RCBR1, RCBR2, RCBR3, RCBR4 Receive Channel Blocking Registers 1 to 4 0C4h, 0C5h, 0C6h, 0C7h + (200h x (n - 1)) : where n = 1 to 8 (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 CH32 CH31 CH30 CH29 CH28 CH27 CH26 (LSB) 0 CH1 CH9 CH17 CH25 (F-bit) RCBR1 RCBR2 RCBR3 RCBR4 (E1 Mode Only)* Bits 7 to 0: Channel Blocking Cont
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name RGCCS1, RGCCS2, RGCCS3, RGCCS4 Receive Gapped Clock Channel Select Registers 1 to 4 0CCh, 0CDh, 0CEh, 0CFh + (200h x (n - 1)) : where n = 1 to 8 (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 CH32 CH31 CH30 CH29 CH28 CH27 CH26 (LSB) 0 CH1 CH9 CH17 CH25 (F-bit) RGCCS1 RGCCS2 RGCCS3 RGCCS4 (E1 Mode Only)* Bits 7 to 0: Ga
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name RBPCS1, RBPCS2, RBPCS3, RBPCS4 Receive BERT Port Channel Select Registers 1 to 4 0D4h, 0D5h, 0D6h, 0D7h + (200h x (n - 1)) : where n = 1 to 8 (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 (LSB) 0 CH1 CH9 CH17 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 RBPCS1 RBPCS2 RBPCS3 RBPCS4 (E1 Mode Only) Bits 7 to 0: BERT Port Cha
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DS26518 8-Port T1/E1/J1 Transceiver 10.4.2 Transmit Register Descriptions Register Name: Register Description: Register Address: THC1 Transmit HDLC-64 Control Register 1 110h + (200h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 TEOML 0 7 NOFS 0 5 THR 0 4 THMS 0 3 TFS 0 2 TEOM 0 1 TZSD 0 0 TCRCD 0 Bit 7: Number of Flags Select (NOFS) 0 = Send one flag between consecutive messages. 1 = Send two flags between consecutive messages. Bit 6: Transmit End of Message and Loop (TEOML).
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: THBSE Transmit HDLC-64 Bit Suppress 111h + (200h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 TBSE7 0 7 TBSE8 0 5 TBSE6 0 4 TBSE5 0 3 TBSE4 0 2 TBSE3 0 1 TBSE2 0 0 TBSE1 0 Bit 7: Transmit Bit 8 Suppress (TBSE8). MSB of the channel. Set to one to stop this bit from being used. Bit 6: Transmit Bit 7 Suppress (TBSE7). Set to one to stop this bit from being used. Bit 5: Transmit Bit 6 Suppress (TBSE6).
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 SiAF 0 E1TSACR E1 Transmit Sa-Bit Control Register 114h + (200h x (n - 1)) : where n = 1 to 8, for Ports 1 to 8 6 SiNAF 0 5 RA 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 Bit 7: International Bit in Align Frame Insertion Control Bit (SiAF) 0 = Do not insert data from the E1TSiAF register into the transmit data stream. 1 = Insert data from the E1TSiAF register into the transmit data stream.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name SSIE1, SSIE2, SSIE3, SSIE4 Software-Signaling Insertion Enable Registers 1 to 4 118h, 119h, 11Ah, 11Bh + (200h x (n - 1)) : where n = 1 to 8 (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 (LSB) 0 CH1 CH9 CH17 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 SSIE1 SSIE2 SSIE3 SSIE4 (E1 Mode Only) Bits 7 to 0: Software-Signaling
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TS1 to TS16 Transmit-Signaling Registers 140h to 14Fh + (200h x (n - 1)) : where n = 1 to 8 T1 Mode: Bit # Name (MSB) 7 CH1-A CH2-A CH3-A CH4-A CH5-A CH6-A CH7-A CH8-A CH9-A CH10-A CH11-A CH12-A 6 CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B 5 CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C 4 CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH1
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name TCICE1, TCICE2, TCICE3, TCICE4 Transmit Channel Idle Code Enable Registers 1 to 4 150h, 151h, 152h, 153h + (200h x (n - 1)) : where n = 1 to 8 (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 (LSB) 0 CH1 CH9 CH17 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 TCICE1 TCICE2 TCICE3 TCICE4 (E1 Mode Only) The Transmit Channel Idle
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1TFDL Transmit FDL Register 162h + (200h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 TFDL6 0 7 TFDL7 0 5 TFDL5 0 4 TFDL4 0 3 TFDL3 0 2 TFDL2 0 1 TFDL1 0 0 TFDL0 0 Note: Also used to insert Fs framing pattern in D4 framing mode. The Transmit FDL Register (T1TFDL) contains the Facility Data Link (FDL) information that is to be inserted on a byte basis into the outgoing T1 data stream.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name (MSB) 7 C8 M2 S=1 T1TSLC1, T1TSLC2, T1TSLC3 (T1 Mode) Transmit SLC-96 Data Link Registers 1 to 3 164h, 165h, 166h + (200h x (n - 1)) : where n = 1 to 8 6 C7 M1 S4 5 C6 S=0 S3 4 C5 S=1 S2 3 C4 S=0 S1 2 C3 C11 A2 1 C2 C10 A1 (LSB) 0 C1 C9 M3 T1TSLC1 T1TSLC2 T1TSLC3 Note: See E1TAF, E1TNAF, and E1TSiAF for E1 Mode.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1TSiAF (E1 Mode) Transmit Si Bits of the Align Frame Register 166h + (200h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 TSiF12 0 7 TSiF14 0 5 TSiF10 0 4 TSiF8 0 3 TSiF6 0 2 TSiF4 0 1 TSiF2 0 0 TSiF0 0 2 TSiF5 0 1 TSiF3 0 0 TSiF1 0 Bit 7: Si Bit of Frame 14 (TSiF14) Bit 6: Si Bit of Frame 12 (TSiF12) Bit 5: Si Bit of Frame 10 (TSiF10) Bit 4: Si Bit of Frame 8 (TSiF8) Bit 3: Si Bit of Frame 6 (TSiF6
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1TRA (E1 Mode Only) Transmit Remote Alarm Register 168h + (200h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 TRAF13 0 7 TRAF15 0 5 TRAF11 0 4 TRAF9 0 3 TRAF7 0 2 TRAF5 0 1 TRAF3 0 0 TRAF1 0 2 TSa4F5 0 1 TSa4F3 0 0 TSa4F1 0 Bit 7: Remote Alarm Bit of Frame 15 (TRAF15) Bit 6: Remote Alarm Bit of Frame 13 (TRAF13) Bit 5: Remote Alarm Bit of Frame 11 (TRAF11) Bit 4: Remote Alarm Bit of Frame 9 (TRAF9)
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TSa5F15 0 E1TSa5 (E1 Mode Only) Transmit Sa5 Bits Register 16Ah + (200h x (n - 1)) : where n = 1 to 8 6 TSa5F13 0 5 TSa5F11 0 4 TSa5F9 0 3 TSa5F7 0 2 TSa5F5 0 1 TSa5F3 0 0 TSa5F1 0 2 TSa6F5 0 1 TSa6F3 0 0 TSa6F1 0 Bit 7: Sa5 Bit of Frame 15 (TSa5F15) Bit 6: Sa5 Bit of Frame 13 (TSa5F13) Bit 5: Sa5 Bit of Frame 11 (TSa5F11) Bit 4: Sa5 Bit of Frame 9 (TSa5F9) Bit 3: Sa5 Bit of Frame 7 (
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TSa7F15 0 E1TSa7 (E1 Mode Only) Transmit Sa7 Bits Register 16Ch + (200h x (n - 1)) : where n = 1 to 8 6 TSa7F13 0 5 TSa7F11 0 4 TSa7F9 0 3 TSa7F7 0 2 TSa7F5 0 1 TSa7F3 0 0 TSa7F1 0 2 TSa8F5 0 1 TSa8F3 0 0 TSa8F1 0 Bit 7: Sa7 Bit of Frame 15 (TSa4F15) Bit 6: Sa7 Bit of Frame 13 (TSa7F13) Bit 5: Sa7 Bit of Frame 11 (TSa7F11) Bit 4: Sa7 Bit of Frame 9 (TSa7F9) Bit 3: Sa7 Bit of Frame 7 (
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 FRM_EN 0 TMMR Transmit Master Mode Register 180h + (200h x (n - 1)) : where n = 1 to 8 6 INIT_DONE 0 5 — 0 4 — 0 3 — 0 2 — 0 1 SFTRST 0 0 T1/E1 0 Bit 7: Framer Enable (FRM_EN). This bit must be set to the desired state before writing INIT_DONE. 0 = Framer disabled—held in low-power state. 1 = Framer enabled—all features active. Bit 6: Initialization Done (INIT_DONE).
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TJC 0 TCR1 (T1 Mode) Transmit Control Register 1 181h + (200h x (n - 1)) : where n = 1 to 8 6 TFPT 0 5 TCPT 0 4 TSSE 0 3 GB7S 0 2 TB8ZS 0 1 TAIS 0 0 TRAI 0 Note: See TCR1 for E1 Mode. Bit 7: Transmit Japanese CRC-6 Enable (TJC) 0 = Use ANSI/AT&T:ITU-T CRC-6 calculation (normal operation). 1 = Use Japanese standard JT–G704 CRC-6 calculation.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TTPT 0 TCR1 (E1 Mode) Transmit Control Register 1 181h + (200h x (n - 1)) : where n = 1 to 8 6 T16S 0 5 TG802 0 4 TSiS 0 3 TSA1 0 2 THDB3 0 1 TAIS 0 Note: See TCR1 for T1 Mode. Bit 7: Transmit Time Slot 0 Pass Through (TTPT) 0 = FAS bits/Sa bits/Remote Alarm sourced internally from the E1TAF and E1TNAF registers. 1 = FAS bits/Sa bits/Remote Alarm sourced from TSERn.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1.TCR2 (T1 Mode) Transmit Control Register 2 182h + (200h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 TSLC96 0 7 TFDLS 0 5 TDDSEN 0 4 FBCT2 0 3 FBCT1 0 2 TRAIS 0 1 — 0 0 TB7ZS 0 Note: See E1.TCR2 for E1 Mode. Bit 7: TFDL Register Select (TFDLS) 0 = Source FDL or Fs bits from the internal TFDL register or the SLC-96 data formatter (T1.TCR2.6).
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 AEBE 0 E1.TCR2 (E1 Mode) Transmit Control Register 2 182h + (200h x (n - 1)) : where n = 1 to 8 6 AAIS 0 5 ARA 0 4 — 0 Note: See T1.TCR2 for T1 Mode. Bit 7: Automatic E-Bit Enable (AEBE) 0 = E-bits not automatically set in the transmit direction. 1 = E-bits automatically set in the transmit direction.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — — 0 TCR3 Transmit Control Register 3 183h + (200h x (n - 1)) : where n = 1 to 8 6 — — 0 5 TCSS1 TCSS1 0 4 TCSS0 TCSS0 0 3 MFRS MFRS 0 2 TFM — 0 1 IBPV IBPV 0 0 TLOOP CRC4 0 Bits 5 and 4 : Transmit Clock Source Select 1 and 0 (TCSS[1:0]) TCSS1 0 TCSS0 0 0 1 1 1 0 1 Transmit Clock Source The TCLKn pin is always the source of transmit clock.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TCLKINV TCLKINV 0 TIOCR Transmit I/O Configuration Register 184h + (200h x (n - 1)) : where n = 1 to 8 6 5 TSYNCINV TSYNCINV TSSYNCINV TSSYNCINV 0 0 4 TSCLKM TSCLKM 0 3 TSSM TSSM 0 2 TSIO TSIO 0 1 TSDW — 0 0 TSM TSM 0 Bit 7: TCLKn Invert (TCLKINV) 0 = No inversion. 1 = Invert. Bit 6: TSYNCn Invert (TSYNCINV) 0 = No inversion. 1 = Invert.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TDATFMT 0 TESCR Transmit Elastic Store Control Register 185h + (200h x (n - 1)) : where n = 1 to 8 6 TGCLKEN 0 5 — 0 4 TSZS 0 3 TESALGN 0 2 TESR 0 1 TESMDM 0 0 TESE 0 Note: Bits 6 and 7 are used for fractional backplane support. See Section 9.8.5. Bit 7: Transmit Channel Data Format (TDATFMT) 0 = 64kbps (data contained in all 8 bits). 1 = 56kbps (data contained in 7 out of the 8 bits).
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 uALAW uALAW 0 TCR4 Transmit Control Register 4 186h + (200h x (n - 1)) : where n = 1 to 8 6 BINV1 BINV1 0 5 BINV0 BINV0 0 4 TJBEN TJBEN 0 3 TRAIM — 0 2 TAISM — 0 1 TC1 — 0 0 TC0 — 0 Bit 7: u-Law or A-Law Digital Milliwatt Code Select (uALAW) 0 = u-law code is inserted based on TDMWEx registers. 1 = A-law code is inserted based on TDMWEx registers.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 THFC Transmit HDLC-64 FIFO Control Register 187h + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 — 0 3 — 0 2 — 0 1 TFLWM1 0 0 TFLWM0 0 2 — 0 1 — 0 0 — 0 Bits 1 and 0: Transmit HDLC-64 FIFO Low Watermark Select (TFLWM[1:0]) TFLWM1 0 0 1 1 TFLWM0 0 1 0 1 Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 Transmit FIFO Watermark (Bytes) 4 16 32 4
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 THMS THMS 0 TXPC Transmit Expansion Port Control Register 18Ah + (200h x (n - 1)) : where n = 1 to 8 6 THEN THEN 0 5 — — 0 4 — — 0 3 — — 0 2 TBPDIR TBPDIR 0 1 TBPFUS — 0 0 TBPEN TBPEN 0 Bit 7 (T1 Mode): Transmit HDLC-256 Mode Select (THMS) 0 = Transmit HDLC-256 assigned to time slots. 1 = Transmit HDLC-256 assigned to FDL bits.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 BPBSE8 0 TBPBS Transmit BERT Port Bit Suppress Register 18Bh + (200h x (n - 1)) : where n = 1 to 8 6 BPBSE7 0 5 BPBSE6 0 4 BPBSE5 0 3 BPBSE4 0 2 BPBSE3 0 1 BPBSE2 0 0 BPBSE1 0 Bit 7: Transmit Channel Bit 8 Suppress (BPBSE8). MSB of the channel. Set to one to stop this bit from being used. Bit 6: Transmit Channel Bit 7 Suppress (BPBSE7). Set to one to stop this bit from being used.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — — 0 TSYNCC Transmit Synchronizer Control Register 18Eh + (200h x (n - 1)) : where n = 1 to 8 6 — — 0 5 — — 0 4 — — 0 3 — CRC4 0 2 TSEN TSEN 0 1 SYNCE SYNCE 0 0 RESYNC RESYNC 0 Bit 3: CRC-4 Enable (CRC4) (E1 Mode Only) 0 = Do not search for the CRC-4 multiframe word. 1 = Search for the CRC-4 multiframe word. Bit 2: Transmit Synchronizer Enable (TSEN) 0 = Transmit synchronizer disabled.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TLS1 Transmit Latched Status Register 1 190h + (200h x (n - 1)) : where n = 1 to 8 Bit # Name 6 TESEM TESEM 0 Default 7 TESF TESF 0 5 TSLIP TSLIP 0 4 TSLC96 — 0 3 — TAF 0 2 TMF TMF 0 1 LOTCC LOTCC 0 0 LOTC LOTC 0 Note: All bits in this register are latched and can cause interrupts. Bit 7: Transmit Elastic Store Full Event (TESF). Set when the transmit elastic store buffer fills and a frame is deleted.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — — 0 TLS2 Transmit Latched Status Register 2 (HDLC-64) 191h + (200h x (n - 1)) : where n = 1 to 8 6 — — 0 5 — — 0 4 TFDLE — 0 3 TUDR TUDR 0 2 TMEND TMEND 0 1 TLWMS TLWMS 0 0 TNFS TNFS 0 Note: All bits in this register are latched and can create interrupts. Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only). Set when the TFDL register has shifted out all 8 bits.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TIIR Transmit Interrupt Information Register 19Fh + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 — 0 3 — 0 2 TLS3 0 1 TLS2 0 0 TLS1 0 The interrupt information register provides an indication of which status registers are generating an interrupt.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TIM1 Transmit Interrupt Mask Register 1 1A0h + (200h x (n - 1)) : where n = 1 to 8 Bit # Name 6 TESEM TESEM 0 Default 7 TESF TESF 0 5 TSLIP TSLIP 0 4 TSLC96 — 0 3 — TAF 0 Bit 7: Transmit Elastic Store Full Event (TESF) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6: Transmit Elastic Store Empty Event (TESEM) 0 = Interrupt masked. 1 = Interrupt enabled.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — — 0 TIM2 Transmit Interrupt Mask Register 2 (HDLC-64) 1A1h + (200h x (n - 1)) : where n = 1 to 8 6 — — 0 5 — — 0 4 TFDLE — 0 3 TUDR TUDR 0 2 TMEND TMEND 0 1 TLWMS TLWMS 0 0 TNFS TNFS 0 1 — 0 0 LOFD 0 Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3: Transmit FIFO Underrun Event (TUDR) 0 = Interrupt masked.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 T1TCD1 (T1 Mode Only) Transmit Code Definition Register 1 1ACh + (200h x (n - 1)) : where n = 1 to 8 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit 7: Transmit Code Definition Bit 7 (C7). First bit of the repeating pattern.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TRTS2 Transmit Real-Time Status Register 2 (HDLC-64) 1B1h + (200h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 — 0 3 TEMPTY 0 2 TFULL 0 1 TLWM 0 0 TNF 0 Note: All bits in this register are real time. Bit 3: Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty. Bit 2: Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TDS0M Transmit DS0 Monitor Register 1BBh + (200h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 B2 0 7 B1 0 5 B3 0 4 B4 0 3 B5 0 2 B6 0 1 B7 0 0 B8 0 Bits 7 to 0: Transmit DS0 Channel Bits (B[1:8]). Transmit channel data that has been selected by the TDS0SEL register. B8 is the LSB of the DS0 channel (last bit to be transmitted).
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name TCBR1, TCBR2, TCBR3, TCBR4 Transmit Channel Blocking Registers 1 to 4 1C4h, 1C5h, 1C6h, 1C7h + (200h x (n - 1)) : where n = 1 to 8 (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 CH32 CH31 CH30 CH29 CH28 CH27 CH26 (LSB) 0 CH1 CH9 CH17 CH25 (F-bit) TCBR1 TCBR2 TCBR3 TCBR4 (E1 Mode Only)* Bits 7 to 0: Transmit Channels 1
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name TGCCS1, TGCCS2, TGCCS3, TGCCS4 Transmit Gapped Clock Channel Select Registers 1 to 4 1CCh, 1CDh, 1CEh, 1CFh + (200h x (n - 1)) : where n = 1 to 8 (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 CH32 CH31 CH30 CH29 CH28 CH27 CH26 (LSB) 0 CH1 CH9 CH17 CH25 (F-bit) TGCCS1 TGCCS2 TGCCS3 TGCCS4 (E1 Mode Only)* Bits 7 to 0: T
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name TBPCS1, TBPCS2, TBPCS3, TBPCS4 Transmit BERT Port Channel Select Registers 1D4h, 1D5h, 1D6h, 1D7h + (200h x (n - 1)) : where n = 1 to 8 (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 (LSB) 0 CH1 CH9 CH17 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 TBPCS1 TBPCS2 TBPCS3 TBPCS4 (E1 Mode Only) Setting any of the CH[1:32] bits
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DS26518 8-Port T1/E1/J1 Transceiver 10.5 LIU Register Definitions Table 10-17.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Addresses: Bit # Name Default 7 — 0 LTRCR LIU Transmit Receive Control Register 1000h + (20h x (n - 1)) : where n = 1 to 8 6 RHPM 0 5 JADS1 0 4 JADS0 0 3 JAPS1 0 2 JAPS0 0 1 T1J1E1S 0 0 LSC 0 Bit 6: Receive Hitless Protection Mode (RHPM) 0 = Normal operation using software for hitless protection (RIMPON). 1 = Hitless protection switching mode using TXENABLE pin.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TG703 0 LTIPSR LIU Transmit Impedance and Pulse Shape Selection Register 1001h + (20h x (n - 1)) : where n = 1 to 8 6 TIMPTON 0 5 TIMPL1 0 4 TIMPL0 0 3 — 0 2 L2 0 1 L1 0 0 L0 0 Bit 7: Transmit G.703 Synchronization Clock (TG703) 0 = Normal transmitter mode. 1 = G.703 2.048MHz clock transmitted on TTIPn and TRINGn.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TAIS 0 LMCR LIU Maintenance Control Register 1002h + (20h x (n - 1)) : where n = 1 to 8 6 ATAIS 0 5 LB2 0 4 LB1 0 3 LB0 0 2 TPDE 0 1 RPDE 0 0 TE 0 Bit 7: Manual Transmit AIS (TAIS). Alarm Indication Signal (AIS) is sent using MCLK as the reference clock. The transmit data coming from the framer is ignored. 0 = TAIS is disabled.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 LRSR LIU Real Status Register 1003h + (20h x (n - 1)) : where n = 1 to 8 6 — 0 5 OEQ 0 4 UEQ 0 3 RSCS 0 2 TSCS 0 1 OCS 0 0 LOSS 0 Bit 5: Over Equalized (OEQ). The equalizer is over equalized. This can happen if there very large unexpected resistive loss. This could result if monitor mode is used and the device is not placed in monitor mode.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: LSIMR LIU Status Interrupt Mask Register 1004h + (20h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 OCCIM 0 7 JALTCIM 0 5 SCCIM 0 4 LOSCIM 0 3 JALTSIM 0 Bit 7: Jitter Attenuator Limit Trip Clear Interrupt Mask (JALTCIM) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6: Open-Circuit Clear Interrupt Mask (OCCIM) 0 = Interrupt masked. 1 = Interrupt enabled.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 JALTC 0 LLSR LIU Latched Status Register 1005h + (20h x (n - 1)) : where n = 1 to 8 6 OCC 0 5 SCC 0 4 LOSC 0 3 JALTS 0 2 OCD 0 1 SCD 0 0 LOSD 0 Note: All bits in this register are latched and can create interrupts. Bit 7: Jitter Attenuator Limit Trip Clear (JALTC). This latched bit is set when a JA limit trip condition was detected and then removed. Bit 6: Open-Circuit Clear (OCC).
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DS26518 8-Port T1/E1/J1 Transceiver LRSL LIU Receive Signal Level Register 1006h + (20h x (n - 1)) : where n = 1 to 8 Register Name: Register Description: Register Address: Bit # Name Default 7 RSL3 0 6 RSL2 0 5 RLS1 0 4 RLS0 0 3 — 0 2 — 0 1 — 0 0 — 0 Bits 7 to 4: Receiver Signal Level 3 to 0 (RSL[3:0]). Real-time receive signal level as shown in Table 10-20. Note that the range of signal levels reported the RSL[3:0] is limited by the Equalizer Gain Limit (EGL) in short-haul applications.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default LRISMR LIU Receive Impedance and Sensitivity Monitor Register 1007h + (20h x (n - 1)) : where n = 1 to 8 7 — 0 6 RIMPON 0 5 — 0 4 — 0 3 — 0 2 RIMPM2 0 1 RIMPM1 0 0 RIMPM0 0 Bit 6: Receive Internal Impedance Match On (RIMPON) 0 = Receive internal impedance termination is disabled (high impedance). 1 = Receive internal impedance termination is enabled.
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DS26518 8-Port T1/E1/J1 Transceiver LRCR LIU Receive Control Register 1008h + (20h x (n - 1)) : where n = 1 to 8 Register Name: Register Description: Register Address: Bit # Name Default 7 RG703 0 6 — 0 5 — 0 4 — 0 3 RTR 0 2 RMONEN 0 1 RSMS1 0 0 RSMS0 0 Bit 7: Receive G.703 Clock (RG703). If this bit is set, the receiver expects a 2.048MHz or 1.544MHz clock from the RTIPn/RRINGn, based on the selection of T1 (1.544) or E1 (2.048) mode in the LTRCR register.
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DS26518 8-Port T1/E1/J1 Transceiver 10.6 BERT Register Definitions Table 10-24.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: BRP1 BERT Repetitive Pattern Set Register 1 1101h + (10h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 RPAT6 0 7 RPAT7 0 5 RPAT5 0 4 RPAT4 0 3 RPAT3 0 2 RPAT2 0 1 RPAT1 0 0 RPAT0 0 Bits 7 to 0: BERT Repetitive Pattern Set Bits 7 to 0 (RPAT[7:0]). RPAT0 is the LSB of the 32-bit repetitive pattern.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TC 0 BC1 BERT Control Register 1 1105h + (10h x (n - 1)) : where n = 1 to 8 6 TINV 0 5 RINV 0 4 PS2 0 3 PS1 0 2 PS0 0 1 LC 0 0 RESYNC 0 Bit 7: Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the pattern that is to be generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern.
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DS26518 8-Port T1/E1/J1 Transceiver BC2 BERT Control Register 2 1106h + (10h x (n - 1)) : where n = 1 to 8 Register Name: Register Description: Register Address: Bit # Name Default 7 EIB2 0 6 EIB1 0 5 EIB0 0 4 SBE 0 3 RPL3 0 2 RPL2 0 1 RPL1 0 0 RPL0 0 Bits 7 to 5: Error Insert Bits 2 to 0 (EIB[2:0]). Will automatically insert bit errors at the prescribed rate into the generated data pattern. Can be used for verifying error detection features. See Table 10-26. Table 10-26.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 BBC7 0 BBC1 BERT Bit Count Register 1 1107h + (10h x (n - 1)) : where n = 1 to 8 6 BBC6 0 5 BBC5 0 4 BBC4 0 3 BBC3 0 2 BBC2 0 1 BBC1 0 0 BBC0 0 Bits 7 to 0: BERT Bit Counter Bits 7 to 0 (BBC[7:0]). BBC0 is the LSB of the 32-bit counter.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 EC7 0 BEC1 BERT Error Count Register 1 110Bh + (10h x (n - 1)) : where n = 1 to 8 6 EC6 0 5 EC5 0 4 EC4 0 3 EC3 0 2 EC2 0 1 EC1 0 0 EC0 0 2 EC10 0 1 EC9 0 0 EC8 0 2 EC18 0 1 EC17 0 0 EC16 0 Bits 7 to 0: Error Counter Bits 7 to 0 (EC[7:0]). EC0 is the LSB of the 24-bit counter.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 BSR BERT Status Register 110Eh + (10h x (n - 1)) : where n = 1 to 8 6 BBED 0 5 RBA01 0 4 RSYNC 0 3 BRA1 0 2 BRA0 0 1 BRLOS 0 0 BSYNC 0 Note: All latched bits in this register can create interrupts. Bit 6: BERT Bit Error Detected Event (BBED). A latched bit that is set when a bit error is detected. The receive BERT must be in synchronization for it to detect bit errors.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 BSIM BERT Status Interrupt Mask Register 110Fh + (10h x (n - 1)) : where n = 1 to 8 6 BBED 0 5 — 0 4 — 0 3 BRA1 0 Bit 6: BERT Bit Error Detected Event (BBED) 0 = Interrupt masked. 1 = Interrupt enabled. Bit 3: BERT Receive All-Ones Condition (BRA1) 0 = Interrupt masked. 1 = Interrupt enabled—interrupts on rising and falling edges.
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DS26518 8-Port T1/E1/J1 Transceiver 10.6.1 Extended BERT Register Definitions Table 10-28.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: BLSR1 BERT Latched Status Register 1 1402h + (10h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 BRA0C 0 7 BRA1C 0 5 BRLOSC 0 4 BSYNCC 0 3 BRA1D 0 2 BRA0D 0 1 BRLOSD 0 0 BSYNCD 0 Note: All latched bits in this register can create interrupts. Bit 7: BERT Receive All-Ones Condition Clear (BRA1C). A latched bit that is set when the BERT transitions out of all-ones condition.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: BSIM1 BERT Status Interrupt Mask Register 1 1403h + (10h x (n - 1)) : where n = 1 to 8 Bit # Name Default 6 BRA0C 0 7 BRA1C 0 5 BRLOSC 0 4 BSYNCC 0 3 BRA1D 0 Bit 7: Receive All-Ones Condition Clear (BRA1C) 0 = interrupt masked 1 = interrupt enabled Bit 6: Receive All-Zeros Condition Clear (BRA0C) 0 = interrupt masked 1 = interrupt enabled Bit 5: Receive Loss of Synchronization Condition Clear (BRLOSC) 0 = inte
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 BLSR2 BERT Latched Status Register 2 1404h + (10h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 — 0 3 — 0 2 BED 0 1 BBCO 0 0 BECO 0 Note: All latched bits in this register can create interrupts. Bit 2: BERT Bit Error Detected Event (BED). A latched bit that is set when a bit error is detected. The receive BERT must be in synchronization for it to detect bit errors.
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DS26518 8-Port T1/E1/J1 Transceiver 10.7 HDLC-256 Register Definitions 10.7.1 Transmit HDLC-256 Register Definitions Table 10-29.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TH256CR1 Transmit HDLC-256 Control Register 1 1500h + (20h x (n - 1)) : where n = 1 to 8 6 TPSD 0 5 TFEI 0 4 TIFV 0 3 TBRE 0 2 TDIE 0 1 TFPD 0 0 TFRST 0 Bit 6: Transmit Packet Start Disable (TPSD). When 0, the transmit packet processor continues sending packets after the current packet end. When 1, the transmit packet processor stops sending packets after the current packet end.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TH256FDR1 Transmit HDLC-256 FIFO Data Register 1 1502h + (20h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 — 0 3 — 0 2 — 0 1 — 0 0 TDPE 0 Bit 0: Transmit FIFO Data Packet End (TDPE). When 0, the transmit FIFO data is not a packet end. When 1, the transmit FIFO data is a packet end. This bit should be written before the last byte of the packet is written into TH256FDR2.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TH256SR1 Transmit HDLC-256 Status Register 1 1504h + (20h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 — 0 3 — 0 2 TFF 0 1 TFE 0 0 THDA 0 Bit 2: Transmit FIFO Full (TFF). When 0, the transmit FIFO contains 255 or less bytes of data. When 1, the transmit FIFO is full. Bit 1: Transmit FIFO Empty (TFE). When 0, the transmit FIFO contains at least one byte of data.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TH256SRL Transmit HDLC-256 Status Register Latched 1506h + (20h x (n - 1)) : where n = 1 to 8 6 — 0 5 TFOL 0 4 TFUL 0 3 TPEL 0 2 — 0 1 TFEL 0 0 THDAL 0 Bit 5: Transmit FIFO Overflow Latched (TFOL). This bit is set when a transmit FIFO overflow condition occurs. Bit 4: Transmit FIFO Underflow Latched (TFUL). This bit is set when a transmit FIFO underflow condition occurs.
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DS26518 8-Port T1/E1/J1 Transceiver 10.7.2 Receive HDLC-256 Register Definitions Table 10-30.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RH256CR1 Receive HDLC-256 Control Register 1 1510h + (20h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 — 0 3 RBRE 0 2 RDIE 0 1 RFPD 0 0 RFRST 0 Bit 3: Receive Bit Reordering Enable (RBRE). When 0, bit reordering is disabled. (The first bit received is in the LSB of the receive FIFO data byte RFD[0].) When 1, bit reordering is enabled.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RH256SR Receive HDLC-256 Status Register 1514h+ (20h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 — 0 3 — 0 2 RFF 0 1 RFE 0 0 RHDA 0 Bit 2: Receive FIFO Full (RFF). When 0, the receive FIFO contains 255 or less bytes of data. When 1, the receive FIFO is full. Bit 1: Receive FIFO Empty (RFE). When 0, the receive FIFO contains at least one byte of data.
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RFOIE 0 RH256SRIE Receive HDLC-256 Status Register Interrupt Enable 1518h + (20h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 RPEIE 0 3 RPSIE 0 2 RFFIE 0 1 — 0 0 RHDAIE 0 Bit 7: Receive FIFO Overflow Interrupt Enable (RFOIE). This bit enables an interrupt if the RFOL bit is set. 0 = interrupt disabled 1 = interrupt enabled Bit 4: Receive Packet End Interrupt Enable (RPEIE).
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DS26518 8-Port T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RH256FDR1 Receive HDLC-256 FIFO Data Register 1 151Ch + (20h x (n - 1)) : where n = 1 to 8 6 — 0 5 — 0 4 — 0 3 RPS2 X 2 RPS1 X 1 RPS0 X 0 RFDV 0 Note: The FIFO data and status are updated when the receive FIFO data (RH256FDR2.RFD[7:0]) is read. Reading this register reflects the status of the next read of RH256FDR2. Bits 3 to 1: Receive Packet Status (RPS[2:0]).
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DS26518 8-Port T1/E1/J1 Transceiver 11. FUNCTIONAL TIMING 11.1 T1 Receiver Functional Timing Diagrams Figure 11-1. T1 Receive-Side D4 Timing 1 FRAME# 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 RFSYNCn RSYNCn1 RSYNCn2 RSYNCn3 NOTE 1: RSYNCn IN THE FRAME MODE (RIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (RIOCR.1 = 0). NOTE 2: RSYNCn IN THE FRAME MODE (RIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (RIOCR.1 = 1). NOTE 3: RSYNCn IN THE MULTIFRAME MODE (RIOCR.0 = 1). Figure 11-2.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 11-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled) RCLKn CHANNEL 23 RSERn CHANNEL 24 CHANNEL 1 LSB LSB MSB F MSB RSYNCn RFSYNCn RSIGn CHANNEL 23 A B C/A D/B CHANNEL 24 A B C/A D/B CHANNEL 1 A RCHCLKn RCHBLKn1 NOTE 1: RCHBLKn IS PROGRAMMED TO BLOCK CHANNEL 24. Figure 11-4. T1 Receive-Side 1.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 11-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) RSYSCLKn CHANNEL 31 1 CHANNEL 32 LSB MSB RSERn CHANNEL 1 LSB RSYNCn2 RMSYNCn RSYNCn3 RSIGn A CHANNEL 31 B C/A D/B A CHANNEL 32 B C/A D/B RCHCLKn RCHBLKn4 NOTE 1: RSERn DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 ARE FORCED TO ONE. NOTE 2: RSYNCn IS IN THE OUTPUT MODE (RIOCR.2 = 0). NOTE 3: RSYNCn IS IN THE INPUT MODE (RIOCR.2 = 1). NOTE 4: RCHBLKn IS PROGRAMMED TO BLOCK CHANNEL 1.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 11-6.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 11-7.
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DS26518 8-Port T1/E1/J1 Transceiver 11.2 T1 Transmitter Functional Timing Diagrams Figure 11-9. T1 Transmit-Side D4 Timing FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 TSYNCn1 TSSYNCIOn TSYNCn2 TSYNCn3 NOTE 1: TSYNCn IN THE FRAME MODE (TIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TIOCR.1 = 0). NOTE 2: TSYNCn IN THE FRAME MODE (TIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (TIOCR.1 = 1). NOTE 3: TSYNCn IN THE MULTIFRAME MODE (TIOCR.0 = 1). Figure 11-10.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 11-11. T1 Transmit-Side Boundary Timing (Elastic Store Disabled) TCLKn CHANNEL 1 TSERn LSB F CHANNEL 2 MSB LSB MSB LSB MSB TSYNCn1 TSYNCn2 CHANNEL 1 TSIGn D/B A B CHANNEL 2 C/A D/B A B C/A D/B TCHCLKn TCHBLKn3 NOTE 1: TSYNCn IS IN THE OUTPUT MODE (TIOCR.2 = 1). NOTE 2: TSYNCn IS IN THE INPUT MODE (TIOCR.2 = 0). NOTE 3: TCHBLKn IS PROGRAMMED TO BLOCK CHANNEL 2. Figure 11-12. T1 Transmit-Side 1.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 11-13. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) TSYSCLKn TSERn1 CHANNEL 31 CHANNEL 32 CHANNEL 1 LSB F3 LSB MSB TSSYNCIOn CHANNEL 31 TSIGn A B CHANNEL 32 C/A D/B A B CHANNEL 1 C/A D/B A TCHCLKn TCHBLKn2 NOTE 1: TSERn DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS IGNORED. NOTE 2: TCHBLKn IS PROGRAMMED TO BLOCK CHANNELS 31 AND 1.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 11-14.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 11-15.
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DS26518 8-Port T1/E1/J1 Transceiver 11.3 E1 Receiver Functional Timing Diagrams Figure 11-17. E1 Receive-Side Timing FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RFSYNCn RSYNCn1 RSYNCn2 NOTE 1: RSYNCn IN FRAME MODE (RIOCR.0 = 0). NOTE 2: RSYNCn IN MULTIFRAME MODE (RIOCR.0 = 1). NOTE 3: THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME. Figure 11-18.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 11-19. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled) RSYSCLKn CHANNEL 23/31 1 RSERn CHANNEL 24/32 CHANNEL 1/2 LSB LSB MSB F MSB RSYNCn2 RMSYNCn RSYNCn3 RCHCLKn RCHBLKn4 NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS MAPPED TO CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED TO ONE). NOTE 2: RSYNCn IN THE OUTPUT MODE (RIOCR.2 = 0).
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DS26518 8-Port T1/E1/J1 Transceiver Figure 11-21.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 11-22.
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DS26518 8-Port T1/E1/J1 Transceiver 11.4 E1 Transmitter Functional Timing Diagrams Figure 11-24. E1 Transmit-Side Timing FRAME# 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 TSYNCn1 TSSYNCIOn TSYNCn2 NOTE 1: TSYNCn IN FRAME MODE (TIOCR.0 = 0). NOTE 2: TSYNCn IN MULTIFRAME MODE (TIOCR.0 = 1). NOTE 3: THIS DIAGRAM ASSUMES BOTH THE CAS MF AND THE CRC-4 MF BEGIN WITH THE TAF FRAME. Figure 11-25.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 11-26. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) TSYSCLKn CHANNEL 23 CHANNEL 24 1 CHANNEL 1 LSB MSB TSERn LSB F MSB TSSYNCIOn TCHCLKn TCHBLKn2 NOTE 1: THE F-BIT POSITION IN THE TSERn DATA IS IGNORED. NOTE 2: TCHBLKn IS PROGRAMMED TO BLOCK CHANNEL 24. Figure 11-27. E1 Transmit-Side 2.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 11-28.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 11-29.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 11-30. E1 G.802 Timing TS# 31 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1718 19 20 21 22 23 24 25 2627 28 29 30 31 0 1 2 RSYNCn TSYNCn RCHCLKn TCHCLKn RCHBLKn TCHBLKn RCLKn/RSYSCLKn TCLKn/TSYSCLKn CHANNEL 25 RSERn/TSERn CHANNEL 26 LSB MSB RCHCLKn/TCHCLKn RCHBLKn/TCHBLKn NOTE: RCHBLKn OR TCHBLKn PROGRAMMED TO PULSE HIGH DURING TIME SLOTS 1 THROUGH 15, 17 THROUGH 25, AND BIT 1 OF TIME SLOT 26. Figure 11-31.
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DS26518 8-Port T1/E1/J1 Transceiver 12. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to VSS (except VDD)…………………………………………….-0.3V to +5.5V Supply Voltage (VDD) Range with Respect to VSS…………………………………………………………..-0.3V to +3.63V Operating Temperature Range…..………………………………………………………………...-40°C to +85°C (Note 1) Storage Temperature Range...………………………………………………………………………………-55°C to +125°C Soldering Temperature………………………………………………………….
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DS26518 8-Port T1/E1/J1 Transceiver 12.1 Thermal Characteristics Table 12-4. Thermal Characteristics PARAMETER CONDITIONS Ambient Temperature (Note 1) MIN TYP -40 Junction Temperature Theta-JA (θJA) in Still Air for 256-Pin TE-CSBGA (Note 2) MAX UNITS +85 °C +125 °C +17.5 °C/W Note 1: The package is mounted on a four-layer JEDEC standard test board.
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DS26518 8-Port T1/E1/J1 Transceiver 13. AC TIMING CHARACTERISTICS Unless otherwise noted, all timing numbers assume 20pF test load on output signals, 40pF test load on bus signals. 13.1 Microprocessor Bus AC Characteristics 13.1.1 SPI Bus Mode Table 13-1. SPI Bus Mode Timing (See Figure 13-1.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 13-1. SPI Interface Timing Diagram CSB INPUT t3 t2 t1 SPI_SCLK t4 t5 SPI_SCLK1 t8 MOSI INPUT SLAVE MSB t6 t7 t9 MISO OUTPUT SLAVE LSB BITS 6:1 MSB BIT 14 t10 BITS 13:0 NOTE 1: CLOCK EDGE REFERENCE TO DATA CONTROLLED BY CPHA AND CPOL SETTINGS. SEE THE FUNCTIONAL TIMING DIAGRAMS. NOTE 2: NOT DEFINED, BUT USUALLY MSB OF CHARACTER JUST RECEIVED.
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DS26518 8-Port T1/E1/J1 Transceiver Table 13-2. AC Characteristics—Microprocessor Bus Timing (VDD = 3.3V ±5%, TA = -40°C to +85°C.) (See Figure 13-2, Figure 13-3, Figure 13-4, and Figure 13-5.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 13-2. Intel Bus Read Timing (BTS = 0) t9 A[12:0] Address Valid Data Valid D[7:0] t5 WRB t1 CSB t2 t4 t3 RDB t10 Figure 13-3.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 13-4.
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DS26518 8-Port T1/E1/J1 Transceiver Table 13-3. Receiver AC Characteristics (VDD = 3.3V ±5%, TA = -40°C to +85°C.) (See Figure 13-6 and Figure 13-7.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 13-6. Receive Framer Timing—Backplane (T1 Mode) RCLKn t D1 F-BIT RSERn/RSIGn t D2 RCHCLKn t D2 RCHBLKn t D2 RFSYNCn/RMSYNCn t D2 RSYNCn1 NOTE 1: RSYNCn IS IN THE OUTPUT MODE. NOTE 2: NO RELATIONSHIP BETWEEN RCHCLKn AND RCHBLKn AND OTHER SIGNALS IS IMPLIED. Figure 13-7.
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DS26518 8-Port T1/E1/J1 Transceiver Table 13-4. Transmit AC Characteristics (VDD = 3.3V ±5%, TA = -40°C to +85°C.) (See Figure 13-8, Figure 13-9, and Figure 13-10.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 13-8. Transmit Formatter Timing—Backplane t CP t CL t CH TCLKn t D1 TESO t SU TSERn/TSIGn t HD t D2 TCHCLKn t D2 TCHBLKn t D2 TSYNCn1 t SU t HD TSYNCn2 NOTE 1: TSYNCn IS IN THE OUTPUT MODE. NOTE 2: TSYNCn IS IN THE INPUT MODE. NOTE 3: TSERn IS SAMPLED ON THE FALLING EDGE OF TCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED. NOTE 4: TCHCLKn AND TCHBLKn ARE SYNCHRONOUS WITH TCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 13-9. Transmit Formatter Timing—Elastic Store Enabled t SP t SL t SH TSYSCLKn t SU TSERn t D3 t HD TCHCLKn t D3 TCHBLKn t SU t HD TSSYNCIOn NOTE 1: TSERn IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSCLKn WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED. NOTE 2: TCHCLKn AND TCHBLKn ARE SYNCHRONOUS WITH TSYSCLKn WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED. Figure 13-10.
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DS26518 8-Port T1/E1/J1 Transceiver 13.2 JTAG Interface Timing Table 13-5. JTAG Interface Timing (VDD = 3.3V ±5%, TA = -40°C to +85°C.) (See Figure 13-11.
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DS26518 8-Port T1/E1/J1 Transceiver 14. JTAG BOUNDARY SCAN AND TEST ACCESS PORT The DS26518 IEEE 1149.1 design supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. See Table 14-1. The DS26518 contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
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DS26518 8-Port T1/E1/J1 Transceiver 14.1 TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 14-2. 14.1.1 Test-Logic-Reset Upon power-up, the TAP Controller will be in the Test-Logic-Reset state. The instruction register will contain the IDCODE instruction. All system logic of the device will operate normally. 14.1.
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DS26518 8-Port T1/E1/J1 Transceiver for the instruction register. JTMS HIGH during a rising edge on JTCLK puts the controller back into the Test-LogicReset state. 14.1.11 Capture-IR The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the controller enters the Exit1IR state. If JTMS is LOW on the rising edge of JTCLK, the controller enters the Shift-IR state.
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DS26518 8-Port T1/E1/J1 Transceiver Figure 14-2.
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DS26518 8-Port T1/E1/J1 Transceiver 14.2 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW shifts the data one stage towards the serial output at JTDO.
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DS26518 8-Port T1/E1/J1 Transceiver 14.3 JTAG ID Codes Table 14-2. ID Code Structure DEVICE REVISION ID[31:28] DEVICE CODE ID[27:12] MANUFACTURER’S CODE ID[11:1] REQUIRED ID[0] DS26519 DS26518 DS26514 Consult factory Consult factory Consult factory 0000000010001011 0000000010001010 0000000010001100 00010100001 00010100001 00010100001 1 1 1 14.4 Test Registers IEEE 1149.1 requires a minimum of two test registers: the Bypass Register and the Boundary Scan Register.
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DS26518 8-Port T1/E1/J1 Transceiver 15. PIN CONFIGURATION 15.
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DS26518 8-Port T1/E1/J1 Transceiver 16. PACKAGE INFORMATION For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. The DS26518 uses a 256-lead thermally enhanced chip scale ball grid array (TE-CSBGA) package. The package dimensions are shown in Maxim document 56-G6028-001.
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DS26518 8-Port T1/E1/J1 Transceiver 17. DOCUMENT REVISION HISTORY REVISION DATE 022007 060607 080607 103008 DESCRIPTION New Product Release. In the Absolute Maximum Ratings portion of Section 12, added Note 1 stating that specifications to -40°C are guaranteed by design (GBD) and not production tested. Updated data sheet to reflect new features with B1 die revision: HDLC-256 Controller—introduced in Section 9.10 and described in Section 9.10.3. Extended BERT Registers—introduced in Section 9.