DS26521 Single T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26521 is a single-channel framer and line interface unit (LIU) combination for T1, E1, and J1 applications. Each channel is independently configurable, supporting both long-haul and short-haul lines. Complete T1, E1, or J1 Long-Haul/Short-Haul Transceiver (LIU plus Framer) APPLICATIONS Crystal-Less Jitter Attenuator can be Selected for Transmit or Receive Path; Jitter Attenuator Meets ETS CTR 12/13, ITU-T G.736, G.
DS26521 Single T1/E1/J1 Transceiver TABLE OF CONTENTS 1. DETAILED DESCRIPTION ...............................................................................................9 1.1 2. MAJOR OPERATING MODES .............................................................................................................9 FEATURE HIGHLIGHTS ................................................................................................10 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 GENERAL ........................
DS26521 Single T1/E1/J1 Transceiver 8.9.8 8.9.9 8.9.10 8.9.11 8.9.12 8.9.13 8.9.14 8.9.15 8.9.16 8.9.17 8.10 HDLC CONTROLLERS ................................................................................................................62 8.10.1 8.10.2 8.11 Receive HDLC Controller..................................................................................................................... 62 Transmit HDLC Controller...............................................................................
DS26521 Single T1/E1/J1 Transceiver 13. JTAG BOUNDARY SCAN AND TEST ACCESS PORT ..............................................250 13.1 TAP CONTROLLER STATE MACHINE .........................................................................................251 13.1.1 13.1.2 13.1.3 13.1.4 13.1.5 13.1.6 13.1.7 13.1.8 13.1.9 13.1.10 13.1.11 13.1.12 13.1.13 13.1.14 13.1.15 13.1.16 13.2 Test-Logic-Reset............................................................................................................
DS26521 Single T1/E1/J1 Transceiver LIST OF FIGURES Figure 6-1. Block Diagram ......................................................................................................................................... 17 Figure 6-2. Detailed Block Diagram........................................................................................................................... 18 Figure 8-1. SPI Serial Port Access for Read Mode (SPI_CPOL = 0, SPI_CPHA = 0)..............................................
DS26521 Single T1/E1/J1 Transceiver Figure 12-7. Receive-Side Timing, Elastic Store Enabled (T1 Mode)..................................................................... 244 Figure 12-8. Receive Framer Timing—Line Side .................................................................................................... 244 Figure 12-9. Transmit Formatter Timing—Backplane ............................................................................................. 246 Figure 12-10.
DS26521 Single T1/E1/J1 Transceiver LIST OF TABLES Table 4-1. T1-Related Telecommunications Specifications ...................................................................................... 14 Table 4-2. E1-Related Telecommunications Specifications ...................................................................................... 15 Table 5-1. Time Slot Numbering Schemes................................................................................................................ 16 Table 7-1.
DS26521 Single T1/E1/J1 Transceiver Table 9-18. Receive Impedance Selection.............................................................................................................. 210 Table 9-19. Receiver Sensitivity Selection with Monitor Mode Disabled................................................................. 211 Table 9-20. Receiver Sensitivity Selection with Monitor Mode Enabled ................................................................. 211 Table 9-21. BERT Register Set ..............
DS26521 Single T1/E1/J1 Transceiver 1. DETAILED DESCRIPTION The DS26521 is a single-channel device that can be software configured for T1, E1, or J1 operation. The DS26521 is composed of a line interface unit (LIU), framer, HDLC controller, and a TDM backplane interface, and is controlled by either an 8-bit parallel port or a serial peripheral interface (SPI). Internal impedance matching is provided for both transmit and receive paths reducing external component count.
DS26521 Single T1/E1/J1 Transceiver 2. FEATURE HIGHLIGHTS 2.1 General Single-port member of the TEX-series transceiver family of devices Software compatible with the DS26522 dual, DS26524 quad, and DS26528 octal transceivers 64-pin LQFP package 3.3V supply with 5V tolerant inputs and outputs IEEE 1149.1 JTAG boundary scan Development support includes evaluation kit, driver source code, and reference designs 2.2 Line Interface Requires a single master clock (MCLK) for both E1 and T1 operation.
DS26521 Single T1/E1/J1 Transceiver Detailed alarm and status reporting with optional interrupt support Large path and line error counters − T1: BPV, CV, CRC-6, and framing bit errors − E1: BPV, CV, CRC-4, E-bit, and frame alignment errors − Timed or manual update modes DS1 Idle Code Generation on a per-channel basis in both transmit and receive paths − User defined − Digital Milliwatt ANSI T1.403-1999 support G.965 V5.
DS26521 Single T1/E1/J1 Transceiver 2.7 HDLC Controllers One HDLC controller engine for each T1/E1 port Independent 64-byte Rx and Tx buffers with interrupt support Access FDL, Sa, or single DS0 channel Compatible with polled or interrupt driven environments 2.8 Test and Diagnostics IEEE 1149.
DS26521 Single T1/E1/J1 Transceiver 3.
DS26521 Single T1/E1/J1 Transceiver 4. SPECIFICATIONS COMPLIANCE The DS26521 LIU meets all the latest relevant telecommunications specifications. Table 4-1 and Table 4-2 provide the T1 and E1 specifications and relevant sections that are applicable to the DS26521. Table 4-1. T1-Related Telecommunications Specifications ANSI T1.102: Digital Hierarchy Electrical Interface AMI Coding B8ZS Substitution Definition DS1 Electrical Interface. Line rate ±32ppm; Pulse Amplitude between 2.4V to 3.
DS26521 Single T1/E1/J1 Transceiver Table 4-2. E1-Related Telecommunications Specifications ITU-T G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces Defines the 2048kbps bit rate—2048 ±50ppm; the transmission media are 75Ω coax or 120Ω twisted pair; peak-topeak space voltage is ±0.237V; nominal pulse width is 244ns. Return loss 51Hz to 102Hz is 6dB, 102Hz to 3072Hz is 8dB, 2048Hz to 3072Hz is 14dB. Nominal peak voltage is 2.37V for coax and 3V for twisted pair.
DS26521 Single T1/E1/J1 Transceiver 5. ACRONYMS AND GLOSSARY This data sheet assumes a particular nomenclature of the T1 and E1 operating environment. In each 125μs T1 frame, there are 24 8-bit channels plus a framing bit. It is assumed that the framing bit is sent first followed by channel 1. For T1 and E1, each channel is made up of 8 bits, which are numbered 1 to 8. Bit 1, the MSB, is transmitted first. Bit 8, the LSB, is transmitted last.
DS26521 Single T1/E1/J1 Transceiver 6. BLOCK DIAGRAMS Figure 6-1.
DS26521 Single T1/E1/J1 Transceiver Figure 6-2.
DS26521 Single T1/E1/J1 Transceiver 7. PIN DESCRIPTIONS 7.1 Pin Functional Description Table 7-1. Detailed Pin Descriptions NAME PIN TYPE FUNCTION ANALOG TRANSMIT TTIP TRING TXENABLE 6 7 Analog Output, High Impedance Transmit Bipolar Tip. This pin is a differential line driver tip output. This pin can be high impedance if: If TXENABLE is low, the TTIP/TRING will be high impedance.
DS26521 Single T1/E1/J1 Transceiver NAME TSYNC TSSYNCIO PIN 61 60 TYPE FUNCTION I/O Transmit Synchronization. A pulse at this pin establishes either frame or multiframe boundaries for the transmit side. This signal can also be programmed to output either a frame or multiframe pulse. If this pin is set to output pulses at frame boundaries, it can also be set to output double-wide pulses at signaling frames in T1 mode. The operation of this signals is synchronous with TCLK.
DS26521 Single T1/E1/J1 Transceiver NAME PIN TYPE FUNCTION RECEIVE FRAMER RSER 57 O RCLK 56 O RSYSCLK 55 I RSYNC 54 I/O RMSYNC/ RFSYNC 53 O RSIG 52 O AL/ RSIGF/ FLOS 51 O RLF/ LTC 50 O Received Serial Data. Received NRZ serial data. Updated on rising edges of RCLK when the receive-side elastic store is disabled. Updated on the rising edges of RSYSCLK when the receive-side elastic store is enabled. When IBO mode is used, the RSER data is synchronous to to RSYSCLK.
DS26521 Single T1/E1/J1 Transceiver NAME RCHBLK/ CLK PIN 49 TYPE O FUNCTION Receive Channel Block/Receive Channel Block Clock. This pin can be configured to output either RCHBLK or RCHCLK. RCHBLK is a userprogrammable output that can be forced high or low during any of the 24 T1 or 32 E1 channels. It is synchronous with RCLK when the receive-side elastic store is disabled. It is synchronous with RSYSCLK when the receive-side elastic store is enabled.
DS26521 Single T1/E1/J1 Transceiver NAME PIN TYPE FUNCTION Data [2]/SPI Serial Interface Clock D[2]/ SPI_SCLK 31 I D[2]: Bit 2 of the 8-bit data bus used to input data during register writes, and data outputs during register reads. Not driven when CSB = 1. SPI_SCLK: SPI serial clock input when SPI_SEL = 1. Data [1]/SPI Serial Interface Data Master-Out/Slave-In D[1]/ SPI_MOSI 32 I D[1]: Bit 1 of the 8-bit data bus used to input data during register writes, and data outputs during register reads.
DS26521 Single T1/E1/J1 Transceiver NAME PIN TYPE FUNCTION TEST JTAG Reset. JTRST is used to asynchronously reset the test access port controller. After power-up, JTRST must be toggled from low to high. This action sets the device into the JTAG DEVICE ID mode. Pulling JTRST low restores normal device operation. JTRST is pulled high internally via a 10kΩ resistor operation. If boundary scan is not used, this pin should be held low. JTAG Mode Select.
DS26521 Single T1/E1/J1 Transceiver 8. 8.1 8.1.1 FUNCTIONAL DESCRIPTION Microprocessor Interface Parallel Port Mode Parallel port control of the DS26521 is accomplished through the 26 hardware pins of the microprocessor port. The 8-bit parallel data bus can be configured for Intel or Motorola modes of operation with the bus type select (BTS) pin. When the BTS pin is a logic 0, bus timing is in Intel mode, as shown in Figure 12-1 and Figure 12-2.
DS26521 Single T1/E1/J1 Transceiver user must configure the SPI_CPOL and SPI_CPHA pins to describe which type of clock that the master device is providing. Figure 8-1. SPI Serial Port Access for Read Mode (SPI_CPOL = 0, SPI_CPHA = 0) SPI_SCLK CSB SPI_MOSI 1 A13 A12 A11 A10 A9 A8 MSB A7 A6 LSB MSB A5 A4 A3 A2 A1 A0 B LSB SPI_MISO D7 D6 D5 D4 D3 D2 D1 MSB D0 LSB Figure 8-2.
DS26521 Single T1/E1/J1 Transceiver Figure 8-5. SPI Serial Port Access for Write Mode (SPI_CPOL = 0, SPI_CPHA = 0) SPI_SLCK CSB SPI_MOSI 0 A13 A12 A11 A10 A9 A8 MSB A7 LSB A6 A5 A4 A3 A2 A1 A0 MSB B D7 LSB MSB D6 D5 D4 D3 D2 D1 D0 LSB SPI_MISO Figure 8-6.
DS26521 Single T1/E1/J1 Transceiver 8.2 Clock Structure The user should provide a system clock to the MCLK input of 2.048MHz, 1.544MHz, or a multiple of up to 8x the T1 and E1 frequencies. To meet many specifications, the MCLK source should have ±50ppm accuracy. 8.2.1 Backplane Clock Generation The DS26521 provides facility for provision of BPCLK at 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz (see Figure 8-9).
DS26521 Single T1/E1/J1 Transceiver 8.3 Resets and Power-Down Modes A hardware reset is issued by forcing the RESETB pin to logic-low. The RESETB input pin resets all framers, LIUs, and BERTs. Note that not all registers are cleared to 00h on a reset condition. The register space must be reinitialized to appropriate values after a hardware or software reset has occurred. This includes writing reserved locations to 00h. The DS26521 has several features included to reduce power consumption.
DS26521 Single T1/E1/J1 Transceiver 8.4 Initialization and Configuration 8.4.1 Example Device Initialization Sequence STEP 1: Reset the device by pulling the RESETB pin low, applying power to the device, or by using the software reset bits outlined in Section 8.3. Clear all reset bits. Allow time for the reset recovery. STEP 2: Check the device ID in the Device Identification register (IDR). STEP 3: Write the GTCCR register to correctly configure the system clocks. If supplying a 1.
DS26521 Single T1/E1/J1 Transceiver Figure 8-10. Device Interrupt Information Flow Diagram RIM2 RIM3 RIM1 RLS2 RLS3 RLS1 DRAWING LEGEND: 0 1 INTERRUPT STATUS REGISTERS REGISTER NAME INTERRUPT MASK REGISTERS REGISTER NAME RIM4 RLS4 RIIR 2 RIM5 RLS5 3 INTERRUPT PIN GTCR1.
DS26521 Single T1/E1/J1 Transceiver 8.8 System Backplane Interface The DS26521 provides a versatile backplane interface that can be configured to the following: • Transmit and receive two-frame elastic stores • Mapping of T1 channels into a 2.
DS26521 Single T1/E1/J1 Transceiver 8.8.1.1 Elastic Stores Initialization There are two elastic store initializations that can be used to improve performance in certain applications: elastic store reset and elastic store align. Both of these involve the manipulation of the elastic store’s read and write pointers and are useful primarily in synchronous applications (RSYSCLK/TSYSCLK are locked to RCLK/TCLK, respectively). The elastic store reset is used to minimize the delay through the elastic store.
DS26521 Single T1/E1/J1 Transceiver 8.8.1.4 Receiving Mapped T1 Channels from a 2.048MHz Backplane Setting the TSCLKM bit (TIOCR.4) enables the transmit elastic store to operate with a 2.048MHz backplane (32 time slots/frame). In this mode the user can choose which of the backplane channels on TSER will be mapped into the T1 data stream by programming the Transmit Blank Channel Select registers (TBCS1:TBCS4).
DS26521 Single T1/E1/J1 Transceiver 8.8.1.7 Mapping E1 Channels onto a 1.544MHz Backplane The user can use the RSCLKM bit (RIOCR.4) to enable the receive elastic store to operate with a 1.544MHz backplane (24 channels / frame + F-bit). In this mode the user can choose which of the E1 time slots will be ignored (not transmitted onto RSER) by programming the Receive Blank Channel Select registers (RBCS1:RBCS4).
DS26521 Single T1/E1/J1 Transceiver 8.8.3 H.100 (CT Bus) Compatibility The registers used for controlling the H.100 backplane are RIOCR and TIOCR. The H.100 (or CT bus) is a synchronous, bit-serial, TDM transport bus operating at 8.192MHz. The H.100 standard also allows compatibility modes to operate at 2.048MHz, 4.096MHz, or 8.192MHz. The control bit H100EN (RIOCR.
DS26521 Single T1/E1/J1 Transceiver Figure 8-13. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode TSSYNCIO1 TSSYNCIO2 TSYSCLK TSER BIT 8 BIT 1 BIT 2 tBC3 NOTE 1: TSSYNCIO IN NORMAL OPERATION. NOTE 2: TSSYNCIO WITH H.100EN = 1 and TSSYNCINV = 1. NOTE 3: tBC (BIT CELL TIME) = 122ns (typ). tBC = 244ns OR 488ns ALSO ACCEPTABLE. 8.8.
DS26521 Single T1/E1/J1 Transceiver 8.9 Framers The DS26521 framer core is software selectable for T1, J1, or E1. The receive framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling data, T1 FDL data, and E1 Si- and Sa-bit information.
DS26521 Single T1/E1/J1 Transceiver Table 8-6. ESF Framing Mode FRAME NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 FRAMING FDL CRC SIGNALING √ CRC-1 √ 0 √ CRC-2 √ √ 0 √ CRC-3 √ √ √ CRC-4 √ 0 √ √ CRC-5 √ 1 √ CRC-6 √ √ 1 Table 8-7.
DS26521 Single T1/E1/J1 Transceiver FRAME NUMBER 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Ft Fs C1 (Concentrator Bit) SIGNALING D 1 C2 (Concentrator Bit) 0 C3 (Concentrator Bit) 1 C4 (Concentrator Bit) A 0 C5 (Concentrator Bit) 1 C6 (Concentrator Bit) 0 C7 (Concentrator Bit) B 1 C8 (Concentrator Bit) 0 C9 (Concentrator Bit) 1 C10 (Concentrator Bit) C 0 C11 (Concentrator Bit) 1 0 (Spoiler Bit)
DS26521 Single T1/E1/J1 Transceiver 8.9.2 E1 Framing The E1 framing consists of FAS, NFAS detection as shown in Table 8-8. Table 8-8.
DS26521 Single T1/E1/J1 Transceiver Table 8-9 shows registers that are related to setting up the framing. Table 8-9. Registers Related to Setting Up the Framer REGISTER FRAMER ADDRESSES FUNCTION Transmit Master Mode Register (TMMR) 180h T1/E1 mode. Transmit Control Register 1 (TCR1) 181h Source of the F-bit. Transmit Control Register 2 (TCR2) 182h F-bit corruption, selection of SLC-96. Transmit Control Register 3 (TCR3) 183h ESF or D4 mode selection.
DS26521 Single T1/E1/J1 Transceiver 8.9.3 T1 Transmit Synchronizer The DS26521 transmitter can identify the D4 or ESF frame boundary, as well as the CRC multiframe boundaries within the incoming NRZ data stream at TSER. The TFM (TCR3.2) control bit determines whether the transmit synchronizer searches for the D4 or ESF multiframe. Additional control signals for the transmit synchronizer are located in the TSYNCC register. The latched status bit TLS3.
DS26521 Single T1/E1/J1 Transceiver 8.9.4 Signaling The DS26521 supports both software- and hardware-based signaling. Interrupts can be generated on changes of signaling data. The DS26521 is also equipped with receive-signaling freeze on loss of synchronization (OOF), carrier loss, or change of frame alignment. The DS26521 also has hardware pins to indicate signaling freeze.
DS26521 Single T1/E1/J1 Transceiver 8.9.4.1 Transmit-Signaling Operation There are two methods to provide transmit-signaling data. These are processor based (i.e., software based) or hardware based. Processor based refers to access through the transmit-signaling registers, TS1:TS16, while hardware based refers to using the TSIG pins. Both methods can be used simultaneously. 8.9.4.1.
DS26521 Single T1/E1/J1 Transceiver 8.9.4.3 Receive-Signaling Operation There are two methods to access receive-signaling data and provide transmit-signaling data: processor based (i.e., software based) or hardware based. Processor based refers to access through the transmit- and receive-signaling registers, RS1:RS16. Hardware based refers to the RSIG pin. Both methods can be used simultaneously. 8.9.4.3.
DS26521 Single T1/E1/J1 Transceiver 8.9.4.3.6 Receive-Signaling Freeze The signaling data in the four multiframe signaling buffers is frozen in a known good state upon either a loss of synchronization (OOF event), carrier loss, or change of frame alignment. In T1 mode, this action meets the requirements of BellCore TR-TSY-000170 for signaling freezing. To allow this freeze action to occur, the RSFE control bit (RSIGC.1) should be set high. The user can force a freeze by setting the RSFF control bit (RSIGC.
DS26521 Single T1/E1/J1 Transceiver 8.9.4.5 Receive SLC-96 Operation (T1 Mode Only) In an SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of message fields. The SLC-96 multiframe is made up of six D4 superframes, thus it is 72 frames long. In the 72frame SLC-96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36 bits are divided into alarm, maintenance, spoiler, and concentrator bits, as well as 12 bits of the normal Fs pattern.
DS26521 Single T1/E1/J1 Transceiver 8.9.5.2 Receive Bit-Oriented Code (BOC) Controller The DS26521 framer contains a BOC generator on the transmit side and a BOC detector on the receive side. The BOC function is available only in T1, ESF mode in the data link bits. Table 8-14 shows the registers related to the receive BOC operation. Table 8-14. Registers Related to T1 Receive BOC REGISTER FRAMER ADDRESSES FUNCTION Receive BOC Control Register (T1RBOCC) 015h Controls the receive BOC function.
DS26521 Single T1/E1/J1 Transceiver The Transmit FDL register (T1TFDL) contains the facility data link (FDL) information that is to be inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first. In D4 mode, only the lower six bits are used. 8.9.5.4 Legacy T1 Receive FDL It is recommended that the DS26521’s built-in BOC or HDLC controllers be used for most applications requiring access to the FDL. Table 8-16 shows the registers related to the receive FDL. Table 8-16.
DS26521 Single T1/E1/J1 Transceiver 8.9.6.1 Additional E1 Receive Sa- and Si-Bit Receive Operation (E1 Mode) The DS26521, when operated in the E1 mode, provides for access to both the Sa and the Si bits via two methods. The first involves using the internal E1RAF/E1RNAF and E1TAF/E1TNAF registers. The second method involves an expanded version of the first method. 8.9.6.1.
DS26521 Single T1/E1/J1 Transceiver Table 8-18 shows some of the registers related to maintenance and alarms. Table 8-18. Registers Related to Maintenance and Alarms REGISTER FRAMER ADDRESSES Receive Real-Time Status Register 1 (RRTS1) 0B0h Real-time receive status 1. Receive Interrupt Mask Register 1(RIM1) 0A0h Real-time interrupt mask 1. Receive Latched Status Register 2 (RLS2) 091h Real-time latched status 2. Receive Real-Time Status Register 3 (RRTS3) 0B2h Real-time receive status 3.
DS26521 Single T1/E1/J1 Transceiver 8.9.7.1 Status and Information Bit Operation When a particular event has occurred (or is occurring), the appropriate bit in one of these registers is set to 1. Status bits can operate in either a latched or real-time fashion. Some latched bits can be enabled to generate a hardware interrupt via the INTB signal. 8.9.7.1.1 Real-Time Bits Some status bits operate in a real-time fashion. These bits are read-only and indicate the present state of an alarm or a condition.
DS26521 Single T1/E1/J1 Transceiver Table 8-19. T1 Alarm Criteria ALARM AIS (Blue Alarm) (See Note 1) 1) D4 Bit 2 Mode (T1RCR2.0 = 0) RAI (Yellow Alarm) 2) D4 12th F-Bit Mode (T1RCR2.0 = 1) (Note: This mode is also referred to as the “Japanese Yellow Alarm.”) 3) ESF Mode LOS (Loss of Signal) (Note: This alarm is also referred to as receive carrier loss (RCL).) SET CRITERIA CLEAR CRITERIA When over a 3ms window, 4 or fewer zeros are received.
DS26521 Single T1/E1/J1 Transceiver RAI-CI is a repetitive pattern within the ESF data link with a period of 1.08 seconds. It consists of sequentially interleaving 0.99 seconds of “00000000 11111111” (right-to-left ) with 90ms of “00111110 11111111.” The RRAI-CI bit is set when a bit-oriented code of “00111110 11111111” is detected while RRAI (RRTS1.3) is set. The RRAI-CI detector uses the receive BOC filter bits (RBF0 and RBF1) located in RBOCC to determine the integration time for RAI-CI detection.
DS26521 Single T1/E1/J1 Transceiver Table 8-21. E1 Line Code Violation Counting Options E1 CODE VIOLATION SELECT (ERCNT.0) WHAT IS COUNTED IN LCVCR1, LCVCR2 0 1 BPVs CVs 8.9.9.2 Path Code Violation Count Register (PCVCR) In T1 operation, the Path Code Violation Count register (PCVCR) records either Ft, Fs, or CRC-6 errors. When the receive side of a framer is set to operate in the T1 ESF framing mode, PCVCR records errors in the CRC-6 codewords.
DS26521 Single T1/E1/J1 Transceiver 8.9.9.4 E-Bit Counter (EBCR) This counter is only available in E1 mode. E-Bit Count Register 1 (E1EBCR1) is the most significant word and E-Bit Count Register 2 (E1EBCR2) is the least significant word of a 16-bit counter that records far-end block errors (FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running with CRC-4 multiframe. These count registers increment once each time the received E-bit is set to 0.
DS26521 Single T1/E1/J1 Transceiver 8.9.11 Transmit Per-Channel Idle Code Insertion Channel data can be replaced by an idle code on a per-channel basis in the transmit and receive directions. The Transmit Idle Code Definition registers (TIDR1:TIDR32) are provided to set the 8-bit idle code for each channel. The Transmit Channel Idle Code Enable registers (TCICE1:TCICE4) are used to enable idle code replacement on a per-channel basis. 8.9.
DS26521 Single T1/E1/J1 Transceiver 8.9.15 T1 Programmable In-Band Loop Code Generator The DS26521 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. Table 8-25. Registers Related to T1 In-Band Loop Code Generator REGISTER Transmit Code Definition Register 1 (T1TCD1) Transmit Code Definition Register 2 (T1TCD2) FRAMER ADDRESSES FUNCTION 1ACh Pattern to be sent for loop code. 1ADh Length of the pattern to be sent.
DS26521 Single T1/E1/J1 Transceiver 8.9.16 T1 Programmable In-Band Loop Code Detection The DS26521 can generate and detect a repeating bit pattern from one to eight bits or 16 bits in length. This function is available only in T1 mode. Table 8-26. Registers Related to T1 In-Band Loop Code Detection REGISTER FRAMER ADDRESSES FUNCTION Receive In-Band Code Control Register (T1RIBCC) 082h Used for selecting length of receive inband loop code register.
DS26521 Single T1/E1/J1 Transceiver 8.9.17 Framer Payload Loopbacks The framer, payload, and remote loopbacks are controlled by Receive Control Register 3 (RCR3). Table 8-27. Registers Related to Framer Payload Loopbacks FRAMER ADDRESSES FUNCTION Framer Loopback 083h Transmit data output from the framer is looped back to the receiver. Payload Loopback 083h The 192-bit payload data is looped back to the transmitter.
DS26521 Single T1/E1/J1 Transceiver 8.10 HDLC Controllers 8.10.1 Receive HDLC Controller The DS26521 has an enhanced HDLC controller that can be mapped into a single time slot, or Sa4 to Sa8 bits (E1 mode), or the FDL (T1 mode). The HDLC controller has a 64-byte FIFO buffer in both the transmit and receive paths. The user can select any specific bits within the time slot(s) to assign to the HDLC controller, as well as specific Sa bits (E1 mode).
DS26521 Single T1/E1/J1 Transceiver 8.10.1.1 HDLC FIFO Control Control of the transmit and receive FIFOs is accomplished via the Receive HDLC FIFO Control (RHFC) and Transmit HDLC FIFO Control (THFC) registers. The FIFO control registers set the watermarks for the FIFO. When the receive FIFO fills above the high watermark, the RHWM bit (RRTS5.1) is set. RHWM and THRM are real-time bits and remain set as long as the FIFO’s write pointer is above the watermark.
DS26521 Single T1/E1/J1 Transceiver Figure 8-15. Receive HDLC Example Configure Receive HDLC Controller (RHC, RHBSE, RHFC) Reset Receive HDLC Controller (RHC.6) Start New Message Buffer Enable Interrupts RPE and RHWM NO Interrupt? No Action Required Work Another Process. YES Read Register RHPBA Start New Message Buffer NO MS = 1? YES (MS = RHPBA[7]) Read N Bytes From Rx HDLC FIFO (RHF) N = RHPBA[5..0] Read N Bytes From Rx HDLC FIFO (RHF) N = RHPBA[5..0] Read RRTS5 for Packet Status (PS2..
DS26521 Single T1/E1/J1 Transceiver 8.10.2 Transmit HDLC Controller 8.10.2.1 FIFO Information The Transmit HDLC FIFO Buffer Available register (TFBA) indicates the number of bytes that can be written into the transmit FIFO. The count from this register informs the host as to how many bytes can be written into the transmit FIFO without overflowing the buffer. This is a real-time register. The count shall remain valid and stable during the read cycle. 8.10.2.
DS26521 Single T1/E1/J1 Transceiver Figure 8-16. HDLC Message Transmit Example Configure Transmit HDLC Controller (THC1,THC2,THBSE,THFC) Reset Transmit HDLC Controller (THC.5) Enable TLWM Interrupt and Verify TLWM Clear Set TEOM (THC1.2) Read TFBA N = TFBA[6..
DS26521 Single T1/E1/J1 Transceiver 8.11 Line Interface Units (LIUs) The DS26521 combines an LIU transmit and receive front-end with its framers. The LIU contains three sections: the transmitter, which waveshapes and drives the network line; the receiver, which handles clock and data recovery; and the jitter attenuator. The DS26521 LIU can switch between T1 or E1 networks without changing any external components on either the transmit or receive side.
DS26521 Single T1/E1/J1 Transceiver Figure 8-17. Basic Balanced Network Connections F1 TX TIP 3.3 V T1 T3 DVDD TTIP S3 0.01 uF S1 S7 S4 560 pF TRING TX RING 2:1 F2 Dallas Single Chip Transceiver or Line Interface Unit F3 RX TIP T2 RTIP T4 S5 68 uF 3.3 V TVDD 0.1 uF TVSS S2 S8 RVDD S6 RX RING 0.1 uF DVSS RRING 1:1 F4 60 0.1 uF RVSS 60 0.
DS26521 Single T1/E1/J1 Transceiver Table 8-29. Recommended Supply Decoupling SUPPLY PINS DECOUPLING CAPACITANCE DVDD/DVSS 0.1μF + 0.1μF + 1μF + 10μF DVDDIO/DVSSIO 0.1μF + 0.1μF + 1μF + 10μF ATVDD/ATVSS (0.1μF + 1μF + 10μF) x 4 ARVDD/ARVSS (0.1μF + 1μF + 10μF) x 4 ACVDD/ACVSS 0.1μF + 1μF + 10μF NOTES — — Place set of three capacitors on each side of the device. Place set of three capacitors on each side of the device. — 8.11.
DS26521 Single T1/E1/J1 Transceiver 8.11.2 Transmitter NRZ data arrives from the framer transmitter; the data is encoded with HDB3 or B8ZS or AMI. The encoded data passes through a jitter attenuator if it is enabled for the transmit path. A digital sequencer and DAC are used to generate transmit waveforms complaint with T1.102 and G.703 pulse templates. A line driver is used to drive an internal matched impedance circuit for provision of 75Ω, 100Ω, 110Ω, and 120Ω terminations.
DS26521 Single T1/E1/J1 Transceiver 8.11.2.1 Transmit-Line Pulse Shapes The DS26521 transmitters can be selected individually to meet the pulse templates for E1 and T1/J1 modes. The T1/J1 pulse template is shown in Figure 8-18. The E1 pulse template is shown in Figure 8-19. The transmit pulse shape can be configured for each LIU on an individual basis.
DS26521 Single T1/E1/J1 Transceiver Figure 8-19. E1 Transmit Pulse Templates 1.2 1.1 269ns SCALED AMPLITUDE (in 75 ohm systems, 1.0 on the scale = 2.37Vpeak in 120 ohm systems, 1.0 on the scale = 3.00Vpeak) 1.0 0.9 0.8 0.7 G.703 Template 194ns 0.6 0.5 219ns 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -250 -200 -150 -100 -50 0 50 100 150 200 250 TIME (ns) 8.11.2.
DS26521 Single T1/E1/J1 Transceiver 8.11.3 Receiver The DS26521 contains identical receivers. Both receivers are designed to be fully software-selectable for E1, T1, and J1 without the need to change any external resistors. The device couples to the receive E1 or T1 twisted pair (or coaxial cable in 75Ω E1 applications) via a 1:1 or 2:1 transformer. See Table 8-32 for transformer details. Receive termination and sensitivity are user configurable.
DS26521 Single T1/E1/J1 Transceiver Figure 8-20. Typical Monitor Application PRIMARY T1/E1 TERMINATING DEVICE T1/E1 LINE Rm Rm X F M R MONITOR PORT JACK Rt DS26521 SECONDARY T1/E1 TERMINATING DEVICE 8.11.3.4 Loss of Signal (LOS) The DS26521 uses both the digital and analog loss-detection method in compliance with the latest ANSI T1.231 for T1/J1 and ITU-T G.775, or ETS 300 233 for E1 mode of operation.
DS26521 Single T1/E1/J1 Transceiver 8.11.3.5 ANSI T1.231 for T1 and J1 Modes For short-haul mode, loss is declared if the received signal level is 3dB lower from the programmed value (based on Table 9-19) for a duration of 192-bit periods. Hence, if the sensitivity is programmed to be 12dB, loss will be declared at 15dB. LOS is reset if the following criteria are met: 1) 24 or more ones are detected in 192-bit period with a programmed sensitivity level measured at RTIP and RRING.
DS26521 Single T1/E1/J1 Transceiver 8.11.4 Jitter Attenuator The DS26521 contains a jitter attenuator for each LIU that can be set to a depth of 32 or 128 bits via the JADS (LTRCR.4) bit in the LIU Transmit Receive Control register (LTRCR). The 128-bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delay-sensitive applications. The characteristics of the attenuation are shown in Figure 8-21.
DS26521 Single T1/E1/J1 Transceiver 8.11.5 LIU Loopbacks The DS26521 provides four LIU loopbacks for diagnostic purposes: analog loopback, local loopback, remote loopback, and dual loopback. In the loopback diagrams that follow, TSER, TCLK, RSER, and RCLK are inputs/outputs from the framer. 8.11.5.1 Analog Loopback The analog output of the transmitter TTIP and TRING is looped back to RTIP and RRING of the receiver. Data at RTIP and RRING is ignored in analog loopback. This is shown in Figure 8-22.
DS26521 Single T1/E1/J1 Transceiver 8.11.5.3 Remote Loopback The outputs decoded from the receive LIU are looped back to the transmit LIU. The inputs from the transmit framer are ignored during a remote loopback. This loopback is conceptually shown in Figure 8-24. Figure 8-24. Remote Loopback TCLK TSER TRANSMIT TRANSMIT FRAMER FRAMER OPTIONAL JITTER OPTIONAL ATTENUATOR JITTER ATTENUATOR RCLK RCLK RSER RSER 8.11.5.
DS26521 Single T1/E1/J1 Transceiver 8.12 Bit-Error-Rate Test (BERT) Function The bit-error-rate tester (BERT) block can generate and detect both pseudorandom and repeating bit patterns. It is used to test and stress data-communication links. BERT functionality is dedicated for each of the transceivers. Table 8-35 shows the registers related to the configure, control, and status of the BERT. Table 8-35.
DS26521 Single T1/E1/J1 Transceiver The BERT block can generate and detect the following patterns: • The pseudorandom patterns 2E7-1, 2E9-1, 2E11-1, 2E15-1, and QRSS • A repetitive pattern from 1 to 32 bits in length • Alternating (16-bit) words that flip every 1 to 256 words • Daly pattern The BERT function must be enabled and configured in the TXPC and RXPC registers for each port.
DS26521 Single T1/E1/J1 Transceiver 9. DEVICE REGISTERS Thirteen address bits are used to control the settings of the registers. The address map is compatible with the Dallas Semiconductor dual framer product, DS26522. The registers control functions of the framers, LIU, and BERT within the DS26521. Global registers (applicable to the transceiver and BERT) are located within the address space of the framer. The register details are provided in the following tables.
DS26521 Single T1/E1/J1 Transceiver 9.1.1 Global Register List Table 9-2.
DS26521 Single T1/E1/J1 Transceiver 9.1.2 Framer Register List Table 9-3.
DS26521 Single T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS NAME 041h 042h 043h 044h 045h 046h 047h 048h 049h 04Ah 04Bh 04Ch 04Dh 04Eh 04Fh 050h 051h 052h 053h 054h 055h 056h 057h 058h–05Fh 060 061 RS2 RS3 RS4 RS5 RS6 RS7 RS8 RS9 RS10 RS11 RS12 RS13 RS14 RS15 RS16 LCVCR1 LCVCR2 PCVCR1 PCVCR2 FOSCR1 FOSCR2 E1EBCR1 E1EBCR2 — RDS0M — T1RFDL E1RRTS7 T1RBOC T1RSLC1 E1RAF T1RSLC2 E1RNAF T1RSLC3 E1RSiAF E1RSiNAF E1RRA E1RSa4 E1RSa5 E1RSa6 E1RSa7 E1RSa8 SaBITS Sa6CODE — RMMR RCR1 RCR1 T1RIBCC E1RCR2 RCR3 RI
DS26521 Single T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS NAME DESCRIPTION R/W 085h 086h 087h 088h 089h 08Ah 08B 08Ch–08Fh 090h 091h 092h 093 094h 095h RESCR ERCNT RHFC RIBOC T1RSCC RXPC RBPBS — RLS1 RLS2 RLS3 RLS4 RLS5 — RLS7 RLS7 — RSS1 RSS2 RSS3 RSS4 T1RSCD1 T1RSCD2 — RIIR RIM1 RIM2 RIM3 RIM3 RIM4 RIM5 — RIM7 — RSCSE1 RSCSE2 RSCSE3 RSCSE4 T1RUPCD1 T1RUPCD2 T1RDNCD1 T1RDNCD2 RRTS1 — RRTS3 RRTS3 — RRTS5 RHPBA RHF — RBCS1 Receive Elastic Store Control Register Error-Counter Configuration Regist
DS26521 Single T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS NAME 0C1h 0C2h 0C3h 0C4h 0C5h 0C6h 0C7h 0C8h 0C9h 0CAh 0CBh 0CCh 0CDh 0CEh 0CFh 0D0h 0D1h 0D2h 0D3h 0D4h 0D5h 0D6h 0D7h 0D8h–0EFh RBCS2 RBCS3 RBCS4 RCBR1 RCBR2 RCBR3 RCBR4 RSI1 RSI2 RSI3 RSI4 RGCCS1 RGCCS2 RGCCS3 RGCCS4 RCICE1 RCICE2 RCICE3 RCICE4 RBPCS1 RBPCS2 RBPCS3 RBPCS4 — Global Registers (Section 9.
DS26521 Single T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS NAME 12Dh 12Eh 12Fh 130h 131h 132h 133h 134h 135h 136h 137h 138h 139h 13Ah 13Bh 13Ch 13Dh 13Eh 13Fh 140h 141h 142h 143h 144h 145h 146h 147h 148h 149h 14Ah 14Bh 14Ch 14Dh 14Eh 14Fh 150h 151h 152h 153h 154h–161h 162h 163h TIDR14 TIDR15 TIDR16 TIDR17 TIDR18 TIDR19 TIDR20 TIDR21 TIDR22 TIDR23 TIDR24 TIDR25 TIDR26 TIDR27 TIDR28 TIDR29 TIDR30 TIDR31 TIDR32 TS1 TS2 TS3 TS4 TS5 TS6 TS7 TS8 TS9 TS10 TS11 TS12 TS13 TS14 TS15 TS16 TCICE1 TCICE2 TCICE3
DS26521 Single T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS NAME 16Bh 16Ch 16Dh 16Eh–17Fh 180h E1TSa6 E1TSa7 E1RSa8 — TMMR TCR1 TCR1 TCR2 TCR2 TCR3 TIOCR TESCR TCR4 THFC TIBOC TDS0SEL TXPC TBPBS — TSYNCC — TLS1 TLS2 TLS3 — TIIR TIM1 TIM2 TIM3 — T1TCD1 T1TCD2 — TRTS2 — TFBA THF — TDS0M — TBCS1 TBCS2 TBCS3 TBCS4 TCBR1 TCBR2 TCBR3 TCBR4 THSCS1 THSCS2 THSCS3 THSCS4 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch–18Dh 18Eh 18F 190h 191h 192h 193h–19Eh 19Fh 1A0h 1A1h 1A2h 1A3h–1ABh 1ACh 1ADh
DS26521 Single T1/E1/J1 Transceiver FRAMER REGISTER LIST ADDRESS NAME 1CCh 1CDh 1CEh 1CFh 1D0h 1D1h 1D2h 1D3h 1D4h 1D5h 1D6h 1D7h 1D8h–1FFh TGCCS1 TGCCS2 TGCCS3 TGCCS4 PCL1 PCL2 PCL3 PCL4 TBPCS1 TBPCS2 TBPCS3 TBPCS4 — DESCRIPTION Only) Transmit Gapped-Clock Channel Select Register 1 Transmit Gapped-Clock Channel Select Register 2 Transmit Gapped-Clock Channel Select Register 3 Transmit Gapped-Clock Channel Select Register 4 (E1 Mode Only) Per-Channel Loopback Enable Register 1 Per-Channel Loopback Enabl
DS26521 Single T1/E1/J1 Transceiver 9.1.3 LIU and BERT Register List Table 9-4.
DS26521 Single T1/E1/J1 Transceiver 9.2 Register Bit Maps 9.2.1 Global Register Bit Map Table 9-6.
DS26521 Single T1/E1/J1 Transceiver 9.2.2 Framer Register Bit Map Table 9-7 contains the framer registers of the DS26521. Some registers have dual functionality based on the selection of T1/J1 or E1 operating mode in the RMMR and TMMR registers. These dual-function registers are shown below using two lines of text. The first line of text is the bit functionality for T1/J1 mode. The second line is the bit functionality in E1 mode, in italics.
DS26521 Single T1/E1/J1 Transceiver ADDR NAME 03Bh RIDR28 03Fh T1RDMWE1 RIDR29 T1RDMWE2 RIDR30 T1RDMWE3 RIDR31 RIDR32 040h RS1 041h RS2 042h RS3 043h RS4 044h RS5 045h RS6 046h RS7 047h RS8 048h RS9 049h RS10 04Ah RS11 04Bh RS12 03Ch 03Dh 03Eh 04Ch 04Dh RS13 RS14 04Eh RS15 04Fh RS16 050h 051h 052h 053h 054h 055h LCVCR1 LCVCR2 PCVCR1 PCVCR2 FOSCR1 FOSCR2 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 — — — — — — — — C7 C6 C5 C4 C3 C2 C1 C0 CH8 C
DS26521 Single T1/E1/J1 Transceiver ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 056h 057h 060h 061h E1EBCR1 E1EBCR2 RDS0M — EB15 EB7 B1 — EB14 EB6 B2 — EB13 EB5 B3 — EB12 EB4 B4 — EB11 EB3 B5 — EB10 EB2 B6 — EB9 EB1 B7 — EB8 EB0 B8 — T1RFDL RFDL7 RFDL6 RFDL5 RFDL4 RFDL3 RFDL2 RFDL1 RFDL0 E1RRTS7 CSC5 CSC4 CSC3 CSC2 CSC0 CRC4SA CASSA FASSA — C8 Si M2 Si S=1 SiF14 SiF15 RRAF15 RSa4F15 RSa5F15 RSa6F15 RSa7F15 RSa8F15 — — FRM_EN SYNCT — — RSa8S — — C7 0 M1 1
DS26521 Single T1/E1/J1 Transceiver ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 097h 098h 099h 09Ah — RSS1 RSS2 RSS3 09Bh RSS4 09Ch T1RSCD1 09Dh T1RSCD2 09Fh 0A0h RIIR RIM1 0A1h RIM2 — CH8 CH16 CH24 — CH32 C7 — C7 — — RRAIC — — LORCC LORCC RESF — — — CH7 CH15 CH23 — CH31 C6 — C6 — RLS7 RAISC — — LSPC — RESEM — — CH8 CH16 CH24 CH7 CH15 CH23 — CH6 CH14 CH22 — CH30 C5 — C5 — RLS6* RLOSC — — LDNC V52LNKC RSLIP ROVR RRAI-CI — CH6 CH14 CH22 — CH5 CH13 CH21 — CH29 C4 — C4 —
DS26521 Single T1/E1/J1 Transceiver ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0C9h 0CAh RSI2 RSI3 0CBh RSI4 0CCh 0CDh 0CEh RGCCS1 RGCCS2 RGCCS3 0CFh RGCCS4 0D0h 0D1h 0D2h RCICE1 RCICE2 RCICE3 CH16 CH24 — CH32 CH8 CH16 CH24 — CH32 CH8 CH16 CH24 — CH15 CH23 — CH31 CH7 CH15 CH23 — CH31 CH7 CH15 CH23 — CH14 CH22 — CH30 CH6 CH14 CH22 — CH30 CH6 CH14 CH22 — CH13 CH21 — CH29 CH5 CH13 CH21 — CH29 CH5 CH13 CH21 — CH12 CH200 — CH28 CH4 CH12 CH20 — CH28 CH4 CH12 CH20 — CH11 CH1
DS26521 Single T1/E1/J1 Transceiver ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 135h 136h 137h TIDR22 TIDR23 TIDR24 C7 C7 C7 C6 C6 C6 C5 C5 C5 C4 C4 C4 C3 C3 C3 C2 C2 C2 C1 C1 C1 C0 C0 C0 138h TIDR25 139h TIDR26 13Ah TIDR27 13Bh TIDR28 13Ch TIDR29 13Dh TIDR30 13Eh TIDR31 13Fh TIDR32 140h TS1 141h TS2 142h TS3 143h TS4 144h TS5 145h TS6 146h TS7 147h TS8 148h TS9 149h TS10 14Ah TS11 14Bh TS12 14Ch TS13 14Dh TS14 — — — — — — —
DS26521 Single T1/E1/J1 Transceiver ADDR NAME 14Eh TS15 14Fh TS16 150h 151h 152h TCICE1 TCICE2 TCICE3 153h TCICE4 162h T1TFDL 163h T1TBOC 164h 165h 166h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 — — — — — — — — CH14-A — CH15-A CH8 CH16 CH24 — CH32 TFDL7 — — CH14-B — CH15-B CH7 CH15 CH23 — CH31 TFDL6 — — CH14-C — CH15-C CH6 CH14 CH22 — CH30 TFDL5 — TBOC5 CH14-D — CH15-D CH5 CH13 CH21 — CH29 TFDL4 — TBOC4 CH29-A — CH30-A CH4 CH12 CH20 — CH28 TFDL3 — TBOC3 CH29-B — CH3
DS26521 Single T1/E1/J1 Transceiver ADDR NAME 18Ah 18Bh TXPC TBPBS 18Eh TSYNCC 190h TLS1 191h TLS2 192h 19Fh TLS3 TIIR 1A0h TIM1 1A1h TIM2 1A2h TIM3 1ACh T1TCD1 ADh T1TCD2 1B1h 1B3h 1B4h 1BBh 1C0h 1C1h 1C2h TRTS2 TFBA THF TDS0M TBCS1 TBCS2 TBCS3 1C3h TBCS4 1C4h 1C5h 1C6h TCBR1 TCBR2 TCBR3 1C7h TCBR4 1C8h 1C9h 1CAh THSCS1 THSCS2 THSCS3 1CBh THSCS4 1CCh 1CDh 1CEh TGCCS1 TGCCS2 TGCCS3 1CFh TGCCS4 1D0h 1D1h 1D2h PCL1 PCL2 PCL3 1D3h PCL4 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3
DS26521 Single T1/E1/J1 Transceiver ADDR NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 1D4h 1D5h 1D6h TBPCS1 TBPCS2 TBPCS3 CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 CH1 CH9 CH17 1D7h TBPCS4 — — — — — — — — CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 *RLS6 is reserved for future use. **Currently, RLS2 does not create an interrupt, therefore this bit is not used in T1 mode. 9.2.3 LIU Register Bit Map Table 9-8.
DS26521 Single T1/E1/J1 Transceiver 9.3 Global Register Definitions Functions contained in the global registers include: framer reset, LIU reset, device ID, BERT interrupt status, framer interrupt status, IBO configuration, MCLK configuration, and BPCLK configuration. The global registers bit descriptions are presented in this section. Table 9-10.
DS26521 Single T1/E1/J1 Transceiver Register Name Register Description: Register Address: Bit # Name Default 7 — 0 GTCR1 Global Transceiver Control Register 1 0F0h 6 — 0 5 RLOFLTS 0 4 GIBOE 0 3 — 0 2 — 0 1 GCLE 0 0 GIPI 0 Bit 5: Receive Loss of Frame/Loss of Transmit Clock Indication Select (RLOFLTS). 0 = RLOF/LTC pin indicates framer receive loss of frame 1 = RLOF/LTC pin indicates framer loss of transmit clock Bit 4: Global IBO Enable (GIBOE).
DS26521 Single T1/E1/J1 Transceiver Register Name: Description: Register Address: Bit # Name Default GFCR Global Framer Control Register 0F1h 7 — 0 6 — 0 5 BPCLK1 0 4 BPCLK0 0 3 RFLOSSFS 0 2 RFMSS 0 1 TCBCS 0 0 RCBCS 0 Bits 5 and 4: Backplane Clock Select 1 and 0 (BPCLK[1:0]). These bits determine the clock frequency output on the BPCLK pin. BPCLK1 0 0 1 1 BPCLK0 0 1 0 1 BPCLK FREQUENCY 2.048MHz 4.096MHz 8.192MHz 16.384MHz Bit 3: Receive Loss of Signal/Signaling Freeze Select (RLOSSFS).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Read/Write Function GTCCR Global Transceiver Clock Control Register 0F3h R/W Bit # Name Default 7 6 5 4 3 2 1 0 BPREFSEL3 BPREFSEL2 BPREFSEL1 BPREFSEL0 BFREQSEL FREQSEL MPS1 MPS0 0 0 0 0 0 0 0 0 Bits 7 to 4: Backplane Clock Reference Selects (BPREFSEL[3:0]).These bits select which reference clock source will be used for BPCLK generation.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 GLSRR Global LIU Software Reset Register 0F5h 6 — 0 5 — 0 4 — 0 3 — 0 2 — 0 1 — 0 0 LSRST1 0 Bit 0: LIU Software Reset (LSRST1). LIU logic and registers are reset with a 0-to-1 transition in this bit. The reset is released when a zero is written to this bit.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 ID7 0 IDR Device Identification Register 0F8h 6 ID6 1 5 ID5 1 4 ID4 1 3 ID3 0 2 ID2 0 1 ID1 0 0 ID0 0 Bits 7 to 3: Device ID (ID[7:3]). The upper five bits of the IDR are used to display the DS26521 ID. Table 9-13.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 GFISR Global Framer Interrupt Status Register 0F9h 6 — 0 5 — 0 4 — 0 3 — 0 2 — 0 1 — 0 0 FIS1 0 The GFISR register reports the framer interrupt status for the T1/E1 framer. A logic one indicates the framer has set its interrupt signal. Bit 0: Framer Interrupt Status 1 (FIS1). 0 = Framer 1 has not issued an interrupt. 1 = Framer 1 has issued an interrupt.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 GFIMR Global Framer Interrupt Mask Register 0FCh 6 — 0 5 — 0 4 — 0 3 — 0 2 — 0 1 — 0 0 FIM1 0 3 — 0 2 — 0 1 — 0 0 BIM1 0 3 — 0 2 — 0 1 — 0 0 LIM1 0 Bit 0: Framer 1 Interrupt Mask (FIM1). 0 = Interrupt masked. 1 = Interrupt enabled.
DS26521 Single T1/E1/J1 Transceiver 9.4 Framer Register Definitions See Table 9-3 for the complete framer register list. 9.4.1 Receive Register Definitions Register Name: Register Description: Register Address: Bit # Name Default 7 RCRCD 0 RHC Receive HDLC Control Register 010h 6 RHR 0 5 RHMS 0 4 RHCS4 0 3 RHCS3 0 2 RHCS2 0 1 RHCS1 0 0 RHCS0 0 Bit 7: Receive CRC-16 Display (RCRCD).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 BSE8 0 RHBSE Receive HDLC Bit Suppress Register 011h 6 BSE7 0 5 BSE6 0 4 BSE5 0 3 BSE4 0 2 BSE3 0 1 BSE2 0 0 BSE1 0 Bit 7: Receive Channel Bit 8 Suppress (BSE8). MSB of the channel. Set to one to stop this bit from being used. Bit 6: Receive Channel Bit 7 Suppress (BSE7). Set to one to stop this bit from being used. Bit 5: Receive Channel Bit 6 Suppress (BSE6).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RDS0SEL Receive Channel Monitor Select Register 012h 6 — 0 5 — 0 4 RCM4 0 3 RCM3 0 2 RCM2 0 1 RCM1 0 0 RCM0 0 Bits 4 to 0: Receive Channel Monitor Bits (RCM[4:0]). RCM0 is the LSB of a 5-bit channel select that determines which receive DS0 channel data will appear in the RDS0M register.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 T1RCR2 (T1 Mode) Receive Control Register 2 014h 6 — 0 5 — 0 4 RSLC96 0 3 OOF2 0 2 OOF1 0 1 RAIIE 0 0 RD4RM 0 Bit 4: Receive SLC-96 Synchronizer Enable (RSLC96). See Section 8.9.4.5 for SLC-96 details. 0 = SLC-96 synchronizer is disabled 1 = SLC-96 synchronizer is enabled Bits 3 and 2: Out of Frame Select Bits (OOF[2:1]).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 E1RSAIMR (E1 Mode Only) Receive Sa-Bit Interrupt Mask Register 014h 6 — 0 5 — 0 4 RSa4IM 0 3 RSa5IM 0 2 RSa6IM 0 1 RSa7IM 0 0 RSa8IM 0 Bit 4: Sa4 Change Detect Interrupt Mask (RSa4IM). This bit will enable the change detect interrupt for the Sa4 bits. Any change of state of the Sa4 bit will then generate an interrupt in RLS7.0 to indicate the change of state. 0 = Interrupt masked.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RBR 0 T1RBOCC (T1 Mode Only) Receive BOC Control Register 015h 6 — 0 5 RBD1 0 4 RBD0 0 3 — 0 2 RBF1 0 1 RBF0 0 0 — 0 Bit 7: Receive BOC Reset (RBR). The host should set this bit to force a reset of the BOC circuitry. Note that this is an acknowledged reset, that is, the host need only set the bit and the DS26521 will clear it once the reset operation is complete (less than 250μs).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default (MSB) 7 CH8 CH16 CH24 0 T1RSAOI1, T1RSAOI2, T1RSAOI3 (T1 Mode Only) Receive-Signaling All-Ones Insertion Registers 1 to 3 038h, 039h, 03Ah 6 CH7 CH15 CH23 0 5 CH6 CH14 CH22 0 4 CH5 CH13 CH21 0 3 CH4 CH12 CH20 0 2 CH3 CH11 CH19 0 1 CH2 CH10 CH18 0 0 (LSB) CH1 CH9 CH17 0 T1RSAOI1 T1RSAOI2 T1RSAOI3 Setting any of the CH[1:24] bits in the T1RSAOI1:T1RSAOI3 registers will cause signaling dat
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RS1 to RS16 Receive-Signaling Registers 1 to 16 040h to 04Fh T1 Mode: (MSB) CH1-A CH2-A CH3-A CH4-A CH5-A CH6-A CH7-A CH8-A CH9-A CH10-A CH11-A CH12-A CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH11-D CH12-D CH13-A CH14-A CH15-A CH16-A CH17-A CH1
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: LCVCR1 Line Code Violation Count Register 1 050h Bit # Name Default 6 LCVC14 0 7 LCVC15 0 5 LCVC13 0 4 LCVC12 0 3 LCVC11 0 2 LCVC10 0 1 LCVC9 0 0 LCVC8 0 Bits 7 to 0: Line Code Violation Counter Bits 15 to 8 (LCVC[15:8]). LCVC15 is the MSB of the 16-bit code violation count.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: FOSCR1 Frames Out of Sync Count Register 1 054h Bit # Name Default 6 FOS14 0 7 FOS15 0 5 FOS13 0 4 FOS12 0 3 FOS11 0 2 FOS10 0 1 FOS9 0 0 FOS8 0 Bits 7 to 0: Frames Out of Sync Counter Bits 15 to 8 (FOS[15:8]). FOS15 is the MSB of the 16-bit frames out of sync count.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 B1 0 RDS0M Receive DS0 Monitor Register 060h 6 B2 0 5 B3 0 4 B4 0 3 B5 0 2 B6 0 1 B7 0 0 B8 0 Bits 7 to 0: Receive DS0 Channel Bits (B[1:8]). Receive channel data that has been selected by the Receive Channel Monitor Select register (RDS0SEL). B8 is the LSB of the DS0 channel (last bit to be received).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RFDL7 0 T1RFDL (T1 Mode) Receive FDL Register 062h 6 RFDL6 0 5 RFDL5 0 4 RFDL4 0 3 RFDL3 0 2 RFDL2 0 1 RFDL1 0 0 RFDL0 0 2 CRC4SA 0 1 CASSA 0 0 FASSA 0 Note: This register has an alternate definition for E1 mode. See E1RRTS7. Bit 7: Receive FDL Bit 7 (RFDL7). MSB of the received FDL code. Bit 6: Receive FDL Bit 6 (RFDL6). Bit 5: Receive FDL Bit 5 (RFDL5).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default T1RBOC (T1 Mode) Receive BOC Register 063h 7 — 0 6 — 0 5 RBOC5 0 4 RBOC4 0 3 RBOC3 0 2 RBOC2 0 1 RBOC1 0 0 RBOC0 0 Bit 5: BOC Bit 5 (RBOC5). Bit 4: BOC Bit 4 (RBOC4). Bit 3: BOC Bit 3 (RBOC3). Bit 2: BOC Bit 2 (RBOC2). Bit 1: BOC Bit 1 (RBOC1). Bit 0: BOC Bit 0 (RBOC0). The T1RBOC register always contains the last valid BOC received.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default (MSB) 7 C8 M2 S=1 0 T1RSLC1, T1RSLC2, T1RSLC3 (T1 Mode) Receive SLC-96 Data Link Registers 1 to 3 064h, 065h, 066h 6 C7 M1 S4 0 5 C6 S=0 S3 0 4 C5 S=1 S2 0 3 C4 S=0 S1 0 2 C3 C11 A2 0 1 C2 C10 A1 0 0 (LSB) C1 C9 M3 0 T1RSLC1 T1RSLC2 T1RSLC3 Note: These registers have an alternate definition for E1 mode. See E1RAF, E1RNAF, and E1RSiAF.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default E1RNAF (E1 Mode) E1 Receive Non-Align Frame Register 065h 7 Si 0 6 1 0 5 A 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 2 SiF4 0 1 SiF2 0 0 SiF0 0 Note: This register has an alternate definition for T1 mode. See T1RSLC2. Bit 7: International Bit (Si). Bit 6: Frame Non-Alignment Signal Bit (1). Bit 5: Remote Alarm (A). Bit 4: Additional Bit 4 (Sa4). Bit 3: Additional Bit 5 (Sa5).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 SiF15 0 E1RSiNAF (E1 Mode Only) Receive Si Bits of the Non-Align Frame Register 067h 6 SiF13 0 5 SiF11 0 4 SiF9 0 3 SiF7 0 2 SiF5 0 1 SiF3 0 0 SiF1 0 3 RRAF7 0 2 RRAF5 0 1 RRAF3 0 0 RRAF1 0 Bit 7: Si Bit of Frame 15 (SiF15). Bit 6: Si Bit of Frame 13 (SiF13). Bit 5: Si Bit of Frame 11 (SiF11). Bit 4: Si Bit of Frame 9 (SiF9). Bit 3: Si Bit of Frame 7 (SiF7).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RSa4F15 0 E1RSa4 (E1 Mode Only) Receive Sa4 Bits Register 069h 6 RSa4F13 0 5 RSa4F11 0 4 RSa4F9 0 3 RSa4F7 0 2 RSa4F5 0 1 RSa4F3 0 0 RSa4F1 0 3 RSa5F7 0 2 RSa5F5 0 1 RSa5F3 0 0 RSa5F1 0 Bit 7: Sa4 Bit of Frame 15 (RSa4F15). Bit 6: Sa4 Bit of Frame 13 (RSa4F13). Bit 5: Sa4 Bit of Frame 11 (RSa4F11). Bit 4: Sa4 Bit of Frame 9 (RSa4F9). Bit 3: Sa4 Bit of Frame 7 (RSa4F7).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RSa6F15 0 E1RSa6 (E1 Mode Only) Receive Sa6 Bits Register 06Bh 6 RSa6F13 0 5 RSa6F11 0 4 RSa6F9 0 3 RSa6F7 0 2 RSa6F5 0 1 RSa6F3 0 0 RSa6F1 0 3 RSa7F7 0 2 RSa7F5 0 1 RSa7F3 0 0 RSa7F1 0 Bit 7: Sa6 Bit of Frame 15 (RSa6F15). Bit 6: Sa6 Bit of Frame 13 (RSa6F13). Bit 5: Sa6 Bit of Frame 11 (RSa6F11). Bit 4: Sa6 Bit of Frame 9 (RSa6F9). Bit 3: Sa6 Bit of Frame 7 (RSa6F7).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RSa8F15 0 E1RSa8 (E1 Mode Only) Receive Sa8 Bits Register 06Dh 6 RSa8F13 0 5 RSa8F11 0 4 RSa8F9 0 3 RSa8F7 0 2 RSa8F5 0 1 RSa8F3 0 0 RSa8F1 0 3 Sa5 0 2 Sa6 0 1 Sa7 0 0 Sa8 0 Bit 7: Sa8 Bit of Frame 15 (RSa8F15). Bit 6: Sa8 Bit of Frame 13 (RSa8F13). Bit 5: Sa8 Bit of Frame 11 (RSa8F11). Bit 4: Sa8 Bit of Frame 9 (RSa8F9). Bit 3: Sa8 Bit of Frame 7 (RSa8F7).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 Sa6CODE Received Sa6 Codeword Register 06Fh 6 — 0 5 — 0 4 — 0 3 Sa6n 0 2 Sa6n 0 1 Sa6n 0 0 Sa6n 0 This register reports the received Sa6 codeword per ETS 300 233. The bits are monitored on a submultiframe asynchronous basis, so the pattern reported could be one of multiple patterns that would represent a valid codeword.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RCR1 (T1 Mode) Receive Control Register 1 081h Bit # Name Default 6 RB8ZS 0 7 SYNCT 0 5 RFM 0 4 ARC 0 3 SYNCC 0 2 RJC 0 1 SYNCE 0 0 RESYNC 0 Note: This register has an alternate definition for E1 mode. See RCR1. Bit 7: Sync Time (SYNCT). 0 = qualify 10 bits 1 = qualify 24 bits Bit 6: Receive B8ZS Enable (RB8ZS). 0 = B8ZS disabled 1 = B8ZS enabled Bit 5: Receive Frame Mode Select (RFM).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RCR1 (E1 Mode) Receive Control Register 1 081h Bit # Name Default 6 RHDB3 0 7 — 0 5 RSIGM 0 4 RG802 0 3 RCRC4 0 2 FRC 0 1 SYNCE 0 0 RESYNC 0 Note: This register has an alternate definition for T1 mode. See RCR1. Bit 6: Receive HDB3 Enable (RHDB3). 0 = HDB3 disabled 1 = HDB3 enabled (decoded per O.162) Bit 5: Receive-Signaling Mode Select (RSIGM).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 T1RIBCC (T1 Mode) Receive In-Band Code Control Register 082h 6 — 0 5 RUP2 0 4 RUP1 0 3 RUP0 0 Note: This register has an alternate definition for E1 mode. See E1RCR2. Bits 5 to 3: Receive Up Code Length Definition Bits (RUP[2:0]).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1RCR2 (E1 Mode) Receive Control Register 2 082h Bit # Name Default 6 RSa7S 0 7 RSa8S 0 5 RSa6S 0 4 RSa5S 0 3 RSa4S 0 2 — 0 1 — 0 0 RLOSA 0 Note: This register has an alternate definition for T1 mode. See T1RIBCC. Bit 7: Sa8 Bit Select (RSa8S). Set to one to have RLCLK pulse at the Sa8 bit position; set to zero to force RLCLK low during Sa8 bit position. Bit 6: Sa7 Bit Select (RSa7S).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RCR3 Receive Control Register 3 083h 6 — 0 5 RSERC 0 4 — 0 3 — 0 2 — 0 1 PLB 0 0 FLB 0 Bit 5: RSER Control (RSERC). 0 = allow RSER to output data as received under all conditions (normal operation) 1 = force RSER to one under loss of frame alignment conditions Bit 1: Payload Loopback (PLB).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default RIOCR Receive I/O Configuration Register 084h 7 6 5 4 RCLKINV RCLKINV RSYNCINV RSYNCINV H100EN H100EN RSCLKM RSCLKM 0 0 0 0 3 RSMS — 0 2 RSIO RSIO 1 1 RSMS2 RSMS2 0 0 RSMS1 RSMS1 0 Bit 7: RCLK Invert (RCLKINV). 0 = no inversion 1 = invert RCLK as input Bit 6: RSYNC Invert (RSYNCINV). 0 = no inversion 1 = invert RSYNC as either input or output Bit 5: H.100 SYNC Mode (H100EN).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default RESCR Receive Elastic Store Control Register 085h 7 6 RDATFMT RGCLKEN 0 0 5 — 0 4 RSZS 0 3 RESALGN 0 2 RESR 0 1 RESMDM 0 0 RESE 0 Bit 7: Receive Channel Data Format (RDATFMT). 0 = 64kbps (data contained in all 8 bits) 1 = 56kbps (data contained in 7 out of the 8 bits) Bit 6: Receive Gapped Clock Enable (RGCLKEN).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 1SECS 1SECS 0 ERCNT Error-Counter Configuration Register 086h 6 MCUS MCUS 0 5 MECU MECU 0 4 ECUS ECUS 0 3 EAMS EAMS 0 2 FSBE — 0 1 MOSCRF — 0 0 LCVCRF LCVCRF 0 Bit 7: One-Second Select (1SECS). This bit allows for synchronization of the error counter updates between multiple ports. When ERCNT.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default RHFC Receive HDLC FIFO Control Register 087h 7 — 0 6 — 0 5 — 0 4 — 0 3 — 0 Bits 1 and 0: Receive FIFO High Watermark Select (RFHWM[1:0]).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default RIBOC Receive Interleave Bus Operation Control Register 088h 7 — 0 6 IBS1 0 5 IBS0 0 4 IBOSEL 0 3 IBOEN 0 2 DA2 0 1 DA1 0 Bits 6 and 5: IBO Bus Size Bits (IBS[1:0]). Indicates how many devices on the bus. IBS1 0 0 1 1 IBS0 0 1 0 1 BUS SIZE 2 devices on bus (4.096MHz) 4 devices on bus (8.192MHz) 8 devices on bus (16.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 T1RSCC (T1 Mode Only) In-Band Receive Spare Control Register 089h 6 — 0 5 — 0 4 — 0 3 — 0 2 RSC2 0 1 RSC1 0 0 RSC0 0 2 RBPDIR RBPDIR 0 1 RBPFUS — 0 0 RBPEN RBPEN 0 Bits 2 to 0: Receive Spare Code Length Definition Bits (RSC[2:0]).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RBPBS Receive BERT Port Bit Suppress Register 08Bh Bit # Name Default 6 BPBSE7 0 7 BPBSE8 0 5 BPBSE6 0 4 BPBSE5 0 3 BPBSE4 0 2 BPBSE3 0 1 BPBSE2 0 0 BPBSE1 0 Bit 7: Receive Channel Bit 8 Suppress (BPBSE8). MSB of the channel. Set to one to stop this bit from being used. Bit 6: Receive Channel Bit 7 Suppress (BPBSE7). Set to one to stop this bit from being used.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RLS1 Receive Latched Status Register 1 090h Bit # Name Default 6 RAISC 0 7 RRAIC 0 5 RLOSC 0 4 RLOFC 0 3 RRAID 0 2 RAISD 0 1 RLOSD 0 0 RLOFD 0 Note: All bits in this register are latched and can create interrupts. Bit 7: Receive Remote Alarm Indication Condition Clear (RRAIC). Falling edge detect of RRAI. Set when a RRAI condition has cleared.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RPDV 0 RLS2 (T1 Mode) Receive Latched Status Register 2 091h 6 — 0 5 COFA 0 4 8ZD 0 3 16ZD 0 2 SEFE 0 1 B8ZS 0 0 FBE 0 Note: All bits in these register are latched. This register does not create interrupts. See RLS2 for E1 mode. Bit 7: Receive Pulse Density Violation Event (RPDV). Set when the receive data stream does not meet the ANSI T1.403 requirements for pulse density.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RLS2 (E1 Mode) Receive Latched Status Register 2 091h Bit # Name Default 6 CRCRC 0 7 — 0 5 CASRC 0 4 FASRC 0 3 RSA1 0 2 RSA0 0 1 RCMF 0 0 RAF 0 Note: All bits in this register are latched. Bits 0 to 3 can cause interrupts. There is no associated real-time register. See RLS2 for T1 mode. Bit 6: CRC Resync Criteria Met Event (CRCRC). Set when 915:1000 codewords are received in error.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 LORCC 0 RLS3 (T1 Mode) Receive Latched Status Register 3 092h 6 LSPC 0 5 LDNC 0 4 LUPC 0 3 LORCD 0 2 LSPD 0 1 LDND 0 0 LUPD 0 Note: All bits in this register are latched and can create interrupts. See RLS3 for E1mode. Bit 7: Loss of Receive Clock Condition Clear (LORCC). Falling edge detect of LORC. Set when an LORC condition was detected and then removed.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 LORCC 0 RLS3 (E1 Mode) Receive Latched Status Register 3 092h 6 — 0 5 V52LNKC 0 4 RDMAC 0 3 LORCD 0 2 — 0 1 V52LNKD 0 0 RDMAD 0 Note: All bits in this register are latched and can create interrupts. See RLS3 for T1 mode. Bit 7: Loss of Receive Clock Clear (LORCC). Change of state indication. Set when an LORC condition has cleared (falling edge detect of LORC) Bit 5: V5.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RLS4 Receive Latched Status Register 4 093h Bit # Name Default 6 RESEM 0 7 RESF 0 5 RSLIP 0 4 — 0 3 RSCOS 0 2 1SEC 0 1 TIMER 0 0 RMF 0 Note: All bits in this register are latched and can create interrupts. Bit 7: Receive Elastic Store Full Event (RESF). Set when the receive elastic store buffer fills and a frame is deleted. Bit 6: Receive Elastic Store Empty Event (RESEM).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RLS5 Receive Latched Status Register 5 (HDLC) 094h 6 — 0 5 ROVR 0 4 RHOBT 0 3 RPE 0 2 RPS 0 1 RHWMS 0 0 RNES 0 Note: All bits in this register are latched and can cause interrupts. Bit 5: Receive FIFO Overrun (ROVR). Set when the receive HDLC controller has terminated packet reception because the FIFO buffer is full. Bit 4: Receive HDLC Opening Byte Event (RHOBT).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RLS7 (T1 Mode) Receive Latched Status Register 7 096h 6 — 0 5 RRAI-CI 0 4 RAIS-CI 0 3 RSLC96 0 2 RFDLF 0 1 BC 0 0 BD 0 Note: All bits in this register are latched and can create interrupts. See RLS7 for E1 mode. Bit 5: Receive RAI-CI Detect (RRAI-CI). Set when an RAI-CI pattern has been detected by the receiver.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default RSS1, RSS2, RSS3, RSS4 Receive-Signaling Status Registers 1 to 4 098h, 099h, 09Ah, 09Bh (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 0 (LSB) CH1* CH9 CH17* CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 0 0 0 0 0 0 0 0 RSS1 RSS2 RSS3 RSS4 (E1 Mode Only) Note: Status bits in this register are latched.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 T1RSCD1 (T1 Mode Only) Receive Spare Code Definition Register 1 09Ch 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Note: Writing this register resets the detector’s integration period. Bit 7: Receive Spare Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6: Receive Spare Code Definition Bit 6 (C6). A Don’t Care if a 1-bit length is selected.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RIIR Receive Interrupt Information Register 09Fh 6 RLS7 0 5 RLS6* 0 4 RLS5 0 3 RLS4 0 2 RLS3 0 1 RLS2** 0 0 RLS1 0 *RLS6 is reserved for future use. **Currently, RLS2 does not create an interrupt, therefore this bit is not used in T1 mode. The Receive Interrupt Information register (RIIR) indicates which of the DS26521 status registers are generating an interrupt.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RIM2 (E1 Mode Only) Receive Interrupt Mask Register 2 0A1h 6 — 0 5 — 0 4 — 0 Bit 3: Receive-Signaling All-Ones Event (RSA1). 0 = interrupt masked 1 = interrupt enabled Bit 2: Receive-Signaling All-Zeros Event (RSA0). 0 = interrupt masked 1 = interrupt enabled Bit 1: Receive CRC-4 Multiframe Event (RCMF). 0 = interrupt masked 1 = interrupt enabled Bit 0: Receive Align Frame Event (RAF).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 LORCC 0 RIM3 (T1 Mode) Receive Interrupt Mask Register 3 0A2h 6 LSPC 0 5 LDNC 0 4 LUPC 0 Note: For E1 mode, see RIM3. Bit 7: Loss of Receive Clock Condition Clear (LORCC). 0 = interrupt masked 1 = interrupt enabled Bit 6: Spare Code Detected Condition Clear (LSPC). 0 = interrupt masked 1 = interrupt enabled Bit 5: Loop-Down Code Detected Condition Clear (LDNC).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 LORCC 0 RIM3 (E1 Mode) Receive Interrupt Mask Register 3 0A2h 6 — 0 5 V52LNKC 0 4 RDMAC 0 Note: For T1 mode, see RIM3. Bit 7: Loss of Receive Clock Clear (LORCC). 0 = interrupt masked 1 = interrupt enabled Bit 5: V5.2 Link Detected Clear (V52LNKC). 0 = interrupt masked 1 = interrupt enabled Bit 4: Receive Distant MF Alarm Clear (RDMAC).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: RIM4 Receive Interrupt Mask Register 4 0A3h Bit # Name Default 6 RESEM 0 7 RESF 0 5 RSLIP 0 4 — 0 Bit 7: Receive Elastic Store Full Event (RESF). 0 = interrupt masked 1 = interrupt enabled Bit 6: Receive Elastic Store Empty Event (RESEM). 0 = interrupt masked 1 = interrupt enabled Bit 5: Receive Elastic Store Slip Occurrence Event (RSLIP).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RIM5 Receive Interrupt Mask Register 5 (HDLC) 0A4h 6 — 0 5 ROVR 0 4 RHOBT 0 3 RPE 0 Bit 5: Receive FIFO Overrun (ROVR). 0 = interrupt masked 1 = interrupt enabled Bit 4: Receive HDLC Opening Byte Event (RHOBT). 0 = interrupt masked 1 = interrupt enabled Bit 3: Receive Packet-End Event (RPE). 0 = interrupt masked 1 = interrupt enabled Bit 2: Receive Packet-Start Event (RPS).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RIM7 (T1 Mode) Receive Interrupt Mask Register 7 (BOC:FDL) 0A6h 6 — 0 5 RRAI-CI 0 4 RAIS-CI 0 3 RSLC96 0 2 RFDLF 0 1 BC 0 0 BD 0 2 — 0 1 Sa6CD 0 0 SaXCD 0 Bit 5: Receive RAI-CI (RRAI-CI). 0 = interrupt masked 1 = interrupt enabled Bit 4: Receive AIS-CI (RAIS-CI). 0 = interrupt masked 1 = interrupt enabled Bit 3: Receive SLC-96 (RSLC96).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default RSCSE1, RSCSE2, RSCSE3, RSCSE4 Receive-Signaling Change of State Enable Registers 1 to 4 0A8h, 0A9h, 0AAh, 0ABh (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 0 (LSB) CH1 CH9 CH17 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 0 0 0 0 0 0 0 0 RSCSE1 RSCSE2 RSCSE3 RSCSE4 (E1 Mode Only) Setting any of the CH[
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 T1RUPCD1 (T1 Mode Only) Receive Up Code Definition Register 1 0ACh 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 1 C1 0 0 C0 0 Note: Writing this register resets the detector’s integration period. Bit 7: Receive Up Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6: Receive Up Code Definition Bit 6 (C6). A Don’t Care if a 1-bit length is selected.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 T1RDNCD1 (T1 Mode Only) Receive Down Code Definition Register 1 0AEh 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Note: Writing this register resets the detector’s integration period. Bit 7: Receive Down Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6: Receive Down Code Definition Bit 6 (C6). A Don’t Care if a 1-bit length is selected.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RRTS1 Receive Real-Time Status Register 1 0B0h 6 — 0 5 — 0 4 — 0 3 RRAI 0 2 RAIS 0 1 RLOS 0 0 RLOF 0 Note: All bits in this register are real-time (not latched). Bit 3: Receive Remote Alarm Indication Condition (RRAI). Set when a remote alarm is received at RTIP and RRING. Bit 2: Receive Alarm Indication Signal Condition (RAIS).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RRTS3 (T1 Mode) Receive Real-Time Status Register 3 0B2h 6 — 0 5 — 0 4 — 0 3 LORC 0 2 LSP 0 1 LDN 0 0 LUP 0 Note: All bits in this register are real-time (not latched). See RRTS3 for E1 mode. Bit 3: Loss of Receive Clock Condition (LORC). Set when the RCLK pin has not transitioned for one channel time. Bit 2: Spare Code Detected Condition (LSP).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 RRTS5 Receive Real-Time Status Register 5 (HDLC) 0B4h 6 PS2 0 5 PS1 0 4 PS0 0 3 — 0 2 — 0 1 RHWM 0 0 RNE 0 Note: All bits in this register are real time. Bits 6 to 4: Receive Packet Status (PS[2:0]). These are real-time bits indicating the status as of the last read of the receive FIFO. PS2 0 PS1 0 PS0 0 PACKET STATUS In Progress: End of message has not yet been reached.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 RHD7 0 RHF Receive HDLC FIFO Register 0B6h 6 RHD6 0 5 RHD5 0 4 RHD4 0 3 RHD3 0 2 RHD2 0 1 RHD1 0 0 RHD0 0 Bit 7: Receive HDLC Data Bit 7 (RHD7). MSB of a HDLC packet data byte. Bit 6: Receive HDLC Data Bit 6 (RHD6). Bit 5: Receive HDLC Data Bit 5 (RHD5). Bit 4: Receive HDLC Data Bit 4 (RHD4). Bit 3: Receive HDLC Data Bit 3 (RHD3). Bit 2: Receive HDLC Data Bit 2 (RHD2).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default RCBR1, RCBR2, RCBR3, RCBR4 Receive Channel Blocking Registers 1 to 4 0C4h, 0C5h, 0C6h, 0C7h 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 0 CH1 CH9 CH17 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 (F-bit) 0 0 0 0 0 0 0 0 RCBR1 RCBR2 RCBR3 RCBR4* (E1 Mode Only) Bits 7 to 0: Receive Channel Blocking Control Bit
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default RGCCS1, RGCCS2, RGCCS3, RGCCS4 Receive Gapped-Clock Channel Select Registers 1 to 4 0CCh, 0CDh, 0CEh, 0CFh 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 0 CH1 CH9 CH17 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 (F-bit) 0 0 0 0 0 0 0 0 RGCCS1 RGCCS2 RGCCS3 RGCCS4* (E1 Mode Only) Bits 7 to 0: Receive Gapped Cl
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default RBPCS1, RBPCS2, RBPCS3, RBPCS4 Receive BERT Port Channel Select Registers 1 to 4 0D4h, 0D5h, 0D6h, 0D7h (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 0 (LSB) CH1 CH9 CH17 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 0 0 0 0 0 0 0 0 RBPCS1 RBPCS2 RBPCS3 RBPCS4 (E1 Mode Only) Bits 7 to 0: BERT Port Channel
DS26521 Single T1/E1/J1 Transceiver 9.4.2 Transmit Register Definitions Register Name: Register Description: Register Address: THC1 Transmit HDLC Control Register 1 110h Bit # Name Default 6 TEOML 0 7 NOFS 0 5 THR 0 4 THMS 0 3 TFS 0 2 TEOM 0 1 TZSD 0 0 TCRCD 0 Bit 7: Number of Flags Select (NOFS). 0 = send one flag between consecutive messages 1 = send two flags between consecutive messages Bit 6: Transmit End of Message and Loop (TEOML).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: THBSE Transmit HDLC Bit Suppress Register 111h Bit # Name Default 6 TBSE7 0 7 TBSE8 0 5 TBSE6 0 4 TBSE5 0 3 TBSE4 0 2 TBSE3 0 1 TBSE2 0 0 TBSE1 0 Bit 7: Transmit Bit 8 Suppress (TBSE8). MSB of the channel. Set to one to stop this bit from being used. Bit 6: Transmit Bit 7 Suppress (TBSE7). Set to one to stop this bit from being used. Bit 5: Transmit Bit 6 Suppress (TBSE6).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 SiAF 0 E1TSACR (E1 Mode) E1 Transmit Sa-Bit Control Register 114h 6 SiNAF 0 5 RA 0 4 Sa4 0 3 Sa5 0 2 Sa6 0 Bit 7: International Bit in Align Frame Insertion Control Bit (SiAF).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: SSIE1, SSIE2, SSIE3, SSIE4 Software-Signaling Insertion Enable Registers 1 to 4 118h, 119h, 11Ah, 11Bh Bit # Name (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 0 (LSB) CH1 CH9 CH17 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 0 0 0 0 0 0 0 0 Default SSIE1 SSIE2 SSIE3 SSIE4 (E1 Mode Only) Bits 7 to 0: Software Signaling Ins
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1 Mode: Bit # (MSB) 7 Name CH1-A CH2-A CH3-A CH4-A CH5-A CH6-A CH7-A CH8-A CH9-A CH10-A CH11-A CH12-A TS1 to TS16 Transmit-Signaling Registers 1 to 16 140h to 14Fh 6 CH1-B CH2-B CH3-B CH4-B CH5-B CH6-B CH7-B CH8-B CH9-B CH10-B CH11-B CH12-B 5 CH1-C CH2-C CH3-C CH4-C CH5-C CH6-C CH7-C CH8-C CH9-C CH10-C CH11-C CH12-C 4 CH1-D CH2-D CH3-D CH4-D CH5-D CH6-D CH7-D CH8-D CH9-D CH10-D CH11-D CH12-D 3 CH13-A CH14-A CH
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default TCICE1, TCICE2, TCICE3, TCICE4 Transmit Channel Idle Code Enable Registers 1 to 4 150h, 151h, 152h, 153h (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 0 (LSB) CH1 CH9 CH17 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 0 0 0 0 0 0 0 0 TCICE1 TCICE2 TCICE3 TCICE4 (E1 Mode Only) The Transmit Channel Idle Cod
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 FR7 0 TFRID Transmit Firmware Revision ID Register 161h 6 FR6 0 5 FR5 0 4 FR4 0 3 FR3 0 2 FR2 0 1 FR1 0 0 FR0 0 Bits 7 to 0: Firmware Revision (FR[7:0]). This read-only register reports the transmitter firmware revision.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: T1TSLC1, T1TSLC2, T1TSLC3 (T1 Mode) Transmit SLC-96 Data Link Registers 1 to 3 164h, 165h, 166h Bit # Name 6 C7 M1 S4 0 Default (MSB) 7 C8 M2 S=1 0 5 C6 S=0 S3 0 4 C5 S=1 S2 0 3 C4 S=0 S1 0 2 C3 C11 A2 0 1 C2 C10 A1 0 0 (LSB) C1 C9 M3 0 T1TSLC1 T1TSLC2 T1TSLC3 Note: See E1TAF, E1TNAF, and E1TSiAF for E1 modes.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1TSiAF (E1 Mode) Transmit Si Bits of the Align Frame Register 166h Bit # Name Default 6 TSiF12 0 7 TSiF14 0 5 TSiF10 0 4 TSiF8 0 3 TSiF6 0 2 TSiF4 0 1 TSiF2 0 0 TSiF0 0 2 TSiF5 0 1 TSiF3 0 0 TSiF1 0 Bit 7: Si Bit of Frame 14 (TSiF14). Bit 6: Si Bit of Frame 12 (TSiF12). Bit 5: Si Bit of Frame 10 (TSiF10). Bit 4: Si Bit of Frame 8 (TSiF8). Bit 3: Si Bit of Frame 6 (TSiF6).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: E1TRA (E1 Mode Only) Transmit Remote Alarm Register 168h Bit # Name Default 6 TRAF13 0 7 TRAF15 0 5 TRAF11 0 4 TRAF9 0 3 TRAF7 0 2 TRAF5 0 1 TRAF3 0 0 TRAF1 0 3 TSa4F7 0 2 TSa4F5 0 1 TSa4F3 0 0 TSa4F1 0 Bit 7: Remote Alarm Bit of Frame 15 (TRAF15). Bit 6: Remote Alarm Bit of Frame 13 (TRAF13). Bit 5: Remote Alarm Bit of Frame 11 (TRAF11). Bit 4: Remote Alarm Bit of Frame 9 (TRAF9).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TSa5F15 0 E1TSa5 (E1 Mode Only) Transmit Sa5 Bits Register 16Ah 6 TSa5F13 0 5 TSa5F11 0 4 TSa5F9 0 3 TSa5F7 0 2 TSa5F5 0 1 TSa5F3 0 0 TSa5F1 0 3 TSa6F7 0 2 TSa6F5 0 1 TSa6F3 0 0 TSa6F1 0 Bit 7: Sa5 Bit of Frame 15 (TSa5F15). Bit 6: Sa5 Bit of Frame 13 (TSa5F13). Bit 5: Sa5 Bit of Frame 11 (TSa5F11). Bit 4: Sa5 Bit of Frame 9 (TSa5F9). Bit 3: Sa5 Bit of Frame 7 (TSa5F7).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TSa7F15 0 E1TSa7 (E1 Mode Only) Transmit Sa7 Bits Register 16Ch 6 TSa7F13 0 5 TSa7F11 0 4 TSa7F9 0 3 TSa7F7 0 2 TSa7F5 0 1 TSa7F3 0 0 TSa7F1 0 3 TSa8F7 0 2 TSa8F5 0 1 TSa8F3 0 0 TSa8F1 0 Bit 7: Sa7 Bit of Frame 15 (TSa7F15). Bit 6: Sa7 Bit of Frame 13 (TSa7F13). Bit 5: Sa7 Bit of Frame 11 (TSa7F11). Bit 4: Sa7 Bit of Frame 9 (TSa7F9). Bit 3: Sa7 Bit of Frame 7 (TSa7F7).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 FRM_EN 0 TMMR Transmit Master Mode Register 180h 6 INIT_DONE 0 5 — 0 4 — 0 3 — 0 2 — 0 1 SFTRST 0 0 T1/E1 0 Bit 7: Framer Enable (FRM_EN). This bit must be set to the desired state before writing INIT_DONE. 0 = Framer disabled—held in low-power state 1 = Framer enabled—all features active Bit 6: Initialization Done (INIT_DONE).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TJC 0 TCR1 (T1 Mode) Transmit Control Register 1 181h 6 TFPT 0 5 TCPT 0 4 TSSE 0 3 GB7S 0 2 TB8ZS 0 1 TAIS 0 0 TRAI 0 Note: See TCR1 for E1 mode. Bit 7: Transmit Japanese CRC-6 Enable (TJC). 0 = use ANSI/AT&T:ITU-T CRC-6 calculation (normal operation) 1 = use Japanese standard JT-G704 CRC-6 calculation Bit 6: Transmit F-Bit Pass Through (TFPT).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TTPT 0 TCR1 (E1 Mode) Transmit Control Register 1 181h 6 T16S 0 5 TG802 0 4 TSiS 0 3 TSA1 0 2 THDB3 0 1 TAIS 0 Note: See TCR1 for T1 mode. Bit 7: Transmit Time Slot 0 Pass Through (TTPT). 0 = FAS bits/Sa bits/remote alarm sourced internally from the E1TAF and E1TNAF registers 1 = FAS bits/Sa bits/remote alarm sourced from TSER Bit 6: Transmit Time Slot 16 Data Select (T16S).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TCR2 (T1 Mode) Transmit Control Register 2 182h Bit # Name Default 6 TSLC96 0 7 TFDLS 0 5 — 0 4 FBCT2 0 3 FBCT1 0 2 TD4RM 0 1 PDE 0 0 TB7ZS 0 Note: See TCR2 for E1 mode. Bit 7: TFDL Register Select (TFDLS). 0 = source FDL or Fs bits from the internal TFDL register or the SLC-96 data formatter (TCR2.6) 1 = source FDL or Fs bits from the internal HDLC controller Bit 6: Transmit SLC-96 (TSLC96).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 AEBE 0 TCR2 (E1 Mode) Transmit Control Register 2 182h 6 AAIS 0 5 ARA 0 4 Sa4S 0 3 Sa5S 0 2 Sa6S 0 1 Sa7S 0 Note: See TCR2 for T1 mode. Bit 7: Automatic E-Bit Enable (AEBE). 0 = E-bits not automatically set in the transmit direction 1 = E-bits automatically set in the transmit direction Bit 6: Automatic AIS Generation (AAIS).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 ODF ODF 0 TCR3 Transmit Control Register 3 183h 6 ODM ODM 0 5 TCSS1 TCSS1 0 4 TCSS0 TCSS0 0 3 MFRS MFRS 0 2 TFM — 0 1 IBPV IBPV 0 0 TLOOP CRC4R 0 Bit 7: Output Data Format (ODF). 0 = bipolar data at TTIP and TRING 1 = NRZ data at TTIP; TRING = 0 Bit 6: Output Data Mode (ODM).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TCLKINV TCLKINV 0 TIOCR Transmit I/O Configuration Register 184h 6 5 TSYNCINV TSYNCINV TSSYNCINV TSSYNCINV 0 0 4 TSCLKM TSCLKM 0 3 TSSM TSSM 0 2 TSIO TSIO 0 1 TSDW — 0 0 TSM TSM 0 Bit 7: TCLK Invert (TCLKINV). 0 = No inversion 1 = Invert Bit 6: TSYNC Invert (TSYNCINV). 0 = No inversion 1 = Invert Bit 5: TSSYNCIO Invert (TSSYNCINV) (Input Mode Only).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TDATFMT 0 TESCR Transmit Elastic Store Control Register 185h 6 TGCLKEN 0 5 — 0 4 TSZS 0 3 TESALGN 0 2 TESR 0 1 TESMDM 0 0 TESE 0 Note: Bits 7 and 6 are used for fractional backplane support. See Section 8.8.5. Bit 7: Transmit Channel Data Format (TDATFMT).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TCR4 (T1 Mode Only) Transmit Control Register 4 186h 6 — 0 5 — 0 4 — 0 3 TRAIM 0 2 TAISM 0 1 TC1 0 0 TC0 0 Bits 3: Transmit RAI Mode (TRAIM). Determines the pattern sent when TRAI (TCR1.0) is activated in ESF frame mode only. 0 = transmit normal RAI upon activation with TCR1.0 1 = transmit RAI-CI (T1.403) upon activation with TCR1.0 Bits 2: Transmit AIS Mode (TAISM).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TIBOC Transmit Interleave Bus Operation Control Register 188h 6 IBS1 0 5 IBS0 0 4 IBOSEL 0 3 IBOEN 0 2 DA2 0 1 DA1 0 0 DA0 0 Bits 6 and 5: IBO Bus Size (IBS[1:0]). Indicates how many devices are on the bus. IBS1 0 0 1 1 IBS0 0 1 0 1 BUS SIZE 2 devices on bus 4 devices on bus 8 devices on bus Reserved for future use Bit 4: Interleave Bus Operation Select (IBOSEL).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TXPC Transmit Expansion Port Control Register 18Ah 6 — 0 5 — 0 4 — 0 3 — 0 2 TBPDIR 0 1 TBPFUS 0 0 TBPEN 0 Bit 2: Transmit BERT Port Direction Control (TBPDIR). 0 = Normal (line) operation. The transmit BERT port sources data into the transmit path. 1 = System (backplane) operation. The transmit BERT port sources data into the transmit path (RDATA).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 BPBSE8 0 TBPBS Transmit BERT Port Bit Suppress Register 18Bh 6 BPBSE7 0 5 BPBSE6 0 4 BPBSE5 0 3 BPBSE4 0 2 BPBSE3 0 1 BPBSE2 0 0 BPBSE1 0 Bit 7: Transmit Channel Bit 8 Suppress (BPBSE8). MSB of the channel. Set to one to stop this bit from being used. Bit 6: Transmit Channel Bit 7 Suppress (BPBSE7). Set to one to stop this bit from being used.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TLS1 Transmit Latched Status Register 1 190h Bit # Name 6 TESEM TESEM 0 Default 7 TESF TESF 0 5 TSLIP TSLIP 0 4 TSLC96 — 0 3 TPDV TAF 0 2 TMF TMF 0 1 LOTCC LOTCC 0 0 LOTC LOTC 0 Note: All bits in this register are latched and can cause interrupts. Bit 7: Transmit Elastic Store Full Event (TESF). Set when the transmit elastic store buffer fills and a frame is deleted.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — — 0 TLS2 Transmit Latched Status Register 2 (HDLC) 191h 6 — — 0 5 — — 0 4 TFDLE — 0 3 TUDR TUDR 0 2 TMEND TMEND 0 1 TLWMS TLWMS 0 0 TNFS TNFS 0 Note: All bits in this register are latched and can create interrupts. Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only). Set when the TFDL register has shifted out all 8 bits.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TIIR Transmit Interrupt Information Register 19Fh 6 — 0 5 — 0 4 — 0 3 — 0 2 TLS3 0 1 TLS2 0 0 TLS1 0 The Transmit Interrupt Information register provides an indication of which status registers are generating an interrupt. When an interrupt occurs, the host can read TIIR to quickly identify which of the transmit status registers are causing the interrupt(s).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: TIM1 Transmit Interrupt Mask Register 1 1A0h Bit # Name 6 TESEM TESEM 0 Default 7 TESF TESF 0 5 TSLIP TSLIP 0 4 TSLC96 — 0 3 TPDV TAF 0 Bit 7: Transmit Elastic Store Full Event (TESF). 0 = interrupt masked 1 = interrupt enabled Bit 6: Transmit Elastic Store Empty Event (TESEM). 0 = interrupt masked 1 = interrupt enabled Bit 5: Transmit Elastic Store Slip Occurrence Event (TSLIP).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — — 0 TIM2 Transmit Interrupt Mask Register 2 (HDLC) 1A1h 6 — — 0 5 — — 0 4 TFDLE — 0 3 TUDR TUDR 0 2 TMEND TMEND 0 1 TLWMS TLWMS 0 0 TNFS TNFS 0 1 — 0 0 LOFD 0 Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only). 0 = interrupt masked 1 = interrupt enabled Bit 3: Transmit FIFO Underrun Event (TUDR).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 C7 0 T1TCD1 (T1 Mode Only) Transmit Code Definition Register 1 1ACh 6 C6 0 5 C5 0 4 C4 0 3 C3 0 2 C2 0 1 C1 0 0 C0 0 Bit 7: Transmit Code Definition Bit 7 (C7). First bit of the repeating pattern. Bit 6: Transmit Code Definition Bit 6 (C6). Bit 5: Transmit Code Definition Bit 5 (C5). Bit 4: Transmit Code Definition Bit 4 (C4). Bit 3: Transmit Code Definition Bit 3 (C3).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 TRTS2 Transmit Real-Time Status Register 2 (HDLC) 1B1h 6 — 0 5 — 0 4 — 0 3 TEMPTY 0 2 TFULL 0 1 TLWM 0 0 TNF 0 Note: All bits in this register are real time. Bit 3: Transmit FIFO Empty (TEMPTY). A real-time bit that is set high when the FIFO is empty. Bit 2: Transmit FIFO Full (TFULL). A real-time bit that is set high when the FIFO is full.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default TDS0M Transmit DS0 Monitor Register 1BBh 7 B1 0 6 B2 0 5 B3 0 4 B4 0 3 B5 0 2 B6 0 1 B7 0 0 B8 0 Bits 7 to 0: Transmit DS0 Channel Bits (B[1:8]). Transmit channel data that has been selected by the Transmit DS0 Channel Monitor Select register (TDS0SEL). B8 is the LSB of the DS0 channel (last bit to be transmitted).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default TCBR1, TCBR2, TCBR3, TCBR4 Transmit Channel Blocking Registers 1 to 4 1C4h, 1C5h, 1C6h, 1C7h (MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 CH9 CH17 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 (F-bit) 0 0 0 0 0 0 0 0 TCBR1 TCBR2 TCBR3 TCBR4* (E1 Mode Only) Bits 7 to 0: Transmit Channel Blocking Channels 1 to
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: THSCS1, THSCS2, THSCS3, THSCS4 Transmit Hardware-Signaling Channel Select Registers 1 to 4 1C8h, 1C9h, 1CAh, 1CBh Bit # Name (MSB) 7 CH8 CH16 CH24 6 CH7 CH15 CH23 5 CH6 CH14 CH22 4 CH5 CH13 CH21 3 CH4 CH12 CH20 2 CH3 CH11 CH19 1 CH2 CH10 CH18 0 (LSB) CH1 CH9 CH17 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 0 0 0 0 0 0 0 0 Default THSCS1 THSCS2 THSCS3 THSCS4* (E1 Mode Only) Bits 7 to 0: Transm
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default PCL1, PCL2, PCL3, PCL4 Per-Channel Loopback Enable Registers 1 to 4 1D0h, 1D1h, 1D2h, 1D3h (MSB) CH8 CH16 CH24 CH7 CH15 CH23 CH6 CH14 CH22 CH5 CH13 CH21 CH4 CH12 CH20 CH3 CH11 CH19 CH2 CH10 CH18 (LSB) CH1 CH9 CH17 CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 0 0 0 0 0 0 0 0 PCL1 PCL2 PCL3 PCL4 (E1 Mode Only) Bits 7 to 0: Per-Channel Loopback Enable for Channels 1 to 32 (CH[1
DS26521 Single T1/E1/J1 Transceiver 9.5 LIU Register Definitions Table 9-14.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 LTITSR LIU Transmit Impedance and Pulse Shape Selection Register 1001h 6 TIMPTOFF 0 5 TIMPL1 0 4 TIMPL0 0 3 — 0 2 L2 0 1 L1 0 0 L0 0 Bit 6: Transmit Impedance Off (TIMPTOFF). 0 = Enable transmit terminating impedance. 1 = Disable transmit terminating impedance. Bits 5 and 4: Transmit Load Impedance 1 and 0 (TIMPL[1:0]). These bits are used to select the transmit load impedance.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TAIS 0 LMCR LIU Maintenance Control Register 1002h 6 ATAIS 0 5 LLB 0 4 ALB 0 3 RLB 0 2 TPDE 0 1 RPDE 0 0 TE 0 Bit 7: Transmit AIS (TAIS). Alarm Indication Signal (AIS) is sent using MCLK as the reference clock. The transmit data coming from the framer is ignored. 0 = TAIS is disabled. 1 = Output an unframed all-ones pattern (AIS) at TTIP and TRING. Bit 6: Automatic Transmit AIS (ATAIS).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 LRSR LIU Real Status Register 1003h 6 — 0 5 OEQ 0 4 UEQ 0 3 — 0 2 SCS 0 1 OCS 0 0 LOSS 0 Bit 5: Over Equalized (OEQ). The equalizer is over equalized. This can happen if there is very large unexpected resistive loss. This could result if monitor mode is used and the device is not placed in monitor mode.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: LSIMR LIU Status Interrupt Mask Register 1004h Bit # Name Default 6 OCCIM 0 7 JALTCIM 0 5 SCCIM 0 4 LOSCIM 0 3 JALTSIM 0 Bit 7: Jitter Attenuator Limit Trip Clear Interrupt Mask (JALTCIM). 0 = Interrupt masked. 1 = Interrupt enabled. Bit 6: Open-Circuit Clear Interrupt Mask (OCCIM). 0 = Interrupt masked. 1 = Interrupt enabled. Bit 5: Short-Circuit Clear Interrupt Mask (SCCIM). 0 = Interrupt masked.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 JALTC 0 LLSR LIU Latched Status Register 1005h 6 OCC 0 5 SCC 0 4 LOSC 0 3 JALTS 0 2 OCD 0 1 SCD 0 0 LOSD 0 Note: All bits in this register are latched and can create interrupts. Bit 7: Jitter Attenuator Limit Trip Clear (JALTC). This latched bit is set when a jitter attenuator limit trip condition was detected and then removed. Bit 6: Open-Circuit Clear (OCC).
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default LRSL LIU Receive Signal Level Register 1006h 7 RSL3 0 6 RSL2 0 5 RLS1 0 4 RLS0 0 3 — 0 2 — 0 1 — 0 0 — 0 Bits 7 to 4: Receiver Signal Level 3 to 0 (RSL[3:0]). Real-time receive signal level as shown in Table 9-17. Note that the range of signal levels reported the RSL[3:0] is limited by the Equalizer Gain Limit (EGL) in short-haul applications. Table 9-17.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: LRISMR LIU Receive Impedance and Sensitivity Monitor Register 1007h Bit # Name Default 6 RIMPOFF 0 7 RG703 0 5 RIMPM1 0 4 RIMPM0 0 3 RTR 0 2 RMONEN 0 1 RSMS1 0 0 RSMS0 0 Bit 7: Receive G.703 Clock Enable (RG703). If this bit is set, the receiver expects a 2.048MHz or 1.544MHz clock from the RTIP/RRING, based on the selection of T1 (1.544) or E1 (2.048) mode in the LTRCR register.
DS26521 Single T1/E1/J1 Transceiver Table 9-19. Receiver Sensitivity Selection with Monitor Mode Disabled RMONEN RSMS[1:0] 0 0 0 0 00 01 10 11 RECEIVER MONITOR MODE GAIN (dB) 0 0 0 0 RECEIVER SENSITIVITY (MAX CABLE LOSS ALLOWED) (dB) 12 18 30 36 for T1; 43 for E1 Table 9-20. Receiver Sensitivity Selection with Monitor Mode Enabled RMONEN RSMS[1:0] 1 1 1 1 00 01 10 11 RECEIVER MONITOR MODE GAIN (dB) 14 20 26 32 RECEIVER SENSITIVITY (MAX CABLE LOSS ALLOWED) (dB) 30 22.5 17.
DS26521 Single T1/E1/J1 Transceiver 9.6 BERT Register Definitions Table 9-21.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: BRP1 BERT Repetitive Pattern Set Register 1 1101h Bit # Name Default 6 RPAT6 0 7 RPAT7 0 5 RPAT5 0 4 RPAT4 0 3 RPAT3 0 2 RPAT2 0 1 RPAT1 0 0 RPAT0 0 Bits 7 to 0: BERT Repetitive Pattern Set Bits 7 to 0 (RPAT[7:0]). RPAT0 is the LSB of the 32-bit repetitive pattern.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 TC 0 BC1 BERT Control Register 1 1105h 6 TINV 0 5 RINV 0 4 PS2 0 3 PS1 0 2 PS0 0 1 LC 0 0 RESYNC 0 Bit 7: Transmit Pattern Load (TC). A low-to-high transition loads the pattern generator with the pattern that is to be generated. This bit should be toggled from low to high whenever the host wishes to load a new pattern. Must be cleared and set again for subsequent loads.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default BC2 BERT Control Register 2 1106h 7 EIB2 0 6 EIB1 0 5 EIB0 0 4 SBE 0 3 RPL3 0 2 RPL2 0 1 RPL1 0 0 RPL0 0 Bits 7 to 5: Error Insert Bits 2 to 0 (EIB[2:0]). Will automatically insert bit errors at the prescribed rate into the generated data pattern. Can be used for verifying error detection features. See Table 9-23. Table 9-23.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 BBC7 0 BBC1 BERT Bit Count Register 1 1107h 6 BBC6 0 5 BBC5 0 4 BBC4 0 3 BBC3 0 2 BBC2 0 1 BBC1 0 0 BBC0 0 Bits 7 to 0: BERT Bit Counter Bits 7 to 0 (BBC[7:0]). BBC0 is the LSB of the 32-bit counter.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 EC7 0 BEC1 BERT Error Count Register 1 110Bh 6 EC6 0 5 EC5 0 4 EC4 0 3 EC3 0 2 EC2 0 1 EC1 0 0 EC0 0 Bits 7 to 0: Error Counter Bits 7 to 0 (EC[7:0]). EC0 is the LSB of the 24-bit counter.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 BLSR BERT Latched Status Register 110Eh 6 BBED 0 5 BBCO 0 4 BECO 0 3 BRA1 0 2 BRA0 0 1 BRLOS 0 0 BSYNC 0 Note: All bits in this register are latched and can create interrupts. Bit 6: BERT Bit-Error-Detected Event (BBED). A latched bit that is set when a bit error is detected. The receive BERT must be in synchronization for it to detect bit errors.
DS26521 Single T1/E1/J1 Transceiver Register Name: Register Description: Register Address: Bit # Name Default 7 — 0 BSIM BERT Status Interrupt Mask Register 110Fh 6 BBED 0 5 BBCO 0 4 BECO 0 3 BRA1 0 Bit 6: BERT Bit-Error-Detected Event (BBED). 0 = interrupt masked 1 = interrupt enabled Bit 5: BERT Bit Counter Overflow Event (BBCO). 0 = interrupt masked 1 = interrupt enabled Bit 4: BERT Error Counter Overflow Event (BECO).
DS26521 Single T1/E1/J1 Transceiver 10. FUNCTIONAL TIMING 10.1 T1 Receiver Functional Timing Diagrams Figure 10-1. T1 Receive-Side D4 Timing 1 FRAME# 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 RFSYNC RSYNC 1 RSYNC 2 RSYNC 3 NOTE 1: RSYNC IN THE FRAME MODE (RIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (RIOCR.1 = 0). NOTE 2: RSYNC IN THE FRAME MODE (RIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (RIOCR.1 = 1). NOTE 3: RSYNC IN THE MULTIFRAME MODE (RIOCR.0 = 1). Figure 10-2.
DS26521 Single T1/E1/J1 Transceiver Figure 10-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled) RCLK CHANNEL 23 CHANNEL 24 RSER CHANNEL 1 LSB LSB MSB F MSB RSYNC RFSYNC RSIG CHANNEL 23 A B C/A D/B CHANNEL 24 A B C/A D/B CHANNEL 1 A RCHCLK RCHBLK1 NOTE 1: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. Figure 10-4. T1 Receive-Side 1.
DS26521 Single T1/E1/J1 Transceiver Figure 10-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) RSYSCLK RSER RSYNC 1 CHANNEL 31 CHANNEL 32 CHANNEL 1 LSB LSB MSB 2 RMSYNC 3 RSYNC RSIG A CHANNEL 31 B C/A D/B A CHANNEL 32 B C/A D/B RCHCLK RCHBLK 4 NOTE 1: RSER DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 ARE FORCED TO ONE. NOTE 2: RSYNC IS IN THE OUTPUT MODE (RIOCR.2 = 0). NOTE 3: RSYNC IS IN THE INPUT MODE (RIOCR.2 = 1). NOTE 4: RCHBLK IS PROGRAMMED TO BLOCK CHANNEL 1.
DS26521 Single T1/E1/J1 Transceiver Figure 10-6.
DS26521 Single T1/E1/J1 Transceiver Figure 10-7.
DS26521 Single T1/E1/J1 Transceiver 10.2 T1 Transmitter Functional Timing Diagrams Figure 10-8. T1 Transmit-Side D4 Timing FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 1 TSYNC TSSYNC 2 TSYNC 3 TSYNC NOTE 1: TSYNC IN THE FRAME MODE (TIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS NOT ENABLED (TIOCR.1 = 0). NOTE 2: TSYNC IN THE FRAME MODE (TIOCR.0 = 0) AND DOUBLE-WIDE FRAME SYNC IS ENABLED (TIOCR.1 = 1). NOTE 3: TSYNC IN THE MULTIFRAME MODE (TIOCR.0 = 1). Figure 10-9.
DS26521 Single T1/E1/J1 Transceiver Figure 10-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled) TCLK CHANNEL 1 TSER LSB F CHANNEL 2 MSB LSB MSB LSB MSB TSYNC1 TSYNC2 CHANNEL 1 TSIG D/B A B CHANNEL 2 C/A D/B A B C/A D/B TCHCLK TCHBLK 3 NOTE 1: TSYNC IS IN THE OUTPUT MODE (TIOCR.2 = 1). NOTE 2: TSYNC IS IN THE INPUT MODE (TIOCR.2 = 0). NOTE 3: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 2. Figure 10-11. T1 Transmit-Side 1.
DS26521 Single T1/E1/J1 Transceiver Figure 10-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) TSYSCLK CHANNEL 31 TSER 1 CHANNEL 32 LSB MSB CHANNEL 1 LSB 3 F TSSYNC CHANNEL 31 TSIG A B CHANNEL 32 C/A D/B A B CHANNEL 1 C/A D/B A TCHCLK TCHBLK 2 NOTE 1: TSER DATA IN CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS IGNORED. NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNELS 31 AND 1.
DS26521 Single T1/E1/J1 Transceiver Figure 10-13.
DS26521 Single T1/E1/J1 Transceiver Figure 10-14.
DS26521 Single T1/E1/J1 Transceiver 10.3 E1 Receiver Functional Timing Diagrams Figure 10-15. E1 Receive-Side Timing FRAME# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 RFSYNC RSYNC 1 RSYNC 2 NOTE 1: RSYNC IN FRAME MODE (RIOCR.0 = 0). NOTE 2: RSYNC IN MULTIFRAME MODE (RIOCR.0 = 1). NOTE 3: THIS DIAGRAM ASSUMES THE CAS MF BEGINS IN THE RAF FRAME. Figure 10-16.
DS26521 Single T1/E1/J1 Transceiver Figure 10-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled) RSYSCLK CHANNEL 23/31 1 RSER CHANNEL 24/32 CHANNEL 1/2 LSB LSB MSB F MSB RSYNC2 RMSYNC 3 RSYNC RCHCLK 4 RCHBLK NOTE 1: DATA FROM THE E1 CHANNELS 1, 5, 9, 13, 17, 21, 25, AND 29 IS DROPPED (CHANNEL 2 FROM THE E1 LINK IS MAPPED TO CHANNEL 1 OF THE T1 LINK, ETC.) AND THE F-BIT POSITION IS ADDED (FORCED TO ONE). NOTE 2: RSYNC IN THE OUTPUT MODE (RIOCR.2 = 0).
DS26521 Single T1/E1/J1 Transceiver 10.4 E1 Transmitter Functional Timing Diagrams Figure 10-19. E1 Transmit-Side Timing FRAME# 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 1 TSYNC TSSYNC TSYNC 2 NOTE 1: TSYNC IN FRAME MODE (TIOCR.0 = 0). NOTE 2: TSYNC IN MULTIFRAME MODE (TIOCR.0 = 1). NOTE 3: THIS DIAGRAM ASSUMES BOTH THE CAS MF AND THE CRC-4 MF BEGIN WITH THE TAF FRAME. Figure 10-20.
DS26521 Single T1/E1/J1 Transceiver Figure 10-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) TSYSCLK CHANNEL 23 1 CHANNEL 24 LSB MSB TSER CHANNEL 1 LSB F MSB TSSYNC TCHCLK TCHBLK 2 NOTE 1: THE F-BIT POSITION IN THE TSER DATA IS IGNORED. NOTE 2: TCHBLK IS PROGRAMMED TO BLOCK CHANNEL 24. Figure 10-22. E1 Transmit-Side 2.
DS26521 Single T1/E1/J1 Transceiver Figure 10-23. E1 G.802 Timing TS # 31 32 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 RSYNC TSYNC RCHCLK TCHCLK RCHBLK TCHBLK RCLK / RSYSCLK TCLK / TSYSCLK CHANNEL 25 RSER / TSER CHANNEL 26 LSB MSB RCHCLK / TCHCLK RCHBLK / TCHBLK NOTE: RCHBLK OR TCHBLK PROGRAMMED TO PULSE HIGH DURING TIME SLOTS 1 THROUGH 15, 17 THROUGH 25, AND BIT 1 OF TIME SLOT 26.
DS26521 Single T1/E1/J1 Transceiver 11. OPERATING PARAMETERS ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Lead with Respect to VSS (except VDD)…………………………………………….-0.3V to +5.5V Supply Voltage (VDD) Range with Respect to VSS…………………………………………………………..-0.3V to +3.63V Operating Temperature Range..……………………………………………………………………-40°C to +85°C (Note 1) Storage Temperature Range...………………………………………………………………………………-55°C to +125°C Soldering Temperature………………………………………………………….
DS26521 Single T1/E1/J1 Transceiver 11.1 Thermal Characteristics Table 11-4. Thermal Characteristics PARAMETER CONDITIONS Ambient Temperature (Note 1) MIN TYP -40 Junction Temperature Theta-JA (θJA) in Still Air for 64-Pin LQFP (Note 2) MAX UNITS +85 °C +125 °C +17.5 °C/W Note 1: The package is mounted on a four-layer JEDEC standard test board. Note 2: Theta-JA (θJA) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard test board.
DS26521 Single T1/E1/J1 Transceiver 12. AC TIMING CHARACTERISTICS Unless otherwise noted, all timing numbers assume 20pF test load on output signals, 40pF test load on bus signals. 12.1 Microprocessor Bus AC Characteristics 12.1.1 Parallel Port Mode Table 12-1. AC Characteristics—Microprocessor Bus Timing (VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Note 1) (See Figure 12-1, Figure 12-2, Figure 12-3, and Figure 12-4.
DS26521 Single T1/E1/J1 Transceiver Figure 12-1. Intel Bus Read Timing (BTS = 0) t9 A12, A[8:0] Address Valid Data Valid D[7:0] t5 WRB t1 CSB t2 t4 t3 RDB t10 Figure 12-2.
DS26521 Single T1/E1/J1 Transceiver Figure 12-3. Motorola Bus Read Timing (BTS = 1) t9 Address Valid A12, A[8:0] Data Valid D[7:0] t5 RWB t1 CSB t2 t4 t3 DSB t10 Figure 12-4.
DS26521 Single T1/E1/J1 Transceiver 12.1.2 SPI Bus Mode Table 12-2. SPI Bus Mode Timing (See Note 1, Figure 12-5.
DS26521 Single T1/E1/J1 Transceiver Figure 12-5. SPI Interface Timing Diagram CS INPUT t3 t2 t1 SPI_SCLK t4 t5 SPI_SCLK1 t8 MOSI INPUT SLAVE MSB t6 t7 t9 MISO OUTPUT SLAVE LSB BITS 6:1 MSB BIT 14 t10 BITS 13:0 NOTE 1: CLOCK EDGE REFERENCE TO DATA CONTROLLED BY CPHA AND CPOL SETTINGS. SEE THE FUNCTIONAL TIMING DIAGRAMS. NOTE 2: NOT DEFINED, BUT USUALLY MSB OF CHARACTER JUST RECEIVED.
DS26521 Single T1/E1/J1 Transceiver Table 12-3. Receiver AC Characteristics (VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Note 1) (See Figure 12-6, Figure 12-7, and Figure 12-8.
DS26521 Single T1/E1/J1 Transceiver Figure 12-6. Receive Framer Timing—Backplane (T1 Mode) RCLK t D1 F-BIT RSER/RSIG t D2 RCHCLK t D2 RCHBLK t D2 RFSYNC/RMSYNC t D2 RSYNC 1 NOTE 1: RSYNC IS IN THE OUTPUT MODE. NOTE 2: NO RELATIONSHIP BETWEEN RCHCLK AND RCHBLK AND OTHER SIGNALS IS IMPLIED.
DS26521 Single T1/E1/J1 Transceiver Figure 12-7. Receive-Side Timing, Elastic Store Enabled (T1 Mode) t SL t SH RSYSCLK t SP t D3 SEE NOTE 3 RSER/RSIG t D4 RCHCLK t D4 RCHBLK t D4 RMSYNC t D4 1 RSYNC t HD t SU RSYNC2 NOTE 1: RSYNC IS IN THE OUTPUT MODE. NOTE 2: RSYNC IS IN THE INPUT MODE. NOTE 3: F-BIT WHEN RIOCR.4 = 0, MSB OF TS0 WHEN RIOCR.4 = 1. Figure 12-8.
DS26521 Single T1/E1/J1 Transceiver Table 12-4. Transmit AC Characteristics (VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Note 1) (See Figure 12-9, Figure 12-10, and Figure 12-11.
DS26521 Single T1/E1/J1 Transceiver Figure 12-9. Transmit Formatter Timing—Backplane t CP t CL t CH TCLK t D1 TESO t SU TSER/TSIG t HD t D2 TCHCLK t D2 TCHBLK t D2 TSYNC1 t SU t HD TSYNC2 NOTE 1: TSYNC IS IN THE OUTPUT MODE. NOTE 2: TSYNC IS IN THE INPUT MODE. NOTE 3: TSER IS SAMPLED ON THE FALLING EDGE OF TCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED. NOTE 4: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS DISABLED.
DS26521 Single T1/E1/J1 Transceiver Figure 12-10. Transmit Formatter Timing, Elastic Store Enabled t SP t SL t SH TSYSCLK t SU TSER t D3 t HD TCHCLK t D3 TCHBLK t SU t HD TSSYNC NOTE 1: TSER IS ONLY SAMPLED ON THE FALLING EDGE OF TSYSCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED. NOTE 2: TCHCLK AND TCHBLK ARE SYNCHRONOUS WITH TSYSCLK WHEN THE TRANSMIT-SIDE ELASTIC STORE IS ENABLED. Figure 12-11.
DS26521 Single T1/E1/J1 Transceiver 12.2 JTAG Interface Timing Table 12-5. JTAG Interface Timing (VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Note 1) (See Figure 12-12.
DS26521 Single T1/E1/J1 Transceiver 12.3 System Clock AC Characteristics Table 12-6. System Clock AC Charateristics (See Note 1.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 1.544 REF_CLK Frequency MHz 2.048 REF_CLK Duty Cycle Gapped Clock Frequency 40 (Note 2) Gapped Clock Duty Cycle 43 40 Note 1: The timing parameters in this table are guaranteed by design (GBD). Note 2: The gapped clock is output on the RCHCLK pin when RESCR.6 = 1.
DS26521 Single T1/E1/J1 Transceiver 13. JTAG BOUNDARY SCAN AND TEST ACCESS PORT The DS26521 IEEE 1149.1 design supports the standard instruction codes SAMPLE:PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. See Table 13-1. The DS26521 contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
DS26521 Single T1/E1/J1 Transceiver 13.1 TAP Controller State Machine The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of JTCLK. See Figure 13-2. 13.1.1 Test-Logic-Reset Upon power-up, the TAP controller is in the Test-Logic-Reset state. The instruction register contains the IDCODE instruction. All system logic of the device operates normally. 13.1.2 Run-Test-Idle The Run-Test-Idle is used between scan operations or during specific tests.
DS26521 Single T1/E1/J1 Transceiver 13.1.11 Capture-IR The Capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is HIGH on the rising edge of JTCLK, the controller enters the Exit1IR state. If JTMS is LOW on the rising edge of JTCLK, the controller enters the Shift-IR state. 13.1.
DS26521 Single T1/E1/J1 Transceiver Figure 13-2.
DS26521 Single T1/E1/J1 Transceiver 13.2 Instruction Register The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the TAP controller enters the Shift-IR state, the instruction shift register will be connected between JTDI and JTDO. While in the Shift-IR state, a rising edge on JTCLK with JTMS LOW will shift the data one stage towards the serial output at JTDO.
DS26521 Single T1/E1/J1 Transceiver 13.3 JTAG ID Codes Table 13-2. ID Code Structure REVISION ID[31:28] DEVICE CODE ID[27:12] MANUFACTURER’S CODE ID[11:1] REQUIRED ID[0] DS26521 Consult factory 0000000010001000 00010100001 1 DS26522 Consult factory 0000000010001001 00010100001 1 DEVICE 13.4 Test Registers IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. An optional test register has been included with the DS26521 design.
DS26521 Single T1/E1/J1 Transceiver 14. PIN CONFIGURATION SPI_SEL 1 BTS 2 SCANMODE 3 SCAN_EN 4 ATVDD 5 TTIP 6 TRING 7 ATVSS 8 ARVDD 9 RSYNC RMSYNC/RFSYNC RSIG AL/RSIGF/FLOS RLF/LTC RCHBLK/CLK 53 52 51 50 49 RCLK 56 RSYSCLK RSER 57 54 TCHBLK/CLK 58 55 TSSYNCIO TSYNC 61 TSIG TSYSCLK 62 59 TCLK 63 60 TSER 64 Figure 14-1.
DS26521 Single T1/E1/J1 Transceiver 15. PACKAGE INFORMATION (The package drawing(s) in this data sheet may not reflect the most current specifications. The package number provided for each package is a link to the latest package outline information.) 15.
DS26521 Single T1/E1/J1 Transceiver 16. DOCUMENT REVISION HISTORY REVISION DESCRIPTION 012406 New product release. 030206 Added further description to SCAN_EN and SCANMODE pin descriptions to clarify that the pins should be connected to ground for normal operation. Updated Figure 8-17. 111606 Updated entire data sheet for typos and clarity to match the TEX-family data sheets (DS26522, DS26524, DS26528).